Design and Implementation of Asymmetrical Multilevel Inverter With Reduced Components and Low Voltage Stress

Multilevel inverters with a high device count, low boosting and DC voltage imbalance are all common problems exists in the traditional topologies. In this article, a new single-phase asymmetrical multilevel inverter (MLI) that can generate 33 levels at the output with fewer components and lower total standing voltage (TSV) at the switches is presented. The multiple input sources of the proposed inverter make it suited for the use in renewable energy generating systems which have a variety of DC sources. The stress distribution among the switches is investigated that reduces the use of high rated devices with which overall cost of the inverter gets reduced. The topology can be extended by adding the circuits in series for higher levels. The performance of the inverter is calculated considering a variety of critical parameters such as TSV, cost function (CF), power loss, and efficiency calculations. The MLI is tested under dynamic load conditions with sudden load disturbances with a range of combinational loads and it has been determined to be stable throughout its operation. A detailed comparison is made based on stress across the switches, stress distribution, switches count, DC sources count, gate driver circuits, component count factor, TSV, CF, and other existing topologies using graphical representations and shown to be cost-effective and superior in all aspects. The total harmonic distortion (THD) derived from simulation and experiment complies with IEEE standards. The proposed framework has been developed in MATLAB/Simulink and tested in a laboratory environment with hardware.


I. INTRODUCTION
The academic and industrial sectors are very interested in multilevel inverters. Multilevel strategies improve the inverter's output power quality while also allowing for higher voltage levels in power electronic circuits. [1]. Low-medium rated semiconductor switches are available on the market and can be used to achieve higher power levels. A sequential connection of switches is required to create a high rated converter with standard two-level operation. Because of their benefits, multilevel inverters are used in a variety of applications, including uninterruptible power supply systems (UPS) [2], The associate editor coordinating the review of this manuscript and approving it for publication was Zhilei Yao .
hybrid photovoltaic UPS systems [3], traction [4], ships [5], renewable systems [6], electric vehicles [7], and power quality [8]. Multilevel converters, despite their differences, frequently need a large number of switches consists of greater losses and costs, and use significant modulation techniques. Many research studies are being undertaken to solve these issues.
Neutral point clamped (NPC) MLIs, flying capacitor (FC) MLIs, and cascaded H-bridge (CHB) MLIs are the three primary types of MLIs [9]. Over the last two decades, the benefits and drawbacks of the three types of MLIs outlined above have been thoroughly researched. In summary, the major disadvantages of these MLIs include altering the voltage in NPC, the control complexity for making a balance in VOLUME 10, 2022 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ voltages in the FC, and the more switches count and independent excitations in CHB. Cascaded MLIs may provide more voltage levels, and dependability than other MLI topologies due to their modular architecture. [10]. Asymmetric MLIs are topologies with uneven dc-link voltages, whereas symmetric cascaded inverters have equal dc sources. Asymmetric topologies may give a wider range of output voltage values than symmetric topologies. These are not possible to implement practically and difficult to balance the supplied power across every source of the circuit with the load with the existence of two or more excitations with same magnitudes [11]. Many techniques for opting the size of input sources are described to get a larger output levels asymmetric type of design. Reference [12] Describes a single-sourced MLI that employs various types of configurations such as equal and unequal sources, series and parallel voltage balancing methods in capacitor in order to double the magnitude of the input voltage. The inverter TSV is relatively low because there is no extra H-bridge circuit. Utilizing two unequal sources and dual capacitors, the inverter [13] can able to produce 13 levels at its output. Because of the connection type as cascade with the other modules offers greater levels at the output without the use of an extra H-bridge, reducing stress across the switches in this type of configuration. MLI [15] covers the usage of T-type architecture and cross sectional-connected units to product the output. Due to the extra power switches in this configuration in order to facilitate charging and discharging behaviour of the capacitor, stress across the switches is high. In recent years, scholars have proposed a slew of new architectures. A couple of them are examined thoroughly. An H-bridge was proposed as part of a framework consisting of cascading basic components in [13] due to the high conduction losses, large number of switches are enhanced in this arrangement. The topology in [14] finds a second-order connection between the peak inverse voltages of the circuit (PIV) with levels count. As a result, the inverter is expensive and unsuitable for applications requiring high voltage. Each basic unit consists of a unique construction comprised of many bidirectional switches. A new cascaded MLI topology is presented in [15], which is aimed to reduce the number of switches and dc sources by utilizing three algorithms. The selective harmonic elimination modulation is used to produce the pulses to the switches for getting the desired output. In [16] and [17], a switched capacitor based MLI is proposed, which consist of high gain and energized with a single DC source. The proposed MLI has reduced switch count and has superior performance and cost-effective. In [18], a novel 21-level MLI is designed with reduced switch count having less TSV and cost function, the MLI is fed to solar PV applications. The topology in [19] introduced a novel framework that includes two algorithms for selecting dc sources. However, the symmetric operation has a high number of switches. An alternative topology is shown in [20].
The cascaded structure is addressed in [21] with a switched capacitor based single phase MLI is designed with superior performance compared with the respective MLI topologies.
A reduced switch count single phase MLI is presented in [22] where the performance evaluation of the parameters is calculated and holds superior aimed to design MLI with less components count and to minimize the standing voltage. The architecture, as illustrated in [23], uses additive and subtractive techniques to generate nine level output from two unequal dc excitations. Reference [23] Offers a series-connected linear dc-source value development. In contrast, this architecture requires higher switch voltage ratings and high stress across the switches on the inverter. In [24], the authors suggested a novel architecture with reduced switch count MLI, where the MLI has outstanding performance in reducing the TSV value. The topology presented in [25] proposed a new MLI with a redesigned H-bridge and numerous dc-sources.
Although these topologies require fewer gate driver circuits, bidirectional type of power electronic switches tends to have a gradual increase of switches and size of the inverter. Another approach is to use modular-based topologies with an integrated polarity switcher to reduce the inverter's standing voltage. The ST-type architecture employs 12 power electronic switches to provide a seventeen levels of output voltage, with input excitation magnitudes to be opted using the trinary progression technique. Even though these topologies offer an output levels count with a limited sources count, they have a more switches count [26]. Each module in [27] delivers 9 level and 17 level voltage outputs in symmetric and asymmetric ways with 10 power switches and 4 input sources. Another system proposed by [28] uses 10 switches to generate seventeen levels. Despite the use of asymmetric dc-sources in this system, the maximum stress across the power electronic switches holds significant. Another reduced switch count topology presented in [29] with a less switching frequency and less TSV.
A 33-level asymmetric MLI architecture is proposed and implemented in this work, with minimal voltage stress on switches and lower THD. Along with the power loss estimates, the influence of voltage stress on the topology is addressed in depth. The number of switches, voltage levels, DC source count, the voltage stress on switches, power loss, efficiency, THD, and circuit complexity are used to determine MLI performance. The developed MLI is built using simulations in environment of MATLAB/Simulink and implemented with a experimental prototype in a laboratory, where it is evaluated under various loaded circumstances such as Resistive load, inductive load, combination of both resistive and inductive loads as well as dynamic loading conditions. The MLI performance is compared to that of different current topologies, both traditional and modern. Where a separate DC source excitation is available, the designed MLI is applied for grid integrated renewable energy systems and electric vehicles.
The remainder of the paper is formulated as: analysis and implementation of the developed 33-level MLI configuration and the extended topology are presented in section-2. Performance evaluation of the MLI with various parameters like TSV, cost function, power loss and efficiency  calculations are presented in section-3. The comparisons and application is presented in section-4. The both simulation and experimental results with discussions are presented in section-5. Section-6 is followed by the conclusions and future scope.

II. PROPOSED INVERTER TOPOLOGY
In this section, a fundamental unit and the generalized extended structure of the proposed 33-level MLI architectures are implemented. Several parameters of the MLI are designed based on the design equations, switching states, load current paths, maximum blocking voltage (MBV), total standing voltage (TSV) calculations with a reference output voltage waveform. Several MLI parameters are calculated which are intended to estimate the performance of MLI.
The circuit configuration of the developed 33-level MLI topology is represented in FIGURE 1. It has eight unidirectional and four bidirectional semiconductor switches with four input DC voltage sources. The basic unit of the proposed architecture can able to generate thirty-three levels of voltage at the output. The magnitudes of the input DC sources V 1 , V 2 , V 3 , and V 4 are selected in the ratio of 1:2:4:9 [31] with a V dc value of 25V.
The multiple inputs with unequal sources make the inverter suited for the use in renewable energy generating systems which have a variety of DC sources. In practical applications like photovoltaic generation systems, the PV panels are integrated using DC-DC converters to optimize the output voltage waveform.
The required DC sources N dc are mathematically related to the number of levels N L used by the equation The number of switches N SW required are may be mathematically related to the number of levels N L used by the equation The required gate driver circuits N gd are given by The maximum voltage output produced V 0,max is given by

A. OPERATION OF THE PROPOSED TOPOLOGY
The basic unit generates 33 number of voltage levels, including 0V, ±1V dc , ±2V dc , ±3V dc , ±4V dc , ±5V dc , ±6V dc , ±7V dc , ±8V dc , ±9V dc , ±10V dc , ±11V dc , ±12V dc , ±13V dc , ±14V dc , ±15V dc and ±16V dc at its output with a step size of V dc with the DC voltage sources of   in TABLE 3. Therefore, for one basic unit of MLI, n = 1, the switches count N SW is 12, the input DC sources count N dc is 4 and the total number of the level N L is 33 with a load voltage of V 0 = 400V. The maximum output voltage levels for the implemented 33-level inverter configuration are ±16V dc , which can be accessed from equation (4). The simulation results of output voltage, current waveform and THD are shown in FIGURE 12, FIGURE 13 and FIGURE 14 respectively.
The functioning of the switches in Mode-1 of the circuit are S 2 , S 3 , S 6 , S 7 , S 9 , and S 12 are in conduction in producing a load voltage of 16 V dc and the rest of the switches are inoperative, where the voltage stress occurs across the switches on S 1 , S 4 , S 5 , S 8 , S 10 , S 11 . Out of these switches, the maximum stress occurs on a switch S 1 with 13V dc stress. The operating of the switches in Mode-2 are S 2 , S 3 , S 6 , S 7 , S 9 and S 11 are in conduction in producing a load voltage of 15 V dc and the rest of the switches are inoperative, where the voltage stress occurs across the switches on S 1 , S 4 , S 5 , S 8 . Out of these switches, the maximum stress occurs on a switch S 1 with 13V dc voltage stress. The operating of the switches in Mode-3 of the circuit are S 2 , S 3 , S 6 , S 8 , S 9 and S 12 are in conduction in producing a load voltage of 14V dc and the rest of the switches are inoperative, where the voltage stress occurs across the switches on S 1 , S 4 , S 5 , S 11 . Out of these switches, the maximum stress occurs on a switch S 1 with 13V dc voltage stress. The operating of the switches in Mode-4 of the circuit are S 2 , S 3 , S 6 , S 7 , S 10 and S 12 are in conduction and generates a load voltage of 13V dc and the rest of the switches are inoperative, where the voltage stress occurs across the switches on S 1 , S 4 , S 5 . Out of these switches, the maximum stress occurs on a switch S 1 with 13V dc voltage stress. The operating of the switches in Mode-5 of the circuit are S 2 , S 4 , S 6 , S 7 , S 9 and S 12 are in conduction and generates a load voltage of 12V dc and the rest of the switches are inoperative, where the voltage stress occurs across the switches on S 1 , S 5 , S 8 , S 10 , S 11 . Out of these switches, the maximum stress occurs on the switches S 1 and S 5 with 9V dc voltage stress. The operating of the switches in Mode-6 of the circuit are S 2 , S 4 , S 6 , S 7 , S 9 and S 11 are in conduction and generates a load voltage of 11V dc and the rest of the switches are inoperative, where the voltage stress occurs across the switches on S 1 , S 5 , S 8 , S 10 , S 12 . Out of these switches, the maximum stress occurs on the switches S 1 and S 5 with 9V dc voltage stress. The operating of the switches in Mode-7 of the circuit are S 2 , S 4 , S 6 , S 8 , S 9 and S 12 are in conduction and generates a load voltage of 10V dc and the rest of the switches are inoperative, where the voltage stress occurs across the switches on S 1 , S 5 , S 7 , S 10 , S 11 . Out of these switches, the maximum stress occurs on the switches S 1 and S 5 with 9V dc voltage stress. The operating of the switches in Mode-8 of the circuit are S 2 , S 4 , S 6 , S 8 , S 9 and S 11 are in conduction and generates a load voltage of 9V dc and the rest of the switches are inoperative, where the voltage stress occurs across the switches on S 1 and S 5 . Out of these switches, the maximum stress occurs on the switches S 1 and S 5 with 9V dc voltage stress. The operating of the switches in Mode-9 of the circuit are S 2 , S 4 , S 6 , S 7 , S 10 and S 11 are in conduction and generates a load voltage of 8V dc and the rest of the switches are inoperative, where the voltage stress occurs across the switches on S 1 , S 5 , S 9 , S 12 . Out of these switches, the maximum stress occurs on the switches S 1 and S 5 with 9V dc voltage stress. The operating of the switches in Mode-10 of the circuit are S 2 , S 4 , S 6 , S 8 , S 10 and S 12 are in conduction and generates a load voltage of 7V dc and the rest of the switches are inoperative, where the voltage stress occurs across the switches on S 1 , S 5 , S 7 , S 9 . Out of these switches, the maximum stress occurs on the switches S 1 and S 5 with 9V dc voltage stress. Similarly, the remaining levels along with negative voltage levels are obtained as per the switching sequences represented in TABLE 2. Some applications such as solar PV systems and energy storage systems are suitable for the proposed inverter. The typical 33-level expected reference voltage waveform at the output and respective gate pulses are represented in FIGURE 3. The gate pulses are produced in MATLAB/Simulink using the round-robin condition (staircase modulation approach). The staircase Modulation technique is considered than the traditional PWM technique because of its major benefits such as less complexity and lesser switching losses. This is applied for both high rated MLIs, with higher voltage levels (N) and low rated MLIs. Here forth, this technique is the most common and famous strategy for specifically multilevel inverters. Also, this technique is the best alternative for the Sine PWM switching technique with its reduced losses for the MLIs with higher ratings (N). While the symmetric type MLIs are common in general, utilizing the asymmetric type MLIs with a cascaded H-Bridge further reduces the total harmonic distortion (THD) value.
The waveform generated by staircase modulation technique, its generalized quarter-wave representation is given in FIGURE 4, which consists of M desired steps per quarterwave, and one optional extra half-step appearing at the origin. For every kth step appearing at the phase switching angle αk, consists of a normalized width and height concerning DC supply voltage ratio of pk. The phase switching angle is α is given as α = {α1, α2, . . . α, . . . αM } and the DC supply voltage ratio is given as p = {p1, p2, . . . pk, . . . pM }, which are in degrees and per unit values respectively. To provide even values of N, an extra half-step with a value of p0/2, appearing at 0th phase angle, which is α0 = 0. The total number of phase switching angles per quarter-wave M is given as M = (N-1)/2 excluding α0, is related to N [30].

B. EXTENDED CASCADED STRUCTURE OF THE PROPOSED MLI
The fundamental unit of the developed MLI configuration can be connected in cascade typed of connection in order to increase the number of levels at the output. The extendable generalized MLI architecture for higher levels of output is shown in FIGURE 5. An efficient opting of DC sources in asymmetric type of operation, the cascaded structure can able to produce a larger levels of voltage at the output. Equations for determining the switches count, TSV and driver boards and the variance of selection is provided in TABLE 3, where 'n' indicates the fundamental unit count.
The parameters for the cascaded connection of the fundamental units are as follows: The DC sources N dc required for the extended topology is assessed as The extended topology produces a higher number of levels N L , which are calculated as VOLUME 10, 2022 The voltage at the load terminals of an extended topology is calculated as The maximum output voltage for the developed extended MLI structure is be accessed using equation (9) V 0,max = ± N L − 1 2 The total number of DC sources, where the DC sources count is N dc = 4n. The TSV of the extended MLI is given by The sum of all maximum blocking voltages across the switches is used to compute the TSV.

III. PERFORMANCE EVALUATION
The proposed 33-level MLI performance can be evaluated by considering the parameters of TSV, cost function (CF), impact of TSV on the circuit, total harmonic distortion (THD), power losses and efficiency calculations. Less TSV across the switches has numerous advantages, including lower losses and the ability to use a low-rated switch, which makes the inverter cost-effective. The following parameters are used to compute the performance parameters:

A. TSV CALCULATION
The total standing voltage of the switches plays a major role in determining the cost effectiveness and efficiency of the MLI. By lowering the stress across the semiconductor switches, the cost of the inverter architecture gets decreased [26]. The maximum voltage stress on a power device during the off state is described as the standing voltage. The sum of all maximum blocking voltages across the switches is the total standing voltage. The TSV can be evaluated based on the operating modes shown in FIGURE 2. The maximum voltage blocking capacity of S 1 is determined using the blocking voltage of S 1 as an example at V 0 = ±16V dc or ±15V dc or ±14V dc or ±13V dc . S 1 is turned off at all of these voltage levels. V 3 and V 4 apply a blocking voltage to S 1 . The voltage stress across the bidirectional switches are Vs bi = V i /2, where i = 1, 2, 3 . . . .n. The stress across each individual bidirectional switch is represented as follows: The voltage stress across the unidirectional switches are V Suni = V i , where i = 1, 2, 3 . . . .n. The stress across each individual unidirectional switch is represented as follows: MBVs 7 = V S7 = V 2 = 2V dc MBVs 9 = V S9 = V 1 + V 2 = 3V dc MBVs 11 = V S11 = V 1 = 1V dc MBVs 12 = V S12 = V 1 = 1V dc FIGURE 6 shows a graphical representation of MBV across all switches. The total maximum blocking voltages across all switches is used to compute the TSV. Hence TSV is calculated from the equation (14) TSV = n i=1 MBV Si TSV = MBVs 1 + MBVs 2 + · · · · · · · · · .. + MBVs 12 TSV = 6.5V dc + 13V dc + 4V dc + 2V dc + 9V dc + 9V dc + 2V dc + 1V dc + 3V dc + 1.5V dc + 1V dc + 1V dc = 53V dc (14) The TSV per unit (TSV pu ) is the ratio of the total TSV to the maximum voltage levels of the proposed MLI, can be obtained mathematically from the following equation (15) TSV PU = V TSV V OMAX (15) where TSV PU = 3.31.
The impact of stress distribution on the switches is represented in FIGURE 7 and is calculated based on the TSV and MBV values of the power switches, which is known as normalized voltage stress. This represents the amount of 3502 VOLUME 10, 2022  stress distribution among the switches. It is the ratio of voltage stress over a single switch to circuit's maximum stress [27], which is calculated from equation (16).

NVS =
Actual voltage stress across switch Maximum voltage stress in the circuit (16) The voltage stress across each power switch along with the maximum stress for 33-level MLI is represented in   have maximum stress of voltage with 13V dc and 9V dc with a NVS of 100 % and 69.23% respectively. Power switch S 9 have stress of 3V dc and NVS of 23.07 %, which is greater than the minimal NVS. The stress on the switch S 3 is 4V dc with a NVS of 30.76 %, which is less than the maximum NVS. The stress on switch S 10 is 1.5V dc with a NVS of 11.53%, which is under minimum NVS. The stress on the switch S 1 is 6.5V dc with a NVS of 50%, which is half of the maximum NVS. The overall stress distribution of the circuit is represented in TABLE 5. The four switches S 1 , S 2 , S 5 , S 6 experience a stress of 31V dc , which is 58 % of the total stress distribution, while the remaining eight switches S 3 , S 4 , S 7 , S 8 , S 9 , S 10 , S 11 , S 12 experience a stress of 22V dc , which is 42 % of the total stress distribution in the proposed 33-level MLI structure. Although switch stress is unequally distributed in the developed structure, 50% of the switches experience minimum stress with an MBV of 16.03%, 25% of the switches experience maximum stress with an MBV of 58.5%, and the remaining 25% of the switches experience intermediate stress with an MBV of 25.47%. As a result, the suggested 33-level MLI provides effective sharing of stress among the power switches. Also the topology makes effective use of as many DC sources and switches as possible with lowering the TSV and cost of MLI. The graphical representation of stress distribution is shown in FIGURE 8.
Based on the stress distribution across the switches, it is found that eight switches experience less stress and hence these are selected with low voltage rating, the cost of the switches gets reduced. The remaining four switches experiences high stress, high rated switches are selected, the cost gets increased. Therefore variable rated switches are VOLUME 10, 2022 operating in the circuit reduces the size, complexity and overall cost of the inverter.

B. COST FUNCTION
The cost function (CF) plays an important role in determining the best suited MLI based on the application. Several factors may be used to calculate the cost function, including the switches count N S , the DC sources count N dc , the diodes count N D , the capacitors count N C , gate drivers count N gd and TSV. As a result, the cost factor is determined using the following equation (17) [28]. (17) The weight coefficient α is always larger than 1 and less than unity. The cost factor is estimated in the developed 33-level MLI with the value of 0.5 (1) and 1. The cost function per level factor is compared with other modern existing topologies and found to be less compared with all topologies. Hence the proposed MLI is found to be cost-effective.

C. POWER LOSS CALCULATION
The power loss of the power electronic switches is the combination of conduction and switching losses. These are calculated based on the approach provided in [17] may be assessed for the developed topology. Conduction losses occurs when semiconductor devices conduct at the on-states owing to voltage drop. Conduction losses are calculated by multiplying the semiconductor device's V on (t) and I(t) during on-state. The calculations are calculated and represented in TABLE 6. The variation of efficiency with respect to the load is represented in FIGURE 9.
The total losses are made up of conduction and switching losses related to switches. Equation (18) may be used to determine the conduction losses for the switches.
The IGBT switch has a voltage drop of V S , whereas diodes have a voltage drop of V d . The equivalent resistance of a diode is R d and R S is the switch resistance. The following is a generalized relationship for estimating conduction power losses (P cl ) using the switces N IGBT and diodes N d at a specific time are calculated from equation (19).
The switching losses are calculated from the equation (20).   The energy utilized by the switches is E on and E off during conduction and isolation of the switches respectively. The following formula is used to calculate total power losses (P loss ): The following equation is used to compute the efficiency (η). η = P out P in = P out P out + P loss (22) where the output and input powers are denoted by P out and P in respectively. The following equation can be used to calculate power:

IV. COMPARISON ANALYSIS AND APPLICATION
The proposed MLI is validated by comparing with other structures based on several key parameters such as the switches count (N S ), gate drivers (N gd ), DC sources (N dc ), diodes (N D ), capacitors (N C ), total standing voltage (TSV pu ), components count per level factor (CC/L), cost function per level count (CF/L), and the number of levels to switches ratio (N L /N S ). Table 7 summarises the relevant comparisons, while FIGURE 11 represents the graphical representations of the respective comparisons. The proposed 33-level MLI is found to be efficient in all parameters and cost-effective when compared to other topologies. The following are the detailed comparisons. The DC sources count has a major impact on the  topology application towards practical implementation. With higher DC sources, the cost of the circuit and voltage stress gets increased. TABLE 7 shows that topologies [31]- [33] have a single input source, but the overall component count is quite high due to the utilization of more number of capacitors as well as diode. The proposed architecture is shown to have fewer DC sources and total components, making it a viable choice for improved power quality. Table 7 shows the number of levels to switches (N L /N S ) ratio, which is compared to all other topologies [27] and the graphical representation is shown in FIGURE 10. This ratio determines the topology's overall cost and efficiency. The higher the N L /N S ratio, the fewer switches are used, and the potential of generating greater voltage levels increases. As a result, higher output levels may be achieved with fewer switches.
The proposed topology has a rating of 2.8, greater than other existing topologies. The developed topology is highly suited for renewable energy applications, based on the previous explanation.
TSV pu plays a crucial role in calculating the inverter's total cost by estimating the rating of the IGBT switches concerning the stress across the switches. The higher the load on the switches, the higher the rating switches must be used, which increases the switches cost. Hence, the overall cost of the circuit gets increased. In the proposed topology, TSV is 53V dc and TSV pu is 3.31, which is less compared with all other existing topologies and hence the stress across the switches is less. The relative stress distributions among the switches are represented in FIGURE 7 and FIGURE 8. FIGURE 10 shows the graphical representation of the TSV pu vs N L /N S ratio comparison. Based on the stress across switches, it can be inferred that the proposed topology provides high performance and is cost-effective.
The cost function of the MLI plays a vital role in obtaining the cost-effectiveness of the topology with a variation of weight coefficient α, the variation of the value of α is from 0.5 (<1) and 1.5 (>1). In the developed 33-level MLI, the cost function is 3.11 for α = 0.5 and 3.51 for α = 1.5, which VOLUME 10, 2022 is lesser compared with the other topologies and found to be cost-effective.
The topology in [40] has a competitive performance with the proposed MLI in several parameters like components count per level, THD, TSV and cost function. Even though the N L /N S value is higher than the proposed MLI, the overall components count factor is high, which is inferior to the proposed MLI and holds better results in all the parameters shown in Table 7. The topology in [43] has the cost function, which is nearer to the proposed MLI parameter with a TSV PU of 5.86. The components count factor is having a nearer value but the THD and all other parameters hold inferior compared with the proposed MLI. The topology represented in [44] has very closer TSV PU value but the overall performance parameters of the proposed MLI hold superior with less cost function. The topology represented in [45] has nearer components count factor but the overall performance of the proposed MLI holds superior. Hence the above mentioned topologies provides a competitive performance with the proposed MLI in some parameters but the overall performance parameters holds superior to that of the all topologies represented in TABLE 7. The graphical representation of the respective comparisons are represented in FIGURE 10 and FIGURE 11 for the easy identification of the performance of the proposed MLI.
According to the parametric comparisons above, the suggested MLI outperforms the modern existing topologies. Following comparisons show how the proposed inverter architecture reduces the number of required switches, TSV of the switches and driver circuits. These significant benefits might lead to the MLI topology's overall cost and installation area being reduced, making it cost-effective. FIGURE 11 represents the results of the various comparisons.

A. APPLICATION OF THE PROPOSED MLI
The proposed reduced switch count MLI is an alternative for the traditional MLIs in industrial requirements due to the wide range of operation with the modulation index. Individual PV panels with varied ratings are supplied into all four input sources of the proposed MLI, which correspond to the ratings of the DC sources [22]. In order to achieve this, some control objectives should be achieved such as the inverter must maintain optimum power quality in accordance with grid constraints, reduce harmonic distortions at the output ac voltage waveform, and extract maximum power from solar panels under various irradiance conditions in order to provide an efficient and stable output throughout its operation. Furthermore, the extracted power has been transferred to the output with a unity power factor in order to maintain reliability.
Because different solar panel ratings are used for different DC sources, an efficient maximum power extraction is used to harvest power under varying irradiance situations. In this aspect, the power factor control of the system plays a major role in transferring power from the solar panels to the grid, which is closer to a high power factor of 0.95. Reactive power  consideration is not required in these systems because the inverter rating is low as per IEC 929-2000 and IEC 62109-2 standards. Furthermore, because the suggested MLI has a greater number of redundant switching states, it is more suitable for solar PV applications in terms of fault ride-through capability and power balance.

V. RESULTS AND DISCUSSION
The developed 33-level MLI is designed and implemented in a laboratory illustrated in FIGURE 22, is used to test the inverter's performance. For the developed MLI configuration, the input dc sources utilized are V 1 = 25V, V 2 = 50V,     experimentally. The hardware prototype of the designed experimental circuit is illustrated in FIGURE 16 along with the entire setup is represented in FIGURE 22. The system consists of four CM75DU-12, 600V, 75A IGBTs with four input DC sources V 1 , V 2 , V 3 , and V 4 that generates 33 levels and a 400V output voltage at 50Hz. Utilizing dSPACE   RTI1104 board, the pulses are generated from the digital input and output ports to operate the IGBT switches. The gate driver in the range of 4 to 16V adds to the pulse width modulation design. The 15V pulse activates the power semiconductor switches. The experimental result of an output voltage is shown in FIGURE 17, which is V 0 = 400V, and FIGURE 18 represents the hardware results with the combination of output voltage V 0 = 400V and current I 0 = 4A for the resistive load with a load resistance of 100 . Experimental THD obtained is shown in FIGURE 23, which is 2.03%, similar to that of the simulation THD. The MLI is tested using a single phase motor load with an inductance L = 187mH produces the output voltage and current V 0 and I 0 of 400V and 6.8A respectively are shown in FIGURE 19.    The proposed MLI is tested for dynamic loaded conditions with various combinations like R||L with L-load variation of R-load, the respective experimental results are obtained and represented below. The case when the inverter is loaded with R-load and suddenly an inductor is added in parallel to the existing R-load, the variation is represented in FIGURE 20 and it is found that the proposed MLI is stable with the load disturbances in throughout its operation. Also the case when the inverter is loaded with L||R load and suddenly the inductive load is removed, the respective variation is represented    in FIGURE 21 and it is found that the proposed MLI is stable in the load disturbance for throughout its operation. VOLUME 10, 2022 Also when the inverter is loaded with a resistive load of 150 and suddenly the load has been changed from 150 to 100 , the respective variation in the current is shown in FIGURE 22 experimentally. Hence based on the above observations, it is found that the load voltage remains constant under all loading conditions. The simulation and experimental specifications of the proposed MLI are given in TABLE 9. The outstanding features of the proposed MLI are represented in FIGURE 25.

VI. CONCLUSION
The proposed new asymmetrical MLI topology that can able to generate 33 voltage levels is implemented with reduced components and less TSV. A detailed stress distribution across the switches is analyzed with which the low voltage rated switches are selected, which decreases the cost and size of the inverter. An extended circuit is designed for higher output voltage levels. The developed MLI is compared with other existing MLI architectures considering several parameters for estimation of its performance and found to be superior. The MLI requires fewer power switches with less DC sources count for the generation of higher output levels. TSV PU of the MLI is 3.31, only 25% of the switches are under maximum stress. Hence the cost of the inverter gets reduced. The comparisons represents that the proposed MLI has low TSV, cost-effective and efficient. As the unequal DC sources and low-rated switches are utilized in this topology, it is feasible for various hybrid energy storage and electric vehicle applications. For evaluating the performance of the MLI, it is tested for dynamically loaded conditions and found to be stable throughout its operation. Both simulation and experimental THD obtained is 2.03% with an efficiency of 95.2%, cost function α is 3.11 and 3.51 respectively, which is less when compared with other existing topologies. The proposed topology can be extended for the solar PV applications with various ratings of PV panels for the multiple inputs.