A Hybrid Switching Modulation of Isolated Bidirectional DC-DC Converter for Energy Storage System in DC Microgrid.

Isolated bi-direction DC-DC converters are widely used for energy storage systems (ESS) of DC microgrids. Particularly, a current-fed isolated bi-directional DC-DC converter (CF-IBDC) receives much attention due to its merits such as the naturally attenuated current ripple on the battery side. However, high efficiency cannot be obtained at the light and heavy load conditions under the conventional control methods. In this paper, a hybrid switching modulation is proposed to improve the power conversion efficiency of the CF-IBDC under light and heavy load conditions. The duty cycle of the secondary sides and the phase shift angle are independently controlled according to the amount of the transferred power. The control strategy is based on the optimization of zero-voltage switching (ZVS) conditions and the minimization of the circulating current in the power converter. Using the proposed control algorithm, the ZVS capability can be obtained under the entire load condition, and the circulating current can be minimized under the single phase-shift modulation (SPSM). Experimental results with a 1-kW laboratory prototype CF-IBDC validate the effectiveness of the proposed modulation algorithm.


I. INTRODUCTION
Since renewable energy resources are required for DC microgrids, and developed energy from energy resources is commonly irregular due to various operating conditions such as weather and temperature. Therefore, an energy storage system (ESS) is essential to ensure the power quality and the reliability of the power supply. To interface the ESS with the DC microgrid, an isolated bi-directional DC-DC converter is used to charge and discharge batteries in the ESS system [1]- [3]. Since the ESS consists of many battery cells which have low voltage ratings and variable voltage ranges, an appropriate converter should handle the wide voltage range and high power conversion efficiency.
Under the single phase-shift modulation (SPSM) due to the inherent zero-voltage switching (ZVS) capability and the simple control algorithm with seamless bi-directional power flow capability, a voltage-fed dual-active-bridge (VF-DAB) converter is widely adopted to bi-directional applications [4]- [7]. However, this control strategy has drawbacks such as circulating current and backflow power in the VF-DAB converter under heavy load conditions [8]- [9]. In addition, since the inductor current is highly sensitive to voltage gain and load conditions, the ZVS can be failed under light load conditions. In particular, the circulating current rapidly increases and the non-ZVS range is extended in the operating region far from the unity voltage gain.
To overcome the limitations of the SPSM, many control strategies such as pulse width modulation plus phase-shift [10]- [12], extended phase-shift, [13], dual phase-shift [14], [15] and triple phase-shift [16]- [18] modulations are proposed. By introducing internal phase-shift (PS) between the two legs of full-bridges, three-level ac waveforms on the phase voltage can be generated, so that the length of a zero-vector can be adjusted. The key technique of those modulations is to extend the degree of freedom (DoF) of the control strategy which expands the soft-switching range and reduces the circulating current, thereby reducing the conduction loss. Although ZVS can be achieved over wide load ranges using various modulation schemes, it is difficult to obtain full ZVS capability over the entire load range because of the high complexity of its implementation [15]. Since there are lots of DoFs, including the internal phase shift of the primary bridge, the internal phase shift of the secondary bridge, and the external phase shift between two ac voltages, linear interpolation can be used to determine the selection of the variables based on the lookup table in the digital signal processor (DSP). However, it can degrade the system's dynamic response.
Furthermore, the characteristics of the VF-DAB converter are not suitable for charging and discharging batteries, which requires the power conversion capability for wide voltage ranges. This is because of a relatively high current ripple from the capacitive output filter of the VF-DAB converter, which adversely affects battery life. Therefore, the VF-DAB converter should not be used directly for the battery interface and a power filter should be connected between the battery and the converter.
As shown in Fig. 1, a current-fed isolated bi-directional DC-DC converter (CF-IBDC) consists of a synchronized buck/boost converter cascaded with the DAB converter including equivalent resistance [19]. The CF-IBDC is suitable for the interface between the battery and the highvoltage DC bus since it has the power conversion availability for the wide voltage range, small output voltage ripple, and high-power conversion efficiency. Comparing with the VF-DAB converter, the CF-IBDC can expand the ZVS region under a wide voltage range since the synchronized buck/boost converter controls the output voltage based on PWM control, and it makes the effective gain of CF-IBDC unity. Also, the current-fed structure can make the current ripple in the battery side attenuated naturally, which can prolong the lifetime of energy storage.
To control the CF-IBDC over the wide-range voltage, a PWM plus phase shift (PPS) control has been proposed [20]. The output voltage is controlled by the clamping operation using the PWM technique on the low voltage side (LVS), while the duty ratio is fixed as 50% on the high voltage side (HVS). The bi-directional power flow is controlled by phase-shift modulation (PSM) between H-bridges.
However, under the light load condition, the power conversion efficiency can be poor since high current spikes and high circulating current are induced. To overcome the PPS, a PWM plus dual phase-shift (PPDPS) was proposed to reduce the conduction loss [21]. However, ZVS cannot be obtained over the entire load range. The asymmetric PPDPS control is proposed in [22] to reduce the peak current and the circulating current, but only the zero current switching (ZCS) can be achieved instead of ZVS in HVS, which increases switching losses. In [23], a modified PWM plus phase-shift (MPPS) modulation is proposed to reduce conduction losses, but ZVS cannot be achieved under light load conditions. In [24], a fixed duty control between Hbridges is proposed to obtain ZVS capability of all the switches even under no-load conditions; however, in the heavy load condition, the circulating current increases due to the existence of zero-vectors in HVS by using the modulation method used in [24].
In this paper, a hybrid switching modulation of the CF-IBDC is proposed to improve power conversion efficiency and reduce the computational burden of the control algorithm. The model analysis based on mathematical approaches is presented. The circulating current and ZVS conditions are also analyzed. The structure of this paper is as follows: In Section 2, the operational principles of the proposed hybrid switching modulation are given. In Section 3, the circulating current based on peak current, RMS current, and ZVS conditions are presented. Also, the design considerations are analyzed. In Section 4, experimental results verify the validity and the performance enhancement of the proposed hybrid switching modulation and control algorithm using a 1-kW prototype CF-IBDC. Section 5 provides a conclusion

II. OPOERATION PRINCIPILES
The schematic of the CF-IBDC is illustrated in Fig. 1. In the LVS, there are two DC inductors of LDC1 and LDC2 which make up the interleaved and synchronized bidirectional buck/boost converter. It is assumed that LDC1 = LDC2 is achieved in this paper. The inductance Ls represents the coupling inductance, which is coupled between the leakage inductance in the transformer and the external series inductance. The phase voltage of the LVS and the HVS is defined as vab and vcd, respectively. The clamping capacitor is defined as CC. The phase-shift angle between vab and vcd is normalized by π and defined as ɸPS (= ϕ/π) Fig. 2 shows the waveforms of the steady-state operations using the proposed modulation strategies for the CF-IBDC. The synchronized buck/boost converter can match the voltage gain of m (=nVCc/VO) as 1 when Vbat widely fluctuates during the charging and discharging process. On the LVS, S1-S4 control to help the clamping voltage of VCc to match the output voltage. The battery voltage of Vbat is controlled to VCc (= VO/n) by using the PWM control of bottom switches, D1 where n is the turn ratio of the transformer. The relationship between VCc and Vbat is expressed as shown in (1).

A. OPERATION PRINCIPLES OF VOLTAGE MATCHING CONTROL
Even if the unity voltage gain is not optimal in terms of the RMS phase current, the converter can achieve ZVS of all the switches at the light load when the voltage gain is unity [18]. Besides, if the gain is not unity voltage gain, the slew rate of the phase current will be steep, causing a high current spike and circulating loss. Therefore, to reduce both the switching loss and the conduction loss, the voltage gain of m is set as one in this paper and the slew rate of the phase current is zero during the positive or negative voltage overlapped period in vab and vcd.
In Fig. 2, the phase voltage of the LVS and the HVS is indicated as red and blue lines of three-level waveforms, respectively. To control the length of zero-vector on each side, an asymmetrical PWM control is employed in the LVS, and an inner phase shift between legs of the H-bridge is adopted in the HVS. The duty ratio of the HVS is defined as D2, which is like the duty ratio of the LVS. The zero-vectors duration of the phase voltage on the primary and secondary is defined as Zpri and Zsec, which are freewheeling time intervals expressed as follows: The difference between Zpri and Zsec is redefined as Zd. The non-overlapped period between the LVS and the HVS is defined as TS1 and TS2, respectively. The relation between TS1 and TS2 is expressed as follows: As following [19]- [23], many patterns have already been proposed to control the CF-IBDC using the three-level waveforms of both bridges; however, those have the following disadvantages. In the case of D1 < D2, ZVS cannot be achieved even under medium load conditions due to not enough current for soft switching.
In addition, the transferred power is also limited even if the phase-shift angle increases. Besides, under the heavy load condition, even though ZVS can be achieved, the circulating current is high to make power conversion efficiency decrease. Therefore, the case of D1 < D2 is not considered in this analysis. The theoretical concept of the proposed control algorithm is shown in Fig. 3, in which ZVS can be achieved in all the switches with low conduction loss by a small circulating current. The mode can be divided into four modes according to the output power. Each mode is controlled by only one parameter which is duty ratio or phase shift.

B. ANALYSIS OF KEY OPERATION
The power delivered from the LVS to the HVS is defined as a forward bias, whereas the power transmission from the HVS to the LVS is defined as a reverse bias. Since the forward and reverse bias are symmetric, only the forward bias is chosen as an example for the analysis in this paper. In addition, since the operating waveforms are repeated every half cycle with opposite polarity, the analysis of the phase current is only obtained in a half switching period. Finally, the reverse bias can be analyzed in the same way.

1) LIGHT-LOAD (LL) -I OPERATION
In many CF-IBDC-related papers, it has been difficult to satisfy ZVS conditions at no-load or very light load conditions. In [24], an effective modulation method was proposed to achieve ZVS even under no-load conditions. However, this method is not suitable for heavy load conditions due to the existence of the zero-voltage vector on the HVS regardless of load conditions, resulting in high circulating current and high reactive power in the converter. Therefore, the algorithm shown in [24] is employed in the proposed algorithm only for light load conditions The phase current can be derived by (5) per period.
The current of I1 and I2 in Fig. 3-(a) can be expressed as (6).
The current of I1 is only associated with variable ϕPS, and I2 is only associated with variable Zd.
The output power in LL-I mode is expressed as shown in (7).
( ) The output power is only associated with D1 and ϕPS. The peak phase current in the LL-I mode is represented as I2 where it depends on D1 and D2. In the case of the duty ratio of D2 is changed depending on D1 to maintain the constant value of Zd. Due to D1 is controlled by the battery voltage, to reduce the RMS current and peak current, Zd should be reduced. The design process of Zd is introduced in Section 3 with the ZVS conditions of the HVS. The phase angle of this mode has the range as follows:

2) LIGHT-LOAD (LL) -II OPERATION
When ϕPS reaches (D1-D2), the operating mode is changed to the light-load II (LL-II). As shown in Fig. 3-(b), this mode is the same as the PPDPS mode but the magnitude of D2 depends on D1 to maintain the fixed Zd in the LL-I mode, which is the extended LL-I mode. According to Fig. 3-(b), t0, t1, t2, t3, and t4 can be represented by D1, D2, and ϕPS as follows:

FIGURE. 3. Theoretical voltage and current waveforms of four operating modes in the proposed converter according to the control strategies: (a) & (b) Light load mode I & II -PWM plus dual phase shift mode (PPDPS) with fixed 'Zd' control, (c) Mid-load mode -PWM control, (d) Heavy load mode -PPS control.
The transmitted power in the LL-II mode is expressed as (10) The transmitted power is related to D1 and ϕPS in the LL-II mode as same as the LL-I mode. I1 and I2 in Fig. 3-(b) can be expressed as (6). Even if I1 and I2in the LL-II mode are the same as the LL-I mode, the peak current is changed from I2 to I1 as ϕPS increases. The amplitude of I2 does not change since I2 depends on Zd, which is held in overall LL mode. When ϕPS arrives at half of Zpri, half of Zsec is the same as TS2.
In this mode, the phase angle is in the range expressed by (11).
Therefore, D1 and D2 should be longer than 0.5+(D1-D2) and 0.5 to obtain the LL-II mode, respectively. Here, the range of D1 is limited to as narrow as possible since the range of D1 is proportional to the circulating current range. The circulating current can be minimized when D1 is 0.5; however, to obtain the ZVS capability, the minimum value of D1 should be greater than 0.5.

3) MEDIUM-LOAD (ML) OPERATION
When ϕPS is arrived at (D1-1/2), the entire LL mode is finished, and the operating mode is changed to the mediumload (ML) mode. Fig. 3-(c) shows the control concept of the ML mode. As the middle between the LL mode and the heavy-load (HL) mode, the ML mode connects the two modes smoothly. In the ML mode, D2 is controlled to regulate the output voltage based on the PMW control of D2 by using an inner PS modulation of the HVS. Fig. 4 shows the theoretical concept of the ML mode as output power increases. Since the waveforms of the phase voltage and the phase current in the ML mode are the same as the LL-II mode, the time interval is equivalent, which is represented in (6). The current of I1 and I2 in Fig. 3-(c) can be expressed as (12).
In the ML mode, since ϕPS is fixed, the amplitude of I1 does not change unless the battery voltage alters. Being different from the entire LL mode, I2 is changed during the ML mode. When D2 decreases until 0.5, I2 increases. The transmitted power in the ML mode is expressed as shown in (13).
From (13), since ϕPS is held as (D1-1/2) in the ML mode, the output power is only associated with D1 and D2. Before the ML mode, D2 changes according to D1 to maintain a constant Zd, while D2 in the ML mode actively changes to regulate the output voltage. As shown in Fig. 5, when D2 decreases, the transferred power increases, and the maximum power can be obtained when D2 is 0.5 in the ML mode regardless of D1. It should be noted that the several combinations of D1 and D2 are possible to transmit power to the backward bias. In Fig. 5, a gray plane shows delivered power zero. This is because D2 in the ML mode can decrease to 0.5 regardless of D1, which does not satisfy (11). Therefore, the proper range of D1 is also required with the consideration of D2. The intuitive criterion of mode change from the ML mode to the HL mode is the length of D2. When D2 reaches 0.5, the mode changes.

4) HEAVY-LOAD (HL) OPERATION
As shown in Fig. 3-(d), in the HL mode, the secondary phase voltage is a square waveform, and the transmitted power is controlled by only ϕPS control. This control strategy is the same as conventional PPS control. The time interval t0, t1, t2, and t3 can be represented only by D1 and ϕPS as follows: In addition, I1 and I2 in Fig. 3-(d) can be expressed as (15).
Since, in the ML mode, ϕPS is fixed to (D1-1/2), the output power consisting of D1 and D2 can be reorganized in terms of ϕPS, which is expressed as follows: From (16), the maximum power can be obtained when ϕPS is 0.25. In the HL mode, the range of the phase angle is expressed by (17).
To satisfy (17), D1 is limited to 0.75. Finally, to protect the reverse power transmission, the proper range of D1 is limited as (18). Fig. 6 shows the phase voltage and the phase current waveforms under the various control modulations according to the load conditions. In Fig. 6-(a) and Fig. 6-(b), a high peak current occurs under the light load condition, resulting in high conduction loss and core loss. When the PPDPS with the fixed Zd in Fig. 6-(c) is alternatively employed in this paper under the light load condition, power loss can be reduced since the duration of high peak current ends only when ϕPS reaches Zd/2.

C. CONTROL STRATEGY OF THE PROPOSED OPERATING MODE
Meanwhile, the shaded area in Fig. 6 shows the circulating current of the phase current due to the zerovector of the HVS. For the proposed control strategy in the HL mode, the PPS method is shown in Fig 6-(d) is adopted to reduce the circulating current. Since the PPS method can eliminate the zero-vector on the HVS under the heavy load condition, it can minimize circulating current and reactive power compared with Fig. 6-(e) and Fig. 6-(f). As shown in Fig. 6-(e), when the PPDPS is employed, the non-power transmission region is extended as power increases. The PPDPS with the fixed Zd under the heavy load condition shown in Fig. 6-(f) also has the same problem since the zero-vector on the HVS is maintained continuously. This is the reason why the fixed Zd with the PPDPS is limited to be used only in the light load condition. The ML mode is an intermediate process from the LL mode to the HL mode. Since in the ML mode, the PWM of D2 is only used to control the output power, the PPDPS with the fixed Zd at the light load condition can be smoothly changed to the PPS control as power increases with the simple control strategy.    Fig. 8, the control variables of D2 and ϕPS can be separated and be individually controlled, making transmitted power increases smoothly and seamlessly. The maximum power can be obtained when ϕPS is 0.25, and D2 is 0.5. As D1 is smaller, the region of the LL-II and the ML mode is reduced, and the range of the HL mode is extended. As the increase in the time interval of LL-II and the ML mode under the same power conditions, the circulating time is extended, resulting in reactive power and conduction losses increased. In order words, to obtain high efficiency, the duration of the LL-II and the ML mode should be minimized. Therefore, although the maximum value of D1 is calculated as 0.75 from (18), the CF-IBDC converter operates under the D1 range as narrow as possible.

III. EFFECTIVE HARDWARE DESIGN STRATEGY
When handling the application of the wide voltage range applications such as ESS, there is commonly a tradeoff between the conduction loss and the switching loss. Therefore, careful design considerations are required to obtain the high performance of the CF-IBDC.

1) PEAK OF PHASE CURRENT
The peak current has a significant effect on the RMS current and it also relates to the core loss of the transformer and extra series coupling inductance. To improve the efficiency, the conduction loss, and the core loss in the CF-IBDC should be minimized. Based on the analysis of peak phase current, the tendency of the conduction loss and the core loss can be estimated. The peak phase current shown in Fig. 3 (19), the peak current is expressed as the function of Zd, D1, and ϕPS. Since the proposed algorithm is employed to the PPDPS with a fixed Zd at light load conditions and the PPS algorithm at heavy load conditions, the peak current at the light load and the heavy load is equal to each control method. Therefore, the proposed algorithm has a low peak current over the entire load range compared with the conventional control strategies.

2) DISCUSSION OF PHASE CURRENT IN CIRCULATING TIME INTERVAL
As shown in Fig. 9, each waveform represents non-active power transfer stages shown in the shadowed area, which depends on the load conditions and the modulation methods. Since the proposed algorithm consis0ts of the PPDPS with the fixed Zd control in the LL mode, PWM of D2 control in the ML mode, and PPS control in the HL mode, respectively, the circulating current is required to be analyzed for each mode. For the simplification of the analysis, when the dead time of the gate signal and the resonance between the output capacitance of the power switches and the coupling inductance is negligible, the circulating current in the LL-I mode can be expressed as (20 The RMS value of the circulating current in the LL-I mode can be derived as follows: where Icir,RMS,LL-I is the RMS value of the circulating current during the LL-I mode, icLL-I is the circulating current expressed in (18). In the same way, the circulating current in the LL-II mode and the ML mode can be derived as shown in (22) The RMS value of the circulating current at the LL-II mode can be obtained as shown in (23 Since the shape of the phase current is the same as the case of the LL-II mode, the circulating current and the RMS current can be obtained by replacing Zd with (D1-D2)T in (22) and (23). Since the zero-vector in HVS is zero in the HL mode, the circulation time interval does not exist. As shown in Fig. 6, even if the peak current shown in Fig. 6-(c) is lower than that shown in Fig. 6-(a) and Fig. 6-(b), the circulating time interval in Fig. 6-(c) is larger than that in Fig. 6-(a) and Fig. 6-(b). Therefore, the proper range of D2 should be decided. Fig. 9 shows the circulating region according to D2. As D2 is set far from 0.5, the circulating time interval increases. Since the value of D2 at the LL mode is determined by D1, the maximum value of D1 should be as small as possible with a suitable voltage matching control strategy.

1) LOW VOLTAGE SIDE (LVS)
Since the CF-IBDC should handle the wide range voltage, the current-fed structure of the battery connected side and the DC bus interface is used as shown in Fig. 1. Therefore, the ZVS condition is different from each side. Fig. 10 shows theoretical switching waveforms in the LVS containing the DC filter current and the dead time duration. In Fig. 10, the maximum and minimum values of the DC filter inductor current are indicated by the phase current. The ZVS criteria of the power switches are indicated as blue circles. Since the switch current in the LVS is related to the filter current, the output capacitance of the switches in the LVS, Coes,LVS, is charged and discharged by the current difference between iLDC and iLS during the dead time. The ZVS conditions can be derived by the relationship between the phase current and the filter current as follows: where td is the dead time duration, ILDC,max and ILDC,min are the maximum and minimum value of the DC filter current, respectively, and Imin,req,L is the desired minimum current for fully charging or discharging Coes,LVS. The maximum and minimum values of the DC filter current can be expressed as follows: where ILDC is the average current passing through the DC filter, which can be derived by the average input current of the boost converter, Iout/(1-D), where D is the duty ratio of power switches. According to Fig. 10 and (24), the upper switches in the LVS, S1 and S2, are easier to obtain the ZVS capability than the lower switches in the LVS, S3 and S4, which is indicated in the dotted circles in Fig. 10 Fig. 11 shows the criteria of the DC filter inductance for the ZVS capability according to Vbat and output power. In Fig. 11, when the inductance is less than the boundary area, the ZVS capability in the LVS is obtained. It is most difficult to obtain the ZVS capability when Vbat = 48 V at the no-load condition. If LDC1 and LDC2 are small enough, the ZVS capability of the LVS switches can easily be obtained; however, the peak current and the RMS current of the DC filter increase, which causes high conduction loss. Therefore, the DC filter inductance should be designed as large as possible to obtain ZVS in the LVS.

1) HIGH VOLTAGE SIDE (HVS)
Being different from the ZVS condition of the LVS switches, that of the HVS switches only depends on the phase current. The basic ZVS condition of the HVS switches can be derived as follows: where Coes,HVS is the output capacitance of the switches in the HVS and Imin,req,H is the desired minimum current for fully charging and discharging of Coes,HVS. Since, as shown in (27), the ZVS capability can be obtained by the phase current, the amplitude of the phase current at the switching moment is significant, which means that the ZVS can easily be achieved under not the light load condition but the heavy load condition in the CF-IBDC. This is the same as the performance issue in most of the DAB converters.
To overcome this limitation, the proposed control algorithm using the fixed Zd with the PPDPS is employed under the light load condition as shown in Fig. 3-(a). Fig.  12 shows the ZVS process in the HVS under the proposed control algorithm. Just as shown in Fig. 10, the ZVS criteria for each switch in the HVS are described as red circles. Difficult points for the ZVS condition are indicated as dotted circles. Details of the resonant time interval are also shown in Fig. 12 where tres is the resonant time duration between Coes,HVS and LS. In Fig. 12-(a) and Fig. 12-(b), the DC currents of ILs,before,r and ILs,after,r are generated by the fixed Zd with the PPDPS in the LL-I mode and the LL-II mode, respectively. The current of ILs,before,r indicates that the constant value before the resonance during the dead time, and it makes charging and discharging of the output capacitance of the HVS switches.
The most important consideration of selecting Zd is the minimum current, ILs,before,r, for charging/discharging the output capacitance of the power switches. As Zd increases, the amplitude of the minimum current increases, which can reduce ZVS failure. However, it also increases the conduction loss because of RMS current increment. This is the reason why the optimal value of Zd is required. In [24], the ZVS condition for the HVS switches with the fixed Zd is explained in detail by considering the resonant process and the parameter design of ΔT. From [24], the length of Zd can be derived. The ZVS condition is that ILs,before,r should be larger than zero at the fixed Zd as follows: Even though the large Zd can easily make the output capacitance of HVS switches charge and discharge, it makes long circulation time interval as analyzed above, which causes higher conduction loss, i.e., the trade-off between the switching loss and the circulation status. Meanwhile, as shown in Fig. 13, tres should be shorter than td for obtaining full ZVS condition. Therefore, the dead time is desired to get the ZVS condition as shown in (29). Note that the dead time duration should be shorter than td,max to prevent capacitor voltage dumping where the resonant current flowing in the reverse direction again to charge the output capacitance. Table I shows the parameter specifications of the CF-IBDC, which are used in analysis and experiment. A prototype of the CF-IBDC converter is shown in Fig. 13. It is composed of two DC inductors and an H-bridge which make the interleaved boost converter in the LVS. In the LVS, SUG80050E manufactured by VISHAY is selected as the power switch since it has a low Rds,on of 5.4 mΩ with 150 V rated voltage, resulting in decreasing conduction loss.  In the HVS, a SiC MOSFET of SCT3060KL manufactured by ROHM is selected to reduce the junction capacitance which is 55 pF with 60 mΩ of Rds,on. In addition, to reduce internal leakage inductance, a toroidal DC inductor core is employed due to its singularity: the closed concentric geometry [25]. According to the considerations of the ZVS condition and the conduction loss in section 3.2, each LDC is selected to 120 μH. From (26) and Fig. 12, Zd is selected to 130 ns, and the dead time duration of td is selected around 0.3 μs. As the controller of TM320F28335 manufactured by TI is employed to control the proposed power converter.

1) STEADY-STATE OPERATING WAVEFORMS
Fig. 14 and Fig. 15 show the steady-state waveforms as the output current increases when vbat is fixed at 48 V and 60 V using the proposed hybrid control algorithm under the forward bias, respectively. Fig. 14 -(a) and Fig. 15 -(a) show the waveforms of the LL-I mode under the no-load condition. Based on the proposed hybrid algorithm, the DC bias current shown in Fig 12 is generated by Zd, which allows the soft switching of the HVS switches. The LL-II mode is shown in Fig. 14 -(b) and Fig. 15 -(b). In the LL mode, Zd is maintained and ϕPS is controlled as power changes. When ɸPS reaches half of Zpri, the ML mode in Fig. 14 -(c) and Fig.15 -(c) starts. In Fig. 14, the ML mode starts at 550 W and ends at 800 W, while the ML mode in Fig. 15 starts at 300 W and ends at 400 W. As the output power increases, D2 is going to 0.5 in the ML mode, which makes the duty of the secondary side be 0.5. After that, it moves to the HL mode, which is the same as the conventional PPS control. In the HL mode shown in Fig. 14 -(d) and Fig. 15 -(d), only ϕPS is controlled to regulate the output power.
The entire mode transition is smooth and seamless. The difference between Fig. 14 and Fig. 15 is only the time interval of the ML mode. In Fig. 14, it has a large portion of power transmission, while the ML mode shown in Fig. 15 is narrow. As D1 is longer, the interval of ML mode becomes wider, resulting in relatively easy ZVS conditions. Since D2 goes to 0.5 as the output power increases in the ML mode, the reactive power and the circulating current is reduced in the HL mode as shown in Fig. 6 and Fig. 9, respectively, resulting in the trapezoidal current waveform. Fig. 16 illustrates the experimental measurements of a step load response from 200 W to 1-kW with Vbat = 48 V under the forward bias. Zoomed waveforms are shown on the right side, which operates under the LL mode (above) and the HL mode. The phase current passing through the LVS increases from 4.7 A to 23.2 A during the step load experiment. The undershoot of the output voltage is measured as around 10 V, which is 3% of the output voltage. The transient state returns to the steady state within about 25ms. It shows that the proposed CF-IBDC converter shows good dynamic performance and enough stability in the transient operation. Since the control variable changes  Fig. 17 shows the double pulse test waveforms of power switches to verify the ZVS conditions of the proposed hybrid control algorithm. The worst case of the ZVS condition is the lowest battery voltage at the no-load condition. In Fig. 17, the gate voltage, the drain-to-source voltage, and the leakage inductor current of the bottom switches in the LVS of S4 and the upper and bottom switches in the HVS of Q1 and Q4 are captured. As shown in Fig. 17, the soft-switching capability can be obtained even under the no-load condition with the lowest Vbat. The bias current of ILs,before,r shown in Fig. 12 is selected as the smallest value to decrease the circulating current. The experimental waveforms demonstrate that the theoretical analysis in Section III.2 of the ZVS condition is well achieved for the full load range. Fig. 18 shows the power conversion efficiency curves according to load and battery voltage variations. Fig. 18-(a) shows the comparison of power conversion efficiency between the proposed control algorithm (red line) and the conventional control algorithms of the PPS (green line) and the PPDPS with ΔT (blue line) when Vbat is 48 V. Under the light load condition, the efficiency when the PPDPS with ΔT is employed is significantly higher than the case of the PPS control. This is because the ZVS can be achieved under the former control method under low RMS phase current. While, at the heavy load condition, the PPS modulation makes high efficiency compared with the PPDPS due to the decrement of the circulating current in the secondary side, which induces low conduction loss. Since the proposed algorithm is employed by the PPDPS with ΔT at the light load condition and by the PPS at the heavy load condition, the efficiency can be maximized. Therefore, the efficiency of the proposed algorithm is matched by PPDPS with ΔT under light load conditions, and by PPS under the heavy load condition, i.e., measured higher efficiency in most of the entire load range than the conventional control algorithm. Fig. 18-(b) shows efficiency curves according to battery voltage conditions of 48 V and 60 V. The maximum power conversion efficiency is measured as 96.67% at 800 W under 60 V of Vbat. The overall power conversion efficiency is relatively high except for very light load conditions since the ZVS capability can be obtained for all the active switches. Since the core loss of the DC inductor and the transformer is dominant at the light load condition, efficiency becomes low when Vbat is 48 V compared with the case of 60 V. In the cases of the heavy load condition, the conduction loss accounts for most of the total power losses. Therefore, efficiency becomes low when Vbat is 60 V compared with the case of 48 V, which is the opposite situation of the light load condition.

V. CONCLUSION
This paper proposes the effective hybrid switching modulation to overcome the limitations of the existing control algorithm and to improve the power conversion efficiency under the light and heavy load conditions of the CF-IBDC. By adopting the fixed Zd and designing DC-filter based on the theoretical analysis at light load conditions, the entire ZVS range can be guaranteed. To minimize the circulating current and the reactive power, the duty cycle of the secondary sides is changed according to load conditions. In addition, the proposed hybrid algorithm controls the decoupled duty cycle of the secondary sides and the phase shift angle between the primary and secondary sides, which can mitigate control complexity.
The effectiveness of the proposed hybrid control algorithm is verified by the prototype of 1 kW CF-IBDC from 48 to 60 V of Vbat at 380 V of Vout. The ZVS conditions of all the power switches are verified using the double pulse test. The performance of the proposed control algorithm is also verified by the steady-state operation and the dynamic response. Based on the experimental results with the proposed hybrid algorithm, the efficiency of both light and heavy load conditions is improved to 3.3 % and 1.8 %, respectively, compared with the conventional control algorithms. The highest efficiency is measured as 96.67% at 800 W under Vbat = 60 V and the effectiveness of the proposed switching pattern is demonstrated.