Common-Mode Voltage Elimination in Multilevel Power Inverter-Based Motor Drive Applications

The industry and academia are focusing their efforts on finding more efficient and reliable electrical machines and motor drives. However, many of the motors driven by pulse-width modulated converters face the recurring problem of common-mode voltage (CMV). In fact, this voltage leads to other problems such as bearing breakdown, deterioration of the stator winding insulation and electromagnetic interferences (EMI) that can affect the lifespan and correct operation of the motors. In this sense, multilevel converters have proven to be a useful tool for solving these problems and mitigating CMV over the past few decades. Among other reasons, because they provide additional degrees of freedom when comparing with two-level converters. However, although there are several proposals in the scientific literature on this topic, no complete information has been reviewed about the CMV issues and the different multilevel alternatives that can be used to solve it. In this context, the objective of this work is to determine how multilevel power converters provide additional degrees of freedom to make the reduction of the CMV possible by using specific modulation techniques, making it easier for engineers and scientists in this field to find solutions to this problem. This document consists of a descriptive study that collects the strengths and weaknesses of most important multilevel power converters, with special emphasis on how CMV affects each of them. In addition, the differences of modulation techniques aimed to the CMV reduction are explained in terms of output voltage, operating linear range, and generated CMV. Considering this last, it is recommended to use those modulation techniques that allow the generation of CMV levels of 0 V in order to be able to completely eliminate said voltage.

. Energy consumption reduction in drives without affecting provided useful energy (adapted from [7]).

FIGURE 2.
Problems caused by common-mode voltage in electric drive systems [8].
3) The reuse of stored kinetic and/or gravitational potential energy (electrical energy regeneration for direct use in other drives, injection into the AC grid and/or common DC bus, and/or energy storage in supercapacitors or batteries).
Despite the search for more efficient systems through the improvement of power converters, the increasing use of these converters in electric drive systems has renewed concerns about one of the main problems of these systems: the common-mode voltage (CMV) [9]- [11]. The high switching frequencies of the semiconductor devices produce high common-mode leakage currents. As a consequence of the existence of several stray common-mode impedance paths between the inverter and the motor frame, this leakage current flows through them every CMV variation (Fig.2) [12]- [15]. This currents lead to motor bearing failures [16]- [18], in addition to electromagnetic interferences (EMI) [19]- [21] or motor stator insulation deterioration (Fig.2) [22]- [24]. Moreover, due to the inherent advantages of the new wide-bandgap materials (especially silicon carbide and gallium nitride), converters based on semiconductors of these materials are expected to be increasingly employed [22], [25]- [28]. Although, these converters are more efficient than silicon-based converters, their high switching frequencies and high dv/dt worsen the aforementioned CMV problem [14], [29]- [31]. Even though the two-level three-phase voltage source inverter (VSI) is the most widely extended power converter [32]- [34], it is well known that it exhibits poor CMV characteristics [35]- [38]. Conversely, other converters with higher number of voltage levels, called 'multilevel' converters, exhibit additional degrees of freedom that can be used to reduce this stray CMV. In addition, they divide the bus voltage into smaller sections, thus lowering the maximum voltage that each semiconductor device must withstand [39]- [42]. Last, multilevel converters present also other benefits such as improved output waveform quality, i.e. lower total harmonic distortion of the output current (THD i ), reduced EMI and better fault tolerance [43], [44].
Multilevel converters are shown in Fig. 3 together with other converter topologies that have been proposed in the scientific literature as suitable solutions to fix CMV derived problems. In previous works [8], [45], the authors have already reviewed two-level three-phase and multiphase topologies directly aimed at CMV reduction. Due to the large number of available alternatives, this work is only focused on multilevel topologies, leaving aside multiphase topologies. Such converters are widely used in many medium-or high-power industrial applications, 1 such as industrial electric motor driven systems (EMDS) (fans, pumps, conveyors, etc. [42]), flexible AC transmission systems (FACTS) [43], high-voltage DC (HVDC) transmission systems [46], renewable energy sources (RES) [47], [48], as well as electric transportation applications, including more electric aircrafts (MEA) [49] and hybrid and fully electric vehicles (HEV/EVs) [50]). Moreover, as a consequence of their benefits, it is expected that more and more multilevel converters will be used, especially since renewable energies are becoming the main source of electrical energy and the transport sector is moving towards a 100 % electric future.
In the particular case of road transport, which currently accounts for approximately 75 % of transport greenhouse gas emissions [51], regulations and policies on emissions are increasingly strict. This last means that the road transport sector is one of the sectors that will change most rapidly, since emissions can be either reduced or eliminated by an hybrid or fully electric transportation, which implies that, ultimately, the electric vehicle fleet will grow considerably in the coming years [25], [51]. 2 In addition, an increase in the number of vehicles will be accompanied by a change in trend that is also beginning to replace the nominal voltages of the battery from 400 V to 800 V [53]- [57]. So it can be expected that the number of multilevel inverters may be increased with the increase in the number of vehicles expected for the next few years [58], without forgetting that the multilevel inverters will also continue to be used in the other applications.
Considering all the above, it is important to understand the operation of the main multilevel converters in electric drive systems and their relationship with the CMV. Therefore, this work aims to make a complete review of these converters, as well as their relationship with the CMV and how to eliminate it. In this sense, first of all, section II explains how CMV is originated in two-level converters, emphasizing how the number of phases affects this voltage and also extrapolating the results for multiphase converters. In addition, figures-ofmerit that allow comparing the different CMV waveforms are defined. Then, in section III, the main topologies of multilevel converters and the CMV values they generate are reviewed. Section IV reviews the various modulation techniques that can be used to reduce/eliminate CMV. Finally, Section V summarizes the main conclusions of this review work.

II. INFLUENCE OF THE NUMBER OF PHASES ON THE COMMON-MODE VOLTAGE IN ELECTRIC DRIVES
In [8] the analytical expression for CMV is presented by the authors. However, it is common to see in the scientific literature the equivalence between the electrical machine neutral to ground voltage and the common mode voltage [14], [59]. Although this is not strictly true, it is ideally a good approximation since the CMV waveform will be proportional and very close to neutral to ground voltage. This is reflected in Fig. 4a where the CMV instead of the neutral-ground voltage of the electrical machine is represented in purple. Fig. 4 represents a generalized VSI for any number of phases and connected to an inductive load with a star connection that presents, in its simplest form, the model of an electrical machine. Considering this figure, it can be stated that the CMV levels generated by each switching state of this converter are obtained as: where m is the number of phases/legs and v i0 is the ith inverter output phase-to-ground voltage. Also, simplifying (1) for a three-phase converter, CMV is defined as: Fig. 4b represents the CMV waveform when the converter is a three-phase inverter. In this sense, the CMV waveform voltage levels of each switching state is shown in Table 1.
At the same time, as each converter topology and modulation technique provides a different CMV waveform, CMV-related particularities are best captured by the following 'the lower the better' figures-of-merit, which will be helpful to understand and compare the CMV waveforms to be presented in this work: 1) P ∈ [0, 1] -Waveform peak-to-peak value, relative to V DC .   to P = 1, S = 1/3, N L = 4, and N T = 6, which are poor values, as indicated in [8]. Indeed, these indicators can be improved (lowered) by using alternative modulation techniques in multilevel converters. Therefore, these topics will be covered in the next sections, where the most relevant multilevel converter topologies and modulation techniques are reviewed (sections III and IV, respectively).

III. COMMON-MODE VOLTAGE IN MULTILEVEL INVERTER TOPOLOGIES
For more than fifty years, researchers have been focused on developing new multilevel power converters for medium-voltage and high-power operation [43]. Some of these architectures have been presented, first in the academia and, finally, as commercial products for applications such as EMDSs [60], [61], FACTS [62], HVDC [41], [46] or RES [63]- [66]. In this context, the most well-known multilevel converter structures are the Neutral-point-clamped (NPC) [67], the Flying capacitor (FC) [68] and the Cascaded H-bridge (CHB) [69]. Topologies that include a clamping circuit in addition to the NPC, as the Active neutral-pointclamped (ANPC) and the T-type NPC are also interesting options [70], [71]. The Modular multilevel (MM) converter has also been extensively investigated in the last decade [40], [42], [72] and, likewise and although they are not analyzed in this work, other hybrid architectures which consist on a combination of the previous ones have also been proposed [73], [74].
All these multilevel topologies can be used to reduce the CMV due to their additional degrees of freedom, since, in accordance with (2), the CMV is directly related to the converter output phase voltages. In general, incorporating additional hardware in these converters to improve the CMV is not interesting, because these architectures are already complex from the hardware point of view. Thus, a better solution is to achieve the CMV reduction through advanced modulation algorithms [75]- [77]. In this sense, the relationship between the switching states of the power converter devices and the vector representation of a SV-based modulation helps to better understand CMV. Hence, considering conventional SV-PWM modulation, the most important characteristics of the above-mentioned converters and their relationship with CMV are presented below.
A. MOST RELEVANT MULTILEVEL CONVERTERS 1) NEUTRAL-POINT-CLAMPED (NPC) CONVERTER This converter was introduced by Nabae in 1981 [67] and it is possibly the first worldwide commercialized multilevel VOLUME 10, 2022 architecture. This converter uses diodes to connect the midpoint of the upper and lower legs with the DC bus midpoint (NP) (see Fig. 5a). In its simplest configuration it provides three voltage levels at the output of each phase. Likewise, in order to increase the number of output voltage levels, the number of diodes and switches can be increased too. The possibility of multiple output voltage levels make this topology appropriate for medium and high power applications, such as RES [63] or industrial drives [60].
The NPC converter exhibits some interesting advantages. From the hardware point of view and compared to other multilevel converters, despite some clamping diodes are employed, few capacitors are needed, thus reducing the system cost while reducing the converter size and increasing the system power density. In addition, the NPC converter (as well as the FC converter) requires a just one DC source. This is an advantage over the CHB converter, which requires various independent DC sources. Moreover, when comparing any multilevel converter over the two-level traditional architecture, they exhibit a lower THD i , due to the multiple level output, and the reduction of the voltage stress on each switching device [78].
Conversely, as the number of output levels increases, so does the complexity of the converter due to the voltage unbalance between the DC-bus capacitors and the need of high number of series connected clamping diodes. Furthermore, these clamping diodes withstand a high voltage stress equal to V DC (n − 2) (n − 1) for an n-level converter, which is a disadvantage for a converter with a high number of levels. Likewise, NPC converters suffer from unequal share of commutation losses among switches due to the unequal number of commutations [39]. In addition, low-frequency voltage ripple appears in NP for high modulation rates and low power factors, resulting in low-frequency distortion on the AC output. For these reasons, it is not common to see NPC converters with more than five levels, as the disadvantages outweigh the advantages.

2) ACTIVE NPC (ANPC) CONVERTER
The ANPC was introduced by Brückner in 2001, replacing the diodes of the three-level NPC converter by active devices [79], [80]. Likewise, its five-level implementation combining both NPC and FC converter concepts was proposed by Barbosa in 2005 [81]. Regardless of the number of levels, the ANPC architecture (see Fig. 5b) is an appropriate candidate for high-power EMDS applications and has received attention in recent years [70], [82]. In industry, an example is ABB, which has upgraded its HVDC Light converter by using a three-level active-NPC structure [43]. In addition, the ABB's five-level ACS2000 is used in diverse fields of application for various industries within the general purpose drives' market as fans, pumps or compressors [83].
The main advantage of the three-level ANPC converter is that it is possible to control the loss distribution among the switching devices [70], [80]. For example, in [80] a loss-balancing scheme is proposed, which can significantly increase the converter output power. On the other hand, as an additional advantage, the five-level ANPC features redundant switching states [81], which provide additional degrees of freedom and, consequently, open-phase fault tolerance control [84], [85]. In addition, compared with the NPC, the five-level ANPC converter has simpler voltage-balancing control of the NP, more flexibility on the output voltage value and higher reliability [86]. It can be said that the five-level ANPC combines the flexibility of the FC converter with the robustness of industrial NPC converters to generate the multilevel voltages [81].
As far as disadvantages are concerned, for the three-level structure, the main drawback is that it needs to control a greater number of active devices. Further, the extension of three levels to a higher number of levels is not straightforward in this converter. To increase the number of levels, while respecting the operation of the converter architecture, a hybrid solution that combines the NPC and FC structures is necessary.

3) T-TYPE NPC CONVERTER
This converter was introduced in 2010 by Schweizer in [87]. Compared to the three-level NPC topology, the T-type incorporates an active bidirectional switch to clamp the DC bus midpoint, thus using two diodes less per bridge leg; see Fig. 5c. Moreover, when increasing to five levels there are two variants of the converter: the dual three-level T-type and the five-level T-type (Fig. 5c), both introduced by Salem in 2013 [71], [88]. In addition to their multilevel nature, the former can also be considered multiphase. In any case, the T-type NPC converter has been extensively investigated in the last decade for RES applications [64], [89], [90], as well as EMDSs [61], [88].
The T-type converter basically combines the advantages of the two-level structure such as low conduction losses, reduced part count and a simple operation, with the advantages of the three-level architecture such as low switching losses and superior output voltage quality [71]. Likewise, in a T-type inverter, fault-tolerant operation can be performed when open-switch fault occurs without adding extra devices [90].
Among its disadvantages, the NP of three-level T-type is similar to the NPC converter, because it needs to be controlled in order to keep equal the voltages of the DC bus capacitors [71]. However, unlike the NPC, its most significant drawback is that the devices must block all DC bus voltage [71].

4) FLYING CAPACITOR (FC) CONVERTER
The FC was introduced by Meynard and Foch in 1992 [68]. Here, an n-level FC converter links the midpoint of upper legs with the midpoint of their respective lower legs by means of 3(n − 2) capacitors (Fig. 6a). In addition, these capacitors are to be precharged in order to produce the correct phase-toground output voltage [62]. The hardware structure of the FC converter makes this topology suitable for photovoltaic (PV) applications [65] and wind turbines [66]. In addition, this topology has also been employed in drive systems as in the case of induction motor drives [91].
The main advantage of the FC architecture is that it is able to generate the same output voltage employing different switch on/off configurations, that is, the FC converter has redundant switching states. Due to this fact, currents may flow with different polarity through the flying capacitors in order to charge or discharge them as needed. In addition, this vector redundancy allows distributing the switching stress equally between the semiconductors [92]. And finally, unlike the NPC structure, low frequency ripple does not appear in the capacitors [93].
In return, the increment of levels reduces the accurate charging and discharging control of flying capacitors [62]. Moreover, as the number of required capacitors is high, especially in inverters with more than five levels, the inverter becomes bulky, expensive and its modularity is reduced [94]. In addition, the voltage of its capacitors must be measured, but regardless of the number of levels a per-phase single sensor is sufficient [95].

5) CASCADED H-BRIDGE (CHB) CONVERTER
This converter was introduced by Marchesoni in 1990 [69]. The structure of the CHB is based on submodules (SM), each of which contains a full-bridge, a DC-link capacitor and an independent voltage source provided by transformers or batteries (Fig. 6b). Since adding more SMs and increasing the number of levels is easy, this converter has been used in a wide variety of high-voltage applications, including EMDSs [96], FACTS such as static synchronous compensators (STAT-COM) [43], and HVDC applications [41].
CHB architectures can reach high output voltage values by connecting various inverters in series. Since each inverter can be considered as an independent SM, in case of a fault in one of them, it can be easily replaced without nearly affecting the converter performance. Consequently, one of the main advantages of this topology is its modularity and fault tolerance. Moreover, this topology features redundant switching states as the FC structure, thus allowing equal distribution of switching stress between the semiconductors and reducing the switching losses [97]. The latter is a particularly interesting feature in applications where efficiency is one of the major objectives, such as in HEV/EVs [98].

TABLE 2.
One phase switching states of the devices of multilevel converters of three and five levels and phase-to-earth output voltage generated.
As a disadvantage, a high number of independent DC sources are needed, one for each SM. Therefore, CHB architectures are mainly used in PV applications, where each half-bridge can be feed by means of an isolated PV panel. Likewise, independent batteries or fuel cells can be also employed as isolated DC sources [99], thus making the converter suitable for off-grid drive systems.   [102]. Although this topology was firstly developed for HVDC systems [46], [103], [104], it is also used in AC/AC cycloconverters [105] or medium-voltage and high-power industrial drive applications [40], [42], [106].
The main advantage of this topology is its modularity [42]. Indeed, medium and high output voltage values can be easily achieved by adding more series-connected SMs. Moreover, there is no need to use a common DC bus, since each SM incorporates its own DC bus capacitor, increasing even more the converter power density and reducing costs [72]. Likewise, other attractive features are its high efficiency and the high quality of the output voltages [42].
Conversely, MM converters suffer from current circulation within the structure, which increases conduction losses. In addition, this current increases DC-bus capacitor thermal stress since high voltage ripple is produced in such capacitor under low speed operation in EMDS applications [40], [106]. Moreover, as in other multilevel converter, the control complexity of the MM converter increases with the number of voltage levels.

B. COMMON-MODE VOLTAGE IN MULTILEVEL CONVERTERS
Any of the previously presented converters improve the quality of the synthesized waveform as the number of levels is increased (see Fig. 7). In any case, despite converters are structurally different, all the reviewed multilevel architectures can synthesize the same output voltage profile (see Fig. 7). Table 2 summarizes the output voltage values for three and five levels depending on the switching states, 3 where each converter has its particularities; e.g. the NPC can only synthesize each voltage value with a single switching state. In contrast, the other converters have redundant switching states that can synthesize the same output voltage level.
Regarding the vector space, n 3 switching states can be synthesized (total vectors of the SV diagram; see Table III-A5), and they can be simplified as n 3 − (n − 1) 3 states of the converter with different line-to-line voltage (different verctors of the SV diagram). Due to this vector redundancy, the number of vectors can be reduced to 27 − 8 = 19 for the three-level converters and 125 − 64 = 61 for the five-level converters (see Fig. 8). 4 Fig. 8a shows the general space-vector diagram of all three-level converters, which depicts the 27 switching states and 19 voltage vectors. Each switching state can be expressed by an ordinal number array, for example, [−1 0 1] corresponds to the connection of phase A to the negative bus, phase B with zero voltage level (e.g, phase B to NP in the NPC converter), and phase C to the positive bus (see Fig. 5 and 6). Likewise, the voltage vectors can be classified according to their amplitude as zero (Z i ), small (upper S iU and lower S iL ), medium (M i ), and large (L i ), where i = 1, 2 . . . 6. Table 2 summarizes this classification.
In accordance with (2) (Table III-A5). The MM converter is an exception, depending on the type of SM chosen [102] the number of switches is different, therefore the switching states and the output voltage cannot be identified directly. Consequently, the CMV will depend both on the resulting converter topology (as a function of the SM chosen) and the modulation used on the converter. However, whatever the SM, the CMV can be generally defined for the MM converter as:  where i represents each phase of the converter, and v Li and v Ui the lower-arm and upper-arm voltage of each phase (see Fig. 6c) [117]- [119]. In any case, when traditional pulse-width modulation (PWM) techniques are employed in all these multilevel converters, such as traditional multilevel SV-PWM [120], [121], the CMV values shown in the Table III-A5 are obtained for three-and five-level converters [64], [108], [110]. The number of CMV values increases with the converter output levels (e.g. from 7 to 13 when increased from three to five levels). Consequently, S is smaller as the number of levels increases. Indeed, S is reduced from 1/6 to 1/12 when the VOLUME 10, 2022 number of converter levels increases from three to five, which can be generalized as S = 1/(3n − 3). Table 4 shows this last case for the most important multilevel topologies, as well as the main differences of each topology emphasizing their advantages and disadvantages.
Finally, and as it has been previously stated, it is worth noting that the reviewed multilevel architectures do not reduce the CMV by themselves. Thats is, a modification of the PWM algorithm is needed for that purpose. But, those advanced PWM algorithms are specific for multilevel topologies. On this basis, section IV-B reviews some of the most relevant PWM techniques to reduce the CMV in multilevel converters.

IV. ADVANCED MODULATION TECHNIQUES FOR COMMON-MODE VOLTAGE REDUCTION
The modulation schemes for multilevel converters have some differences from those of two levels. However, although each multilevel converter has its differences, the same modulation algorithm can generally be used for all converters as long as they have the same number of levels. 5 In this sense, the most important modulation techniques of multilevel converters, both conventional and for the reduction of CMV, are reviewed below.

A. CONVENTIONAL PWM TECHNIQUES FOR MULTILEVEL CONVERTERS
Multicarrier PWM are the most extended modulation techniques for controlling multilevel converters [122]. Like carrier based algorithms, this technique is based on comparing a high-frequency carrier, normally a triangular signal, with the modulation or reference signal. However, n − 1 carriers are compared with the reference signal in the multicarrier PWM techniques, where n is the number of the output levels of the converter. The most common multicarrier PWM techniques can be classified as level-shifted (LS) and phase-shifted (PS) PWM respectively. 5 Note that not all modulation techniques are used equally in all multilevel converters, some are proposed to solve particularities of each converter. For example, various modulation algorithms have been proposed to solve the problem of balancing DC bus capacitors in NPC converters [107], [108], [121]. The LS-PWM techniques consist in distributing N carriers vertically along the modulation amplitude range, where the amplitude of the each carrier corresponds to V DC /(n − 1) [123]. Depending on the phase disposition of the carriers, the LS-PWM can be divided into three different techniques [124]. The Phase-disposition PWM (PD-PWM) consists in using all the carriers with the same phase displacement. The alternative phase opposite disposition PWM (APOD-PWM) is based in shifting each carrier 180 • from its adjacent carrier. In some converters, this technique can be used for reducing the third order harmonic component from the output voltage [125]. Finally, the Phase opposite disposition (POD-PWM) uses carriers in the negative range of the modulation signal that are 180 • shifted from the carriers in the positive range of the modulation signal. Fig. 9a shows an example of PD-PWM which is well situated for NPC and T-Type multilevel converter. However, they are not suitable for other types of converters (CHB, FC, and MMC) [43].
Phase-shifted PWM (PS-PWM) is another highly extended multicarrier modulation technique (Fig. 9b), because it eliminates all low order harmonic components of the output voltage [126] and is easy to implement. In this technique, the peak-to-peak amplitudes of the carriers corresponds to V DC , but they are displaced in phase along the carrier period. That is, the phase displacement between carriers is φ = 2π /N . This technique is suitable for converters such as CHB, FC and MMC. However, it is not suitable for NPC or T-type converter topologies [43].
Regarding SV-PWM, the SV diagram of the three-level multilevel inverters has been introduced according to the switching states of each converter in section III-B. Thus, Fig. 8a shows how this diagram is divided into six sectors as in two-level inverters. In this case, each sector is divided into four triangles labeled from I to IV; see Fig. 9c. This leads to several alternative algorithms to form the reference vector. The most typical is the Nearest three-vector PWM (NTV-PWM), which uses the nearest three states (nodes of the triangle containing the vector) to synthesize the desired voltage vector (see Fig. 9c). As the zero and small vectors can be generated by more than one switching state, different vector sequences can be applied to synthesize V ref [120], [121], [127]. On the other hand, a more complex SV-based modulation technique and particular to NPC converters, named Virtual SV-PWM (VSV-PWM), allows to control voltage in NP over the full linear range on these converters [120], [128]. For it, a set of new virtual vectors is defined as a linear combination of the previous vectors (Fig. 9d). Other alternative for various multilevel converters is to use a conventional twolevel three-phase SV-PWM, which is achieved by correcting the reference voltage vector, and dividing the vectorial space into smaller hexagons [129]; see Fig. 9e. Finally, although SVM is usually calculated in the αβ plane it can also be represented in three-dimensional space (3D-SVM) [130], where apart from the α and β axes, the gamma axis is added in order to compensate harmonics and control the zero sequence in three-phase four-leg converters.
All in all, when comparing the multilevel converter SV with a two-level converter, there are certain similarities. On the one hand, the six large vectors are equivalent to the two-level converter active vectors [121]. Therefore, the same maximum reference vector is synthesized (0.5773V DC ) and M a ∈ [0, 1.1547]. On the other hand, only using six large vectors is not the best solution, the nearest vectors to V ref (zero, small, medium or large) are the most appropriate alternatives in terms of their ability to minimize the switching frequencies of the power devices, improve the quality of the output voltage spectra, and the EMI [121]. In this sense, Fig. 10a shows the nearest vectors that are used to synthesize V ref in sector 1, Fig. 10b shows the linear range (LR), and Figs. 10c to 10f show the switching state of each phase and the CMV produced by the converter in I to IV triangles.
Note that unlike the modulations for traditional two-level three-phase converter, different sequences of vectors can be applied within the same sector for each T SW (one for each triangle). Therefore, the CMV waveform can also change in each case. Even so, in this case the CMV figures-of-merit are improved to P = 1/2, S = 1/6, N L = 4 and N T = 6 when comparing with the three-phase two-level inverter.
Despite the CMV is better than in their two-level counterparts, further improvement can be achieved with other modulation techniques. Therefore, the most featured algorithms for CMV reduction are reviewed below.

B. PWM TECHNIQUES FOR THE CMV REDUCTION 1) DISCONTINUOUS PWM TECHNIQUES
Discontinuous modulation techniques (D-PWM) for multilevel converters are discussed in detail in [131], [132]. As in multiphase converters, discontinuous modulation techniques for multilevel converters aim to reduce the number of commutations per switching period (T SW ). Thus, switching losses are reduced and consequently fewer CMV levels and transitions are produced. Fig. 11b shows the classification of the vectors in the first sector so that one of the phases remains clamped to certain voltage level. Likewise, Figs. 11c and 11d show two possible vector sequences in the second triangle. In these examples, the CMV figures-of-merit are P = 1/3, S = 1/6, N L = 3 and N T = 4. Furthermore, the LR of both modulation algorithms is the same as SV-PWM since the same vectors are used to synthesize V ref .
It should be pointed out that, despite several D-PWM techniques have been proposed [131], [132], their main objective is not reducing the CMV. So, in the following section RCMV-PWM techniques that have been prepared for this purpose are introduced.  eliminated [133], [134]. Fig. 12a shows the synthesis of V ref for this modulation technique named Zero-CMV PWM (ZCMV-PWM). In this case, the LR is reduced compared to the conventional NTV-PWM and discontinuous modulations (Fig. 12b), where M a ∈ [0, 1] and V ref ,max = 0.5V DC [135]. However, the best CMV result is obtained from this modulation where P = S = N L = N T = 0 (see Fig. 12c).
Given the benefits of ZCMV-PWM in terms of the CMV, some variations of this technique have been investigated. For example, [75]- [77] have presented this modulation technique for five-level converters, where only 19 vectors producing VOLUME 10, 2022  [136] modulation for seven-level converters is featured. On the other hand, [133] also investigates how to implement this technique in the carrier-based approach. Furthermore, in [76], [137] a generalized method based on carrier-based is proposed that serves for both CHB and NPC converters regardless the number of levels.
Considering the above, and given the existence of vectors that generate zero CMV, it is less common to find the classical modulation techniques named RCMV-PWM for multilevel converters. Nonetheless, there are still some works that review these techniques, which are explained below.

b: ACTIVE ZERO-STATE PWM (AZS-PWM)
Following the idea of Fig. 9e, a simplification of the three-level vectorial space to the conventional two-level scheme has been proposed in [108]. This simplification allows the use of the two-level AZS-PWM algorithm to reduce the CMV in multilevel converters. This modulation scheme combines two opposite active vectors to synthesize the zero vector. Fig. 13a shows the synthesis of the reference vector. The LR remains the same as NTV-PWM and discontinuous modulation techniques (all multilevel linear range). Finally, Fig. 13b shows the CMV waveform where its figures-of-merit values are P = S = 1/6, N L = 2 and N T = 6.

c: REMOTE-STATE PWM (RS-PWM)
In [135] two-level RS-PWM scheme is adapted to multilevel converters. This modulation only uses odd/even medium vectors to minimize the produced CMV. Fig 14a shows how V ref is synthesized in multilevel converters when this algorithm is used. The main drawback of this modulation, as in twolevel RS-PWM, is that the LR is dramatically reduced (see Fig 14b). Moreover, as all the medium vectors produce the same CMV, it cannot be improved more than ZCMV-PWM, therefore the CMV waveform is the same (see Fig. 14c), with: As in the previous one, the SV implementation resulting from using only medium vectors of NS-PWM is represented in [135]. In this modulation only the adjacent median vectors (see Fig 15a) are used to synthesize V ref and therefore the LR is reduced as in two-level NS-PWM (see Fig 15b). Likewise, as all the medium vectors generate the same CMV, it cannot be improved more than ZCMV-PWM, therefore the CMV waveform again is identical of ZCMV-PWM (see Fig. 15c), with: P = S = N L = N T = 0.

3) OTHER MODULATION TECHNIQUES FOR CMV REDUCTION
In addition to the above techniques, other works have studied more modulation techniques for the CMV reduction which usually avoid the switching states that generate the highest CMV levels (zero vectors) [107], [109]. However, more ambitious techniques for three-level converters [10], [77], [138] manage to limit the CMV waveform ±V DC /6 range, trying to find a balance between CMV and power losses or DC bus balancing.
As a summary, Table 5 shows the modulation techniques for multilevel converters reviewed in this section, which are compared to the conventional SV-PWM technique of a twolevel three-phase VSI. As it can be seen, the multilevel converters together with the appropriate modulation technique, allow to reduce the CMV considerably compared to twolevel VSI. In fact, there are techniques that reduce all defined figures-of-merit completely. However, techniques such as RS-PWM or NS-PWM reduce the linear range considerably, thus being the ZCMV-PWM more beneficial than the previous ones, both in CMV reduction and in signal quality.

V. CONCLUSION
Environmental pollution and climate change, among other problems, are driving a complete evolution of the current energy transformation methods towards a more sustainable and efficient 100% renewable energy conversion systems. In order to achieve this goal, power electronics not only play a crucial role as a tool for power conducting in renewable energy sources, but also for controlling motor speed and torque generation in electric machines by varying its input frequency and voltage. Indeed, power inverters are increasingly used to control the rotational speed of these machines and to condition the power provided by a energy source in practically all sectors, but especially in industry and electric transportation.
In such context, the key role of multilevel inverters in electric drives and its relation to common mode voltage has been discussed in this paper. From this review, it can be concluded that despite each multilevel topology has its pros and cons, they allow to synthesize waveforms with higher quality than two-level converters, as well as increase their voltage values and consequently their power ranges. In addition, all multilevel converters (considering the same number of levels) have the possibility of generating the same voltage at each phase output. Therefore, regarding the output voltage, the only difference between multilevel converters is that they can have a different number of redundant states and the switching states are converter topology dependent.
From the CMV point of view, it should be noted that multilevel converters are generally the most promising converters for reducing CMV, since they have redundant switching states (i.e. they synthesize the same output voltages). In this way, those states that generate the same CMV can be selected in order to eliminate CMV transitions. Furthermore, unlike other converters, these power inverters have the advantage that one of the CMV levels that they produced is 0 V, being possible to completely eliminate CMV.
Finally, regarding the modulation techniques oriented to the CMV reduction, the ZCMV-PWM technique for multi-level converters is apparently the most advantageous, both in terms of CMV and in its balance between power losses, signal quality and linear range. This technique achieves 100 % elimination of CMV. However, when modulation techniques are used to reduce CMV, other parameters are usually affected, regardless of whether the technique has been implemented following the carrier-based or space-vector approach. At this point, each technique can bring its own benefits, for example D-PWM techniques use the full linear range of SV and reduce switching losses. Although, these techniques does not improve CMV as much as others (only up to 66.7 % of P ). Likewise, the AZS-PWM technique also uses the entire linear range and further improves the CMV (up to 83.3 % of P ), but has the disadvantage of increasing the harmonic distortion of the converter output current. Therefore, the most suitable modulation technique will depend on the requirements of each application. And it will be up to each user to select the most suitable converter with its corresponding modulation technique that allows a reduced CMV.