Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based ternary half adder (THA) and multiplier (TMUL) circuits use novel ternary unary operator circuits and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. Extensive simulations (over 160) of the proposed designs in terms of PVT (Process, Voltage, Temperature) variations, noise effect, and scalability studies, along with several benchmark designs using HSPICE simulator, prove the significance of the proposed circuits to decrease the power-delay product (PDP), improve the robustness to process variations, and the noise tolerance. The obtained results show the superiority of the designs in a reduction between 32% and 74% in transistors count and between 18% and 99% in PDP compared to the most recent works.


I. INTRODUCTION
Two major problems are facing the embedded systems and nano-scale circuits currently, which are (1) the CMOS (Complementary Metal Oxide Semiconductor) transistor, and (2) the binary circuits. Solutions can be done by using CNT-FET (Carbon Nano-Tube Field Effect Transistor) instead of CMOS transistor and using MVL (Multiple-Valued Logic) circuits instead of binary circuits.
(1) The CMOS faces significant complications in nanotechnology circuits such as tight channel-effects and high current leakage [1]. Therefore, many scientists proposed various alternative solutions in the transistor technologies like FinFET (Fin Field-Effect Transistor), Spin-wave, Single-electron devices, CNTFET. Among all different transistor technologies, CNTFET has a higher performance [2].
(2) The binary circuits require high energy consumption. Whereas, MVL circuits reduce the consumption of energy because the MVL digit can hold over two states of data.
The associate editor coordinating the review of this manuscript and approving it for publication was Chaitanya U. Kshirsagar.
However, the challenge in the ternary circuit is: How to obtain the logical state 1 (Vdd/2) from one power supply (Vdd)?
Many researchers inserted two resistors (which increase the size of the circuit and are not recommended in VLSI circuits) and others inserted two diode-connected transistors acting like resistors to solve the problem size in VLSI.
These two resistors or two diode-connected transistors are necessary to create a voltage divider to generate logic 1 (Vdd/2). But the results showed a huge rise in the power dissipation because of the direct current path from the power supply (Vdd) to the ground [14]. Therefore, one of the advantages of this paper is the use of (Vdd/2) in the designs to eliminate these two diode-connected transistors.
This paper utilizes the ternary unary operators (see Section II), CNTFET transistor, transmission gates and applies dual-voltages (Vdd, Vdd/2) in the designs to decrease the PDP of the proposed THA and TMUL. This technique is used to save battery consumption of the nano-scale embedded systems and Internet of Thing (IoT) devices.

A. LITERATURE REVIEW
There are a large number of publications that presented different THAs and TMULs based on CNTFET. This paper describes the importance and the latest ones, as summarized in Table 1.
Different methodologies have been proposed to design ternary logic circuits, which are described as follows: VOLUME 9, 2021 (1) Use of the ternary conventional design by utilizing the Ternary Decoders (TDecoder) to make the conversion from the ternary inputs to intermediate binary bits, then using binary logic gates, and finally using the ternary encoders to get the final ternary outputs such as: Authors of [15]- [18] designed THAs with (136, 112, 112 CNTFETs, and 108 GNRFET (Graphene Nano Ribbon FET, which is derived from CNTFET)) and TMULs with (100, 86, and 76 CNTFETs), respectively, using the conventional design. Whereas in [19], the authors proposed a THA with 85 CNTFETs and TMUL with 61 CNFTFETs without using ternary encoders by using dual-voltages (Vdd and Vdd/2).
(4) Use an algorithm for a logic synthesis but this method will generate a large number of transistors in series, which produced high propagation delays and PDP, such as: Authors of [27] designed a THA with 48 CNTFETs using a modified Quine-McCluskey and post-optimization algorithms.
(5) Use transmission gates (TGs) in series, special transistors arrangements, or Resistive Random Access Memory (RRAM) such as: Authors of [28], [29] proposed THAs with (39 and 50 CNTFETs) and TMULs with (34 and 38 CNTFETs) using cascading TGs, which produced higher propagation delays and PDP. In [30], the authors proposed THA with 90 CNTFETs and TMUL with 62 CNTEFTs using RRAM. The authors of [31] proposed two THAs with 94 and 66 CNTFETs and the authors of [32] proposed THA with 64 CNTFETs using TDecoders and special transistors arrangements. Whereas in [33], the authors proposed a THA with 60 CNTFETs using ternary encoders and special transistors arrangments.
Finally, the authors of [34] proposed the lowest energy consumption THA with 34 CNTFETs compared to the designs mentioned above using only unary operators and transmission gates, which is adopted in this paper.

B. CONTRIBUTIONS
The previous designs suffer from a large number of transistors used, high PDP, low robustness to process variations, and/or low noise tolerance.
This paper proposes efficient circuit implementation of THA and TMUL with 35 and 26 CNTFETs using unary operators, transmission gates, and dual-voltages (Vdd, Vdd/2) to get the lowest PDP for saving battery consumption of the embedded systems and IoT devices.
The main contributions of this paper are as follow: 1) The proposed designs do not utilize basic logic gates, TDecoders, and encoders that lead to high transistors count and PDP (compared to [15]- [21]). 2) Use dual-voltages (Vdd and Vdd/2) to disconnect the direct current path from Vdd to the ground that leads to high energy consumption (like [15]- [17], [22], [27]). 3) Use ternary unary operators that can replace the basic logic gates, which significantly reduce the number of used transistors and energy consumption. So, we reduce the transistors count, decrease the energy consumption, improve the robustness to process variations, and noise tolerance.

II. THE PROPOSED UNARY OPERATORS
This paper uses the Stanford CNTFET model, as shown in Fig.1, which can be found in [35]. However, it is worth to mention that the threshold voltage depends on the carbon nano-tube (CNT) diameter by the following equation (1): where Dcnt is the CNT diameter.  Table 2 describes the operation of the CNTFET transistor, and the relation between the threshold voltage and the CNT diameter. Unary operators of m-valued system are one-input and one-output logic gates [36].
In To design new THA and TMUL (next section), eight unary functions are needed which are shown in Table 3: Where A is the ternary input, the first unary function A p is a Positive Ternary Inverter (PTI), the second A n is a Negative Ternary Inverter (NTI), the third and the fourth functions are the cycle operators, A 1 is A + 1 and A 2 is A + 2, whereas the fifth functionĀ 2 is the complement of A 2 . The sixth function A 1 is the decisive literal, and the last two unary functions are 1 ·Ā n and 1 ·Ā p .
We propose novel designs for two unary operators: B 1 is shown in Fig. 2(g) and in Fig. 3(d), andĀ 2 is shown in Fig. 3(c). The other six unary operators are presented in [34].
The transistors count comparison of the proposed unary operators to those in [14], [23]- [25] are shown in Table 4.

III. THE PROPOSED TERNARY COMBINATIONAL CIRCUITS
We propose a THA and a TMUL with 35 and 26 CNTFETs using unary operators and transmission gates.
where A i and B i , i ∈ {0,1,2}. Figure 2 shows the proposed THA with 35 CNTFETs using eight unary operators, transmission gates (TGs), and dual-voltages (Vdd, Vdd/2). Without using cascading TGs, which is the advantage compared to THA with 34 CNTFETs in [34] that used cascading TGs. Because cascading TGs provide higher propagation delays and energy consumption.
When the voltage supply (Vdd) decreases in a transistor then the propagation delay will increase. Therefore, any path from inputs to outputs contains transistors that have voltage supply equal to Vdd/2, that path will have higher propagation than other paths that have voltage supply equal Vdd.
The dotted red line is the critical path which is the maximum propagation delay 7.74 ps (we got that value from the simulation results) from the input A to the output Carry via (A, An, 1 ·Ā n , TG (B, Bp), then Carry), when A changes from 0 to 1, B = 2, and Carry from 0 to 1.

B. THE PROPOSED TERNARY MULTIPLIER
The 1-trit ternary multiplier (TMUL) can multiply two ternary inputs (A and B) and produces two outputs: the Product and the Carry, as described in truth Table 6.  The equations of the Product and Carry can be obtained from Table 6 to lead three designs: 1) Conventional design in [15]- [17], [19], which uses Eq. (5). 2) Cascading TMUXs design in [20], [21], which uses Eq. (6). [14], [22]- [25] and adopted in this paper, which uses Eq. (7).  The dotted red line is the critical path which is the maximum propagation delay 9.33 ps from the input A to the output Product via (A, Ap,Ā 2 , TG (B, Bp), then Product), when A changes from 1 to 2, B = 2, and Product from 2 to 1.

IV. SIMULATION RESULTS AND COMPARISONS
The proposed ternary unary operators, THA, and TMUL are validated, simulated, and compared to 32 nm channel CNTFET-Based ternary circuits in [15]- [23], [25], [27], [29], [31]- [34] using the HSPICE simulator. Figures 4 and 5 show the transient analysis of the proposed THA, and TMUL with power supply at 0.9 V, the temperature at 27 • C, and the frequency at 1 GHz. All input signals have a fall and rise time of 20 ps.

A. RESULTS DISCUSSION
The power consumption in a transistor is composed of two types: Dynamic and Static.
Dynamic power is the power consumed while charging and discharging the capacitive nodes in the process of switching.
Static power essentially consists of the power used when the transistor is not in the process of switching. If diode-connected transistors exist, then the transistors will act as Resistors. Thus, Joule effect power is created and generated heat in the circuit.
Total Power consumption : Static Power : Dynamic Power : To decrease the power consumption, we must remove the diode-connected transistors and reduce the number of transistors.
The results of the proposed designs are very good as expected, as shown in Tables 8 and 9, due to our major contributions (See Subsection I.C.). We will explain the results in detail, as follow.
1) The proposed designs do not use diode-connected transistors that act like resistors to generate logic 1 (Vdd/2). This technique will generate the direct current path from the power supply (Vdd) to the ground, which will increase the static power in a drastic way, as described in equation (8a). Therefore, one of the advantages of this paper is the use of Vdd/2 in the designs to eliminate these two diode-connected transistors and to decrease the static power to a very small value due to very small leakage current in CNFET transistor. The Standard Ternary Inverter (STI) is the typical example to generate logic 1 from one power source Vdd. We analyze the static power of STI [15] in Fig. 6: (a) The transistor-level of STI, (b) the truth table of STI, (c) shows that when logic 1 (0.45V) is generated by two diode-connected transistors, the static power is 2000 times higher than other outputs, and (d) shows that 98% from the average power consumption is for static power.
2) The proposed designs do not utilize basic logic gates, TDecoders, and encoders that lead to high transistors count and PDP.
3) The proposed designs use unary operators of the ternary system that can replace the basic logic gates, which significantly reduce the number of used transistors and energy consumption. So as explained above, the proposed designs reduce the power consumption more than 90% compared to [15]- [21] that use diode-connected transistors and between 6% and 60% reduction compared to [29], [31], [33], [34] that do not use diode-connected transistors.

B. PVT VARIATIONS
To validate and test the proposed designs by how are working in all different conditions? Therefore, this paper analyses and simulates the proposed and all the investigated THAs and TMULs for PVT (Process, Voltage, Temperature) variations.
Process variation is generally occurring change in the attributes of transistors (i.e., oxide thickness, length, . . . ) during the fabrication of the integrated circuits (ICs). The variation becomes a larger percentage at smaller process nodes and has a strong influence on the behavior of the circuits.
Therefore, all THAs and TMULs circuits are validated in the presence of major process variations: TOX, CNT's Count, Channel length, and CNT diameter using Monte Carlo analysis [38].

C. NOISE EFFECT
In addition to PVT validation, the proposed circuits are tested with the injection into the inputs by a noise signal, as shown 56732 VOLUME 9, 2021  in Fig. 9. The noise signal has a pulse width (W n ) and a pulse amplitude (V n ).
To determine the influence of noisy inputs on all circuits, the Noise Immunity Curve (NIC) is used.
To draw NIC, choose a W n and try several values for V i to get the maximum value of V i , which is V n that the output remains correct.
Above that point (W n , V n ), the circuit will provide an output error. Then we choose another value of W n and try again to get new V n , and so on till we get an almost horizontal line. We do it for all investigate circuits. Thus, any circuit with higher NIC shows a more noise-tolerant circuit [39]. Figure 10 shows that the proposed THA and TMUL have higher noise immunity among other designs because their NIC curves are above all curves.

D. SCALABILITY STUDY
To verify the scalability of the proposed THA and TMUL in big circuits. Two and three cascading THAs, and two cascading TMULs are simulated with power supply at 0.9 V, the temperature at 27 • C, the frequency at 1 GHz, and fall and rise time of 20 ps, as shown in Tables 10 and 11. When the number of cascading THAs and TMULs are increasing, the power consumption, delay, and PDP are increasing less than or around double. Therefore, the proposed THAs and TMULs have scalability in big circuits.

V. CONCLUSION
This paper proposed novel designs of 32 nm CNTFET-Based Ternary Half Adder and Ternary Multiplier using proposed Unary Operators combined with transmission gates without using ternary decoders, basic logic gates, or ternary encoders.
The design process utilizes different techniques in terms of transistor arrangement, two power supplies (Vdd, Vdd/2), transistor count reduction to reach the final target.
The HSPICE simulation results of the proposed circuits to existing circuits demonstrate higher performance and lower energy consumption for different simulation environments, such as PVT (process, voltage, and temperature) variations, and the noise effect study. The results confirmed that the proposed circuits had higher robustness to process variations and higher noise tolerance than other models.
Finally, the proposed THA and TMUL can be implemented in low-power nano-scale embedded systems and IoT devices to save battery consumption.