Interleaved Modulation Scheme With Optimized Phase Shifting for Double-Switch Buck-Boost Converter

Owing to low voltage stresses, wide range of input voltage and the same polarity of output voltage and input voltage, double-switch buck-boost converter (DSBBC) is a popular choice to achieve dc/dc conversion in photovoltaic generations (PV), power factor correction (PFC), portable devices and so on. Combined control (CC) makes DSBBC operate efficiently, but large ripples of output voltage are unavoidable during mode transition. With two equal duties, interleaved modulation (IM) makes the inductor ripple current decrease remarkably compared with synchronous modulation (SM) while inductor average current is still high. By introducing duty offset, inductor average current declines and efficiency is enhanced obviously under interleaved modulation with duty cycle offset (IMDO). However, with 180-degree phase-shifted angle, the ripple current is not low enough in some cases. Thus, to make further improvement on ripple current, an interleaved modulation scheme with optimized phase shifting (IMOPS) is proposed for DSBBC in this paper. Current features, optimal phase-shifted angle (OPSA) and operating region under IMOPS are described meticulously. Besides, theoretical and quantitative comparisons of different modulation schemes are presented, including inductor average current, inductor ripple current and ratio of direct power transfer (DPT). Based on a 150W prototype, the feasibility and effectiveness of IMOPS are demonstrated by experimental results.


I. INTRODUCTION
Double-switch buck-boost converter (DSBBC) is regarded as a cascaded dc/dc device, where a buck converter lies ahead and a boost converter lies behind. By removing the intermediate capacitor and combining two inductors into one, a DSBBC is achieved, whose topology is drawn in Fig. 1. The converter contains two switches S 1 , S 2 , two diodes D 1 , D 2 , inductor L and filter capacitor C. In addition, R is the load resistor. By adjusting duty cycles, d 1 and d 2 , input voltage U i can be stepped up or down to output voltage U o , which is decided by The associate editor coordinating the review of this manuscript and approving it for publication was Zhe Zhang .
In contrast with conventional single-switch buck-boost converter, DSBBC has advantages on lower voltage stresses on switches, wider range of input voltage, and the same polarity of output voltage and input voltage [1]. As for other buck-boost converters in non-isolated form, such as Cuk and SEPIC, DSBBC has a simpler circuit structure because of less components, which is beneficial to high power density and high efficiency [1], [2]. On account of these characteristics, DSBBC gains increasing attention in photovoltaic generations (PV) [3]- [5], electric vehicles or plug-in hybrid electric vehicles [6], [7], light-emitting-diode (LED) drivers [8], power factor correction (PFC) [9], [10], power supplies for communication systems [11] and portable devices [12], [13].
In [18], authors utilize two scaled and phase-shifted carrier waves so that converter could transit between buck, boost and buck-boost modes. The information, including operating mode and direction of power flow, is unnecessary in this modulator. Moreover, this modulation scheme could be achieved by adjusting control signals as well. Concretely, the original control signal generated by inner loop controller is split into two scaled and phase-shifted ones, which facilitates digital implementation.
In terms of amplitude adjustment of carrier wave, two symmetric and sawtooth-like ramp signals are used as buck and boost carrier waves in [19]. With this method, only two switches change their states instead of all in a switching period. Therefore, conduction and switching losses both decrease. Besides, owing to the avoidance of buck-boost mode, inductor average current descends and furthermore conduction loss declines. Based on [19], three possibilities of slope mismatching as well as working states of converter are analyzed in [20]. In addition, a symmetric dual-ramp generation circuit is designed to ease this problem. However, realization of these two approaches is difficult for digital converters.
As for phase-shifted angle optimization, there exist four strategies generally, including combined control (CC), synchronous modulation (SM), interleaved modulation (IM) and IM with duty cycle offset (IMDO). Under CC, on the one hand, DSBBC fulfills the function of buck converter when S 2 is kept off and S 1 works in PWM style. On the other hand, DSBBC degrades into a boost converter when S 1 is kept on and S 2 is driven by PWM signal. However, smooth transition between buck and boost modes needs additional transition methods or compensation techniques, which is the main drawback of CC.
The load power P L is divided into two parts, which are P direct and P indirect . P direct is directly from input source while P indirect is from energy-storage components. If S 1 is turned on and S 2 is turned off, then the load is supplied by input source. This case is direct power transfer (DPT), which benefits high efficiency [21]. As Fig. 2 shows, when DSBBC operates under SM, the two switches are turned on and off meanwhile. Here, u S1 , u S2 are driving signals of S 1 , S 2 while u L , i L are instant voltage and current of inductor respectively. And T S denotes the switching period.  Nevertheless, large volume caused by large energy-storage components goes against power density improvement and efficiency is not high as a result of DPT absence. A two-edge modulation (TEM) scheme is presented in [2], where S 1 is triggered by trailing edge and S 2 is triggered by leading edge. In this case, S 1 is turned on at the beginning of a switching period while S 2 is turned off in the end of a switching period. Thus, the overlapping interval when switches are both onstate or off-state is narrowed and ripple current decreases somewhat. But the phase-shifted angle ϕ isn't the optimal choice and varies according to duty cycle. In [21], IM is introduced as Fig. 3 illustrates, where d 1 = d 2 and phase-shifted angle between two duties is 180 • . Due to this technique, inductance is reduced sharply and efficiency is promoted because DPT exists. On account of lower ripple current, IM is also put into use in modified topology [7].
Whereas, high inductor average current is still an existing issue to limit efficiency promotion. An asynchronous control scheme applied in non-inverting buck-boost converter with coupled inductor is proposed in [22]. Under this scheme, two semiconductors work with the synchronous moment of turning on, but asynchronous moment of turning off if d 1 is not identical to d 2 . This scheme reduces ripple current in comparison with synchronous modulation on the same condition. Practically, inductor average current also descends and phase-shifted angle is zero in this situation. Furthermore, the concept of duty offset is introduced in [23] and IMDO is put forward thereupon as Fig. 4 depicts. The influence of duty offset on inductor average current is analyzed. What's more, small-signal model is also derived for realization of dual-loop control. Yet, the ripple current under IMDO is still not low enough in some cases, as phase-shifted angle is fixed at 180 degrees, which may be not always optimal in the whole range of input voltage. In other words, the strategy to reduce ripple current could be further researched. In this paper, interleaved modulation with optimized phase shifting (IMOPS) is proposed for DSBBC based on IMDO. Actually, average current and ripple current of inductor are both low under the proposed modulation scheme, which guarantee high conversion efficiency for various input voltages.
The reminder parts of this paper are organized as follows. In Section II, the impacts of phase-shifted angle on ripple current when duty offset exists are analyzed firstly. Subsequently, the phase-shifted angle and operating region under IMOPS are also described in this section. Comparisons of inductor average current, inductor ripple current and ratio of direct power transfer under different modulation schemes are elaborated in Section III. Experimental verifications and analysis are displayed in Section IV. At last, conclusions are presented in Section V.

A. DUTY OFFSET
When positive duty offset c exists, d 1 is enlarged and d 2 is narrowed by where d is the control signal. According to [23], evaluation range of c is where D max and D min represent upper and lower bounds of effective duty cycles; U i_max and U i_min are upper and lower limits of input voltage. Influenced by unavoidable non-idealities, switching noise and circuit layout in practical operations, D min is not zero and D max is not one. Virtually, D min is the minimum duty cycle to turn on the switch and make it work in PWM style while D max is the minimum duty cycle to keep the switch conducting all the time. When d 1 or d 2 is less than D min , it will jump to zero and the corresponding switch keeps offstate. When d 1 or d 2 is more than D max , it will jump to one and the corresponding switch is always on-state. With the help of oscilloscope, values of D max and D min can be acquired by testing the converter beforehand according to the aforementioned descriptions.
Therefore, duty cycles should follow that As a result, d has the limitations that When DSBBC operates at buck mode, the condition is As for boost mode, the condition is Compared to SM and IM, inductor average current is reduced remarkably with the same load, which is evaluated as Substituting (1) and (2) into (8), it is obtained that From Fig. 5, I L becomes lower if larger c is selected, which contributes much to efficiency promotion in practice. 55424 VOLUME 9, 2021

B. SWITCHING STATES
To facilitate the analyzing process, the conditions listed below are considered to be satisfied: 1) all power semiconductors are ideal; 2) filter capacitor C is large enough to ensure output voltage constant in a switching period; 3) DSBBC works at continuous current mode (CCM). As for DSBBC, there exist four potential switching states in total and relevant current flow paths are outlined in Fig. 6. In a switching period, actual number of switching states depends on the adopted modulation scheme and the values of duty cycles. Each state is described as follows: With both switches on-state, D 1 and D 2 are turned off due to inverse voltage, which is drawn in Fig. 6 (b). On the one hand, inductor is charged by input voltage and inductor current increases. On the other hand, load consumes the energy, which is stored in capacitor.
State 3[S 1 OFF and S 2 ON]: In this situation, D 1 is on-state and provides path for inductor freewheeling. Besides, output voltage is maintained by energy-releasing capacitor. The state is displayed in Fig. 6 (c).

State 4[S 1 OFF and S 2 OFF]:
Inductor discharges by the way of two diodes and hence inductor current declines, which is described in Fig. 6 (d). As a consequence, capacitor is charged and load is supplied by L.

C. IMPACTS OF PHASE-SHIFTED ANGLE ON RIPPLE CURRENT
If duty offset is zero, the two duty cycles are equal. Based on the above, the phase-shifted angle under SM is zero while that under IM is 180 degrees. With positive duty offset, it is always satisfied that d 1 > d 2 . To deeply research the influence of phase-shifted angle on inductor ripple current with duty offset, the whole range of ϕ/360 is divided into four sections firstly because it affects the switching states and duration time of each state quite a lot. In fact, whether U i > U o or U i < U o , three critical points are common for ϕ/360, namely Considering buck mode first, where d 1 + d 2 < 1, take the section (0, d 1 − d 2 ) as an example to calculate the inductor ripple current. As Fig. 7 (a) depicts, four intervals constitute a complete switching period. Detailed analysis is presented below, and i Ln represents the variation of inductor current in each interval.
Interval 1[0∼t 1 ]: Converter works at State 1 and the duration time is (ϕ/360)T S . The inductor is in charging process and its current rises up owing to positive terminal voltage. Following volt-second balance rule, it is obtained that Interval 2[t 1 ∼t 2 ]: DSBBC functions at State 2 and it lasts d 2 T S . Thus, variation of inductor current is expressed as Interval 3[t 2 ∼t 3 ]: Status of all components in this interval is the same as that in Interval 1 while t 3 Abiding by volt-second balance, it is satisfied that Combined with (10), (11), (12) and (13), when ϕ/360 is located in (0, d 1 − d 2 ), inductor ripple current at buck mode is acquired by where f S is the switching frequency. In a similar way, when ϕ/360 lies in ( , the inductor ripple current in those cases could be deduced one by one according to Fig. 7 (b), (c) and (d). The corresponding expressions of I L are summarized in Table 1.
As for boost mode, where d 1 +d 2 > 1, section (1 − d 2 , d 1 ) is taken for instance to derive I L . As Fig. 8 (c) displays, a whole period is made up of four intervals.
Interval 1[0∼t 1 ]: The power circuit operates at State 2 and the sustained time is (d 2 +ϕ/360−1)T S . Hence, the increment of inductor current is expressed as Interval 2[t 1 ∼t 2 ]: Converter performs at State 1 and it lasts as long as (1 − d 2 )T S . Therefore, the decrement of inductor Interval 3[t 2 ∼t 3 ]: Working state of converter stays the same as that in Interval 1 and this process continues for (d 1 − ϕ/360)T S . Then, i L3 is calculated by Interval 4[t 3 ∼t 4 ]: DSBBC is at State 3 and length of the interval is (1 − d 1 )T S . Ignoring on-state voltage drops on semiconductors, inductor current keeps constant, which is considered as Combined with (15), (16), (17) and (18), when ϕ/360 is situated in (1 − d 2 , d 1 ), inductor ripple current at boost mode is attained by Likewise, when ϕ/360 evaluates in (0, d 1 − d 2 ), (d 1 − d 2 , 1 − d 2 ) or (d 1 , 1), I L could be derived according to Fig. 8 (a), (b) and (d) respectively. The corresponding expressions of I L are listed in Table 2. On the basis of Table 1 and Table 2, curves of I L versus ϕ/360 are plotted in Fig. 9 to make the variation trend clear and definite. From Fig. 9 (a), at buck mode, the ripple current experiences four stages successively when ϕ/360 ranges from 0 to 1. Particularly, they are remaining unchanged at first, decreasing secondly, remaining unchanged then and increasing finally. Besides, the maximum and minimum values of I L are And the minimum I L is achieved in section (d 1 , 1 − d 2 ), which is the concern of this paper. In other words, when ϕ/360 varies between d 1 and 1 − d 2 , I L is the lowest in the whole range of ϕ/360 and it keeps constant despite the profile of inductor current. From Fig. 9 (b), inductor ripple current at boost mode undergoes the same variation process as buck mode while the maximum and minimum values of I L are Actually, the minimum I L is achieved in section (1 − d 2 , d 1 ). According to (20) and (21), I L could even reach zero theoretically if d 1 + d 2 = 1. As a matter of convenience, (d 1 , 1 − d 2 ) at buck mode and (1−d 2 , d 1 ) at boost mode are named as the optimized sections for ϕ/360. According to (2), length and endpoint locations of (d 1 , 1 − d 2 ) or (1 − d 2 , d 1 ) vary with different d. However, ϕ mid / 360, the midpoint of optimized sections, is unchanged, which is evaluated as  Once duty offset c is selected, the midpoint location is confirmed as (22) expresses. And ϕ OPS is called the optimal phase-shifted angle (OPSA) in this paper. The OPSA is convenient for digital implementation because it shares the uniform expression whether at buck or boost mode. In addition, it is independent of d, which is impossible for the other locations in optimized sections. Hence, some repetitive tasks are effectively avoided if DSP or other digital microprocessors is utilized, including initialization for PWM modules under different operating conditions and calculation of phaseshifted angle in each switching period. This virtue eases the computing burden of microprocessors to some extent.
The key waveforms of DSBBC under proposed IMOPS are drawn in Fig. 10 Fig. 10 (a) and t 3 −t 2 = t 1 −t 0 = (d −0.5)T S in Fig. 10 (b). Specially, if duty offset is zero, then converter functions on condition that d 1 = d 2 and ϕ is 180 degrees. Actually it is just the typical feature of IM, so IM is viewed as a special case of IMOPS.
From another perspective, the peak value of inductor current, I PEAK , is usually taken into consideration to minimize current stress and enhance efficiency. So it is necessary to compare the proposed IMOPS with the scheme to achieve lowest I PEAK . Actually, I PEAK could be deduced in a similar way. At buck mode, the lowest I PEAK is achieved when ϕ/360 = d 1 . As for boost mode, lowest peak current is achieved when ϕ/360 = 1 − d 2 . However, I PEAK doesn't decrease obviously because I L keeps constant with the same I L in the optimized section. According to the definition, ratio of DPT is the same under two schemes, which indicates the same efficiency. That's to say, inductor ripple current and converter efficiency couldn't be further optimized with the same L even if I PEAK is lowest. What's more, there are obvious disadvantages to realize the lowest I PEAK , which are mentioned in the previous paragraph. By contrast, these issues are avoidable in IMOPS. Based on the above analysis, the proposed IMOPS has more benefits than the scheme to realize the lowest I PEAK .

D. DIVISION OF OPERATING REGION
As shown in Fig. 11, to draw a distinction between 180 degrees and OPSA, the whole operating region is divided into four parts according to d 1 and d 2 , including Region A, B, C, and D. The input voltage is stepped down in Region A and B while it is stepped up in Region C and D.
Note that 180-degree phase-shifted angle is equivalent to that ϕ/360 = 0.5. At buck mode, when 0.5 lies between d 1 and 1 − d 2 , it is satisfied that Combined with (2) and (5), it is obtained that When 0.5 is outside the optimized section, namely Further, it is acquired that Thus, it is summarized that at buck mode, when d meets (24), DSBBC operates in Region A. If so, the same ripple current is shared under IMDO and IMOPS. And when d satisfies (26), DSBBC operates in Region B. In that case, the ripple current under IMOPS is lower than that under IMDO.
At boost mode, when 0.5 is in (1 − d 2 , d 1 ), namely Combined with (2) and (5), it is obtained that When 0.5 is outside (1 − d 2 , d 1 ), that is Further, it is acquired that Therefore, it is concluded that at boost mode, when d meets (28), DSBBC operates in Region D. If so, the same ripple current is shared under IMDO and IMOPS. When d satisfies (30), DSBBC operates in Region C. In that case, the ripple current under IMOPS is reduced compared to IMDO. Furthermore, with fixed output voltage, a threshold value U th1 for input voltage could be calculated with d equal to 0.5 − c if converter works at buck mode. In virtue of U th1 , Region A and B are distinguished. Accordingly, if converter works at boost mode, another threshold value U th2 is obtained when d = 0.5 +c. With the help of U th2 , Region C and D are told apart.

III. COMPARISONS OF DIFFERENT MODULATION SCHEMES A. POWER TRANSFER STYLE
At State 1, DSBBC is in the progress of DPT. Therefore, the ratio of DPT, P direct /P L , is calculated by duration of State 1 occupying T S . The ratio is a quantitative index to indicate efficiency, which considers I L and I L comprehensively. Only with I L and I L , efficiency under different modulation schemes could not be distinguished in some cases. But the ratio could give comparative results directly. Thus, the ratio of DPT is necessary to be discussed independently.
In particular, P direct / P L under IMDO is calculated by With IMOPS scheme applied, the ratio is expressed by As for IM, the ratio is given by  When converter operates under CC, the ratio is Under SM scheme, the output power is entirely acquired from energy-storage inductor. Thus the ratio is zero.
In this section, U i ranges from 12V to 60V and c is set as 0.2. Therefore, U th1 is 54V and U th2 is 16.7V respectively.
In Fig. 12, ratio of DPT is always zero under SM. As for IM, the ratio increases up to 0.5 until U o = U i and afterwards decreases gradually. For CC, the ratio rises up to one in scale while U i < U o , and declines in inverse proportion while U i > U o . When DSBBC works under IMDO scheme, the ratio increases on condition that U i < 16.7V, remains unchanged at 0.5 on condition that 16.7V < U i < 54V, and decreases on condition that U i > 54V. The ratio under IMDO is always higher than that under IM. If U i < 16.7V or U i > 54V, the same ratio is shared by IMOPS and IMDO. And in other cases, IMOPS makes the ratio higher. This conclusion indicates less power losses and higher conversion efficiency under IMOPS in contrast with IMDO when U i varies from U th1 to U th2 .

B. AVERAGE AND RIPPLE CURRENTS OF INDUCTOR
Under CC, inductor average and ripple currents in DSBBC can be formulated as When converter works under SM, I L and I L are where If IM method is applied in DSBBC, I L is the same as that under SM. In the meantime, its ripple is expressed by With IMDO employed, I L is calculated by (9) and I L is With regard to the proposed IMOPS, I L is exactly as that under IMDO. What's more, I L is divided into two cases according to U i and U o , which is assigned by In Fig. 13, U o is maintained at 30V. When U i goes up, I L drops under CC (boost) and it keeps constant under CC (buck). What's more, inductor average current under IMDO and IMOPS declines continuously, which is always lower than that under SM and IM.
In Fig. 14, curves of I L versus P L under different modulation schemes are plotted when U o is fixed at 30V. Input voltage is 60V and 15V in Fig. 14 (a) and (b) respectively. By comparison, I L under IMDO and IMOPS is obviously lower than that under SM and IM whether U i < U o or U i > U o . In fact, the average current under SM and IM is (1+2c) times of that under IMDO and IMOPS, which is deduced from (9) and (38). And I L under IMDO and IMOPS is slightly higher than that under CC.
In Fig. 15, curves of I L versus U i under different modulation schemes are depicted when U o keeps unchanged. With the same L, the inductor ripple current under SM is highest while that under IM is lowest. The I L under IMDO, IMOPS or CC lies between the two limitations respectively. In the case of (25) and (29), I L is reduced under IMOPS compared to IMDO. In else case, I L under IMOPS is the same as that under IMDO. Particularly when U o is equal to U i , the I L under IMOPS, IM or CC could reach zero in theory.

IV. EXPERIMENTAL VERIFICATIONS AND ANALYSIS A. EXPERIMENTAL SETUP AND PREPARATIONS
With TMS320F28335 as core chip, a 150W prototype is built to demonstrate the validity of the proposed modulation VOLUME 9, 2021   scheme. Photograph of the dc/dc converter is shown in Fig. 16 and main parameters are listed in Table 3.
Two MOSFETs constitute a half bridge. One switch works in PWM style while the other is always turned off. And inductor is connected with midpoints of two bridge arms. In addition, a 3kW dc power supply functions as the input source of converter while a variable resistor (5.7 to 40 ) performs as the load. Current sensor LA50P is used for inductor current sampling while voltage sensor CHV600VD is employed to measure output voltage.
First of all, DSBBC is made to operate as conventional buck converter and boost converter separately. According to the above-mentioned definitions and testing rule, D min and D max are found out to be 0.02 and 0.98 respectively. And c is chosen as 0.2 according to (3) subsequently. Note that the lowest input voltage in practice is set at 15V, rather than 12V in Fig. 12 and Fig. 13. Because 12V is the lowest input voltage in ideal conditions that d 1 = 1 and on-state voltage drops are ignored. Then, 60V, 45V, 25V and 15V are selected as input voltage one by one, which are corresponding to operating point in Region A, B, C and D with output voltage fixed at 30V.

B. STEADY TESTS
In the steady tests, switching frequency is fixed at 2kHz. With different input voltage, Fig. 17, Fig. 18, Fig. 19, and Fig. 20 show the inductor ripple currents under five modulation schemes. Waveforms from top to bottom are S 1 driving signal u GS1 (20V/div), S 2 driving signal u GS2 (20V/div), i L (1A/div) and u L (50V/div) respectively with common horizontal scale 250µs/div. And crucial values are summarized in Table 4.   According to the experimental waveforms, peak-peak value of i L under SM is always the highest while that under IM keeps the lowest. When U i is 60V and 15V, inductor ripple current under IMOPS is equal to that under IMDO while I L under IMOPS is obviously reduced compared to IMDO when input voltage is 45V and 25V. In addition, I L under CC is always between the highest and lowest ones. These results match well with Fig. 15.
As for inductor average current, CC makes it lowest compared with the other schemes. In fact, I L under IMOPS is  identical to that under IMDO. And the same case exists between SM and IM. Therefore, taking CC, IM and IMOPS for comparison is enough. With output current I o fixed at 4.53A, Table 5 presents I L under CC, IM and IMOPS when input voltage varies from 60V to 15V. It could be analyzed that I L rises when U i falls because duty cycles of both switches become larger. On the same condition, inductor average current under IMOPS declines much in comparison with IM thanks to a smaller d 2 . Besides, IMOPS has increasingly obvious superiority in terms of I L when U i decreases. This feature agrees with experimental results in [23].
To confirm the influence of modulation schemes on losses, efficiency curves under CC, SM, IM, IMDO and IMOPS are depicted in Fig. 21 respectively, where load power P L VOLUME 9, 2021  varies from 21W to 156W. It reveals that when input voltage is 60V and 15V, the efficiency under IMDO and IMOPS almost agrees with each other as a result of the same I L and I L . And when input voltage is 45V and 25V, the efficiency under IMOPS is further enhanced due to reduced I L . Thus, the gap of efficiency between CC and IMOPS is narrowed compared with that between CC and IMDO.
In addition, IMOPS makes DSBBC much more efficient than SM and IM in the whole range of input voltage and load power generally. And the advantage on efficiency becomes more prominent with heavier load and lower input voltage. It is because the deviation on inductor average current is much larger in that case, and loss gap is further amplified.

C. TRANSIENT TESTS
In the transient tests, dual-loop control is adopted to achieve mode transition under five modulation schemes. To obtain better transient performance, switching frequency is fixed at 30kHz and it keeps unchanged during the whole process.
Proportional-integral (PI) controllers are utilized for both inner current loop and outer voltage loop. Here, k pi and k ii represent proportional and integral parameters of current controller while k pv and k iv are proportional and integral parameters of voltage controller respectively.
In practical DSP program, the value of period register is 2500 and time-base counter works in count-up mode.
On account of duty offset and effective duty cycles, the maximum of d is set as 4950 for CC. To realize the effective control, it is 2450 for SM and IM while it is 1950 for IMDO and IMOPS. Under CC, k pi and k ii are 200 and 16.7 while k pv and k iv are 0.6 and 0.0004. Under SM and IM, k pi and k ii are 153 and 3.6 while k pv and k iv are 1.5 and 0.003. Under IMDO and IMOPS, k pi and k ii are 165 and 6.2 while k pv and k iv are 0.85 and 0.015. Fig. 22 shows the transition from buck to boost mode while Fig. 23 shows the process from boost to buck mode. Waveforms from top to bottom are instantaneous input voltage u i (40V/div), instantaneous output voltage u o (40V/div), u GS1  (20V/div) and u GS2 (20V/div) respectively with common horizontal scale 25ms/div. Under CC, limitations of effective duty cycles cause discontinuity of voltage gain near one. Due to that, obvious ripples of output voltage exist during mode transition. For smooth transition, additional transition strategy or compensation technique is essential to eliminate the negative effects.
In this respect, the other four schemes are advantageous because both switches are working in PWM style and the two duty cycles are always between D min and D max when u i approaches u o . Thus, voltage gain is continuous in the neighborhood of one and adverse effects from discontinuous voltage gain are avoided. As a result, output voltage is almost not influenced during mode transition.

V. CONCLUSION
Based on IMDO, to further decease inductor ripple current, interleaved modulation with optimized phase shifting (IMOPS) is presented for DSBBC in this paper. On condition that duty offset exists, impacts of phase-shifted angle on inductor ripple current are deeply researched. Then, optimized section for phase-shifted angle at buck and boost mode is confirmed respectively to achieve the lowest ripple current. To facilitate digital implementation, the optimal phase-shifted angle is set at the midpoint of the above section, rather than 180 degrees, because it is independent of control signal and has consistent form whether at buck or boost mode. Compared with CC, obvious ripples of output voltage are avoided during mode transition because both switches under IMOPS are working in PWM style and voltage gain is continuous near one. Compared with IM, remarkable efficiency promotion is achieved under IMOPS owing to reduced inductor average current, let alone SM. Despite identical inductor average current, lower ripple current and higher efficiency are achieved under IMOPS than those under IMDO if conditions related to control signal are satisfied. On the same conditions, steady and transient tests under five modulation schemes are conducted on a 150W prototype respectively. Experimental results validate the correctness and effectiveness of the proposed IMOPS.