State-of-Charge Balancing Control for Optimal Cell Utilisation of a Grid-Scale Three-Phase Battery Energy Storage System Using Hybrid Modular Multilevel Converter Topology Without Redundant Cells

Cell state-of-charge (SoC) balancing within each branch of a three-phase battery energy storage system (BESS) and among three branches is crucial to overcome the inability to fully utilise the available capacity of a three-phase BESS. The proposed topology is constructed with one branch instead of three branches to take advantage of its idle cells/modules (Ms) (one-third of the total cells/ Ms) and to eliminate the need of SoC balancing among the branches. Contrary to conventional topologies, idle cells/ Ms can serve as redundant cells/ Ms or can be dropped out of a BESS, thereby leading to a reduction in the cost, control complexity, size, and losses of a BESS. A novel SoC balancing strategy for the proposed topology of a three-phase BESS is introduced in this paper. Moreover, the cell/M activation algorithm is implemented to minimise the duration needed to activate the cells/Ms required to generate voltage for the phases, thereby leading to an improvement of battery operational efficiency. Based on the simulation results, SoC balancing among 3996 cells, 2664 cells, 333/222 Ms, and 12 cells in M with the lowest and the highest average SoC is achieved in 53 min, 48 min, 38 min, 18 min and 53 min, respectively.


I. INTRODUCTION
The wide use of distributed generation based on renewable energy is one of the most effective solutions in the power industry for addressing global environmental issues [1]. However, voltage instability, poor power grid quality, frequency fluctuation, and load discrepancy are the main notable challenges faced during the integration of renewable energy sources (RESs) [2]. The integration of energy storage systems (ESSs) with RESs into the power grid is a promising solution to overcome these limitations and to obtain grid stability [2]. In addition, it can improve power quality through The associate editor coordinating the review of this manuscript and approving it for publication was Zhilei Yao . voltage and frequency regulation as well as avoiding power fluctuations by providing backup electricity [3], [4]. Consequently, many ESS technologies have emerged in recent years that can be classified into mechanical, electrical, chemical, and electrochemical storage systems. Electrochemical energy storage technologies are rechargeable battery energy storage systems (BESSs) that store electrical energy in the form of chemical energy [5]. Compared with batteries, such as nickel-cadmium cell and lead-acid cell, lithium-ion (Li-ion) cells have been widely used in BESSs because they are characterised by several features such as high energy density, fast charge/discharge capability, long life span, and low self-discharge rate [6], [7]. Nevertheless, cell parameter difference poses major drawback, which occurs during BESS operation or due to manufacturing tolerance. Accordingly, the state-of-charge (SoC) imbalance occurs among the cells within a BESS [8].
In the conventional topology, a three-phase BESS is constructed using three branches. Each branch (phase) consists of numerous cells, which are connected in series and/or parallel to generate the required voltage and capacity [9]. The available capacity of the BESS is limited by the cells with the lowest/highest capacity where cells must not be overcharged and/or deeply-discharged, otherwise cells will be damaged and thus destroying the entire BESS eventually [10]. Therefore, during charging and as a result of cell parameter differences, the strongest cell (highest capacity) within a BESS reaches its upper voltage limit firstly, thereby terminating the charging operation, while the remaining cells are not completely charged. On the other hand, the weakest cell (lowest capacity) reaches its cut-off voltage firstly during discharging, thereby terminating the discharging operation, while the capacity of the remaining cells is not yet exhausted (still available) [11], [12]. Consequently, BESS typically requires a SoC balancing system [13].
Cell balancing circuits are either passive or active according to their energy handling ways [14]. In passive balancing, excess energy is eliminated through resistors, whereas in active balancing, additional storage devices (inductors, capacitors) are used to transfer the energy among the cells via small shunt currents [15]. The passive balancing circuit is the most common approach because of its low-cost and easy implementation [16]. However, its disadvantage is that energy is dissipated as heat, which is inefficient and difficult to deal with, particularly in space-restricted applications. On the other hand, active balancing circuits are not dissipative, but rather the circuits seek to individually monitor and control the SoC of cells during charging and discharging so that SoC balancing among cells is achieved at all times of BESS operation. Though numerous types of active balancing approaches have been proposed, they mainly focus on the architecture of the cell-balancing circuits which can be classified into three main categories: the adjacent cell-to-cell (A-C2C) [17], [18], the direct cell-to-cell (D-C2C) [19], [20], and the cell-to-pack (C2P) [21], [22]. The A-C2C architecture involves balancing circuits based on the switched capacitor converter, the Ćuk converter, and the bidirectional buck-boost converter. The A-C2C owns advantages such as simple structure, low cost, and modular design. However, its main drawback is that energy can only be transferred between adjacent cells, which consequently increase cell balancing duration and energy losses. Contrary to A-C2C, the D-C2C architecture can transfer the energy between any two cells regardless of their positions. However, since there is only one balancing circuit, only two selected cells can be balanced at the same moment. Thus, the balancing duration will be increased significantly when a high number of cells is imbalanced. The D-C2C architecture includes balancing circuits based on the quasiresonant, the shared inductor, and the flying capacitor converters. Flexible balancing is provided in the C2P architecture by transferring energy between the individual cell and a pack of cells. In the C2P architecture, multiple transformers or multi-winding transformer is used where each cell requires a winding to step up the voltage [21]. Thus, compared to A-C2C and D-C2C architectures, C2P architecture suffers from increased cost, losses, and volume. However, it has the highest balancing speed.
Duty cycle balancing (DCB) architecture is a subcategory of active cell balancing circuits. Cell balancing is implemented by controlling the duty cycle of each cell based on their corresponding SoC [23]. Contrary to the previous architectures where all the cells are in the current path at all time, the fundamental idea of DCB is to bypass the cells during the system operation which requires integrating additional switches (in form of L-bridge or H-bridge) into each cell and/or a pack of cells [24]. Accordingly, the inclusive of redundant cells is a requirement for DCB circuits to meet the desired output voltage when some cells are bypassed. Modular multi-level converter using a cascaded H-bridge (CHB) has been widely used in BESS applications because they are characterised by using MOSFET switches, reducing output voltage harmonics, and possessing inherent modularity [25]. Moreover, SoC balancing among phases and cells/Ms within a single phase can be obtained in a CHB-BESS without additional balancing circuits [26], [27]. However, the zero-sequence voltage (ZSV) injection method is required to obtain SoC balancing among three phases, which cannot be applied without redundant cells/Ms [28]- [30]. The ZSV injection method has been described in [26], [29]. Note that the inclusion of the redundant cells/Ms in BESS increases the total cost of the BESS, control complexity, size, and losses. However, it is required in the conventional topology to prevent unnecessary shut-down of a BESS when several cells are dropped out for replacement/maintenance [31].
In [32], [33], CHB multilevel converter is used to integrate cells to the grid where each pack of cells (M ) is linked to a single H-bridge. SoC balancing among Ms can be obtained by controlling their duty cycle, whereas it cannot be achieved among the cells within each M . In [26], [28], [33], ZSV injection method is used to obtain SoC balancing among three phases of a BESS. Nevertheless, an auxiliary battery management system (BMS) is necessary to obtain SoC balancing within each M (internal cells), which is achieved in [28] by developing a multi-level BMS where a multi-winding transformer is utilised to obtain SoC balancing among the cells, whereas SoC balancing among Ms is obtained by linking each M into H-bridge and releasing its power (of each M ) according to its corresponding SoC. In [11], [26], each cell is integrated into an H-bridge to obtain SoC balancing at cell level without additional BMS or components. Moreover, controlling and monitoring each cell can be obtained by integrating each cell into H-bridge. Consequently, the BESS reliability can be increased by isolating (dropping out) the failed cells for replacement/maintenance without affecting the entire system. In [26], the control complexity of a BESS is addressed through a hierarchical control strategy. However, its drawbacks involve utilising a huge number of switches, the inclusion of the redundant cells/Ms, and requires peak sharing algorithm [26]. The number of switches is reduced by using the hybrid modular multi-level converter in [34], whereby each cell is linked to L-bridge, while each M is linked to H-bridge. Moreover, an additional circuit (parallel module dual L-bridge) is used to minimise the duration needed to obtain SoC among cells/Ms, but SoC balancing among phases cannot be addressed. Note that in a grid-scale BESS, a significant number of cells is necessary to generate the desired output voltage (V out ), thereby determining the cells required to generate each level of V out during a short duration (normally corresponds to 10 ns [35]) is crucial. In [26], [35], the required cells are activated one after another until V out is closer to V ref . The total voltage of the activated cells is compared to V ref after activating each cell. Therefore, a long duration is required to activate all the cells required to generate each level of V out . Accordingly, a new algorithm is necessary to minimise the duration needed to activate the cells/Ms required to generate each level of V out .
In the literature, when various balancing circuits are compared, evaluation criteria such as the efficiency, balancing speed, size, and cost are often qualitatively evaluated by assigning grades such as 'excellent/high', 'good/medium', and 'poor/low' [16]. Moreover, all compared cell balancing circuits should be designed under the same considerations; otherwise the quantitative comparisons will not be very meaningful. A summary of efficiency, reliability, control complexity, cost, size, losses and, control and monitoring of each cell for the proposed SoC balancing strategy compared to existing balancing strategy is presented in Table 1. In Table 1, efficiency and reliability are evaluated based on balancing speed, cost, size, losses, the ability to control and monitoring each cell, and the ability to meet V ref when several cells/Ms are dropped out for replacement/maintenance. Control complexity is evaluated according to the number of control and sensing signals. This paper has two main contributions. First, a new topology of a three-phase BESS using three cascaded hybrid modular multi-level converters (TCHMMC) is proposed. Compared to the conventional topologies, the proposed topology is designed to generate output voltage for a three-phase BESS via one branch rather than three branches without redundant cells. As a result, one-third of the total cells is idle and isolated from the system. These idle cells can serve as redundant cells or they can be eliminated from a threephase BESS. Therefore, the total number of the required cells for a three-phase BESS can be reduced by one-third without affecting its output power rating (P out ). Accordingly, control complexity, size, losses, and BESS total cost can be reduced. Moreover, in the proposed topology, SoC balancing among branches (phases) is not required, where one branch is utilised to generate a three-phase multi-level output voltage (V outa , V outb , and V outc ).
The second contribution is that a novel SoC balancing strategy of a three-phase grid-scale BESS is proposed. Moreover, a novel cell/M activation algorithm is proposed to minimise the duration needed to activate the cells/Ms required to generate each level of V outa , V outb , and V outc by activating most of the required cells/Ms as explained in Section III with improved operational efficiency of a BESS. Contrary to the different SoC balancing strategies introduced in the literature, the proposed SoC balancing strategy begins by using current-prioritised (as explained in Section III) which aims to take advantage of the highest current among the three-phase currents to charge or discharge the cells/Ms with the highest priority during each time step of the duty cycle. Accordingly, the proposed SoC balancing strategy can be summarised in two main steps: First, based on M -prioritised (as explained in Section III), Ms with lowest priority will be activated to generate two output voltages that have the lowest two relative currents. Second, based on cell-prioritised (as explained in Section III), cells with highest priority will be activated to generate the output voltage that has the highest relative current. Note that the use of the highest current with cell-prioritised aims to address SoC balancing among cells in M . The methodology of the proposed topology is described in Section II. The SoC balancing strategy for the proposed topology of a three-phase BESS is explained in Section III. The simulation results of the proposed SoC balancing strategy are discussed in Section IV. The experimental set-up is presented in Section V while the conclusion of the study is provided in Section VI.

A. PROPOSED TOPOLOGY CONFIGURATION
The proposed topology configuration of a three-phase BESS and operational statuses of each H-bridge and L-bridge are illustrated in Fig. 1. Compared to the conventional topologies, the proposed topology is constructed using one branch instead of three branches to generate V refa , V refb , and V refc through TCHMMC. The proposed topology consists of Z Modules (Ms), N cells/Sub-modules (SMs), three cascaded H-bridges (TCHB) (from Hsw a1 , Hsw b1 , and Hsw c1 until Hsw az , Hsw bz , and Hsw cz ), and an auxiliary switch linked to each H-bridge (sw az , sw bz , and sw cz ). Z, K, and N (= Z × K ) refer to the number of Ms, the number of cells/SMs in M , and the total number of cells/SMs, respectively. In this paper, K is unified for all Ms [36].
In Fig. 1a, three H-bridges connected in parallel of TCHB are linked to the next three H-bridges, which are connected in parallel via three ports, and so on (e.g., Hsw a1 , Hsw b1 , and Hsw c1 are linked to Hsw a2 , Hsw b2 , and Hsw c2 , respectively). The upper three ports of TCHB are linked to the electrical grid to generate V refa , V refb , and V refc whereas the lower three ports of TCHB are linked together. Each phase is linked to a certain CHB of TCHB. To avoid the overlapping of three-phase currents of the electrical grid (short-circuit), an auxiliary switch is linked between the upper end of each H-bridge and its corresponding M, as presented in Subsection B, Section II. Each cell is linked to L-bridge. M consists of K cells connected in series via cascaded L-bridge. The lower end of each H-bridge and its corresponding M are connected together. Accordingly, before a BESS starts operation, each M is linked to its related H-bridges in parallel and series with other Ms via TCHB, whereas during the BESS operation, each M is linked to a single H-bridge of its related H-bridges in parallel and in series with other Ms, which are linked with the same CHB, as presented in Sub-section B, Section II. The proposed topology is, therefore, constructed within one branch. Fig. 1b and 1c show M related switches statuses (either ON (1 or −1) or OFF (0)) and their effect on the voltage across M and SM (V M and V C ). The voltage across H-bridge (Hswz) will be equal to +V M , −V M , and 0 when H-bridge is 1, −1, and 0, respectively as shown in Fig. 1b. Note that current (I) will not pass through M when the voltage across its related H-bridge is equal to 0. The voltage across Lswk will be equal to a cell voltage +V C or 0 (i.e., the cell is idle) when Lswk is 1 or 0, respectively as shown in Fig. 1c. Consequently, V M value is selected according to the number of its activated cells (e.g., assume that M contains eight cells, six cells are activated while the remaining two cells are unutilised. Therefore, the V M value is equal to the sum of the voltages of these activated cells).

B. OPERATING PRINCIPLE AND CELLS/MODULES DISTRIBUTION INTO A THREE-PHASE
Each cell is independently controlled by linking it with an L-bridge. The failed cells can, therefore, be dropped out for replacement/maintenance without affecting the BESS operation. Many cells/Ms are linked with each other in series to generate V out close to V ref . During BESS operation, each M is linked into an H-bridge to generate a sinusoidal V out as shown in Fig. 2. In Fig. 2, each duty cycle (0 to π is split into several T S , where a certain level of V out is generated during each T S . At the beginning of each T S (at t 1 , t 2 , and so on), the cells/Ms required to generate each level of V out is activated based on the cell/M activation algorithm as explained in Section III. During each T S , the cells' statuses (1 or 0) are determined based on SoC balancing strategy presented in Section III. The T S value is calculated based on (1), which affects the voltage step of V out (i.e., in Fig. 2 . Note that Ts is unified during the BESS operation. Consequently, in order to generate V out as close as possible to V ref , (1) is designed to achieve a voltage step as close as possible to a single V C [26]. Note that T S is selected before BESS starts operation. Therefore, to make sure that each voltage step of V out is as close as possible to V C , the V C value in (1) is chosen as the cell cut-off voltage depending on the based on the manufacturer datasheet Each simulation time (t 1 , t 2 , and so on) is equal to the previous simulation time along with the T S value (i.e., t 3 The fundamental idea of the proposed topology involves using one branch rather than three branches to generate V refa , V refb , and V refc via TCHB. As a result, one-third of the total cells/Ms is idle and isolated from the remaining cells/Ms [36]. During each T S , Ms are split into three isolated groups and idle Ms as shown in Fig. 3. Splitting Ms into three groups can be obtained by controlling their corresponding switches as presented in Fig. 4. To avoid the overlapping of three-phase currents of the electrical grid (short-circuit), complete isolation among these groups must be obtained (1) prior to the utilisation of their corresponding Ms. All the cells/Ms take part to generate each level of V refa , V refb , and V refc . Nevertheless, there is no certain cell/M for a specific phase. Note that during each T S , each M can only be used in a single group. In Fig. 3 (2). The term Block is the activated H-bridge (1 or −1) and its corresponding auxiliary switch. Fig. 4 shows three scenarios to activate M 1 during each specific T S . M 1 is connected to different phase (Ph b , Ph c , or Ph a ) during each scenario.
Moreover, Fig. 4 shows the method utilised to isolate M 1 from the remaining phases once it is selected to be within a certain phase (e.g., once M 1 is selected to be within Ph a , it is isolated from Ph b and Ph c as shown in Fig. 4a). In Fig. 3 and Fig. 4a, during each T S , only a single H-bridge of three H-bridges connected in parallel, are linked (ON (1 or −1)) into their corresponding M , while the remaining two H-bridges are OFF (0). In Fig. 3, the total voltage across (M a1 -M aw ), (M b1 -M by ), and (M c1 -M ce ) should be as close as possible to V refa , V refb , and V refc , respectively. In Fig. 4, M 1 is linked to three H-bridges (Hsw a1 , Hsw b1 , and Hsw c1 ) of TCHB via their auxiliary switches (sw a1 , sw b1 , and sw c1 ) before starting the operation of the BESS. Nevertheless, during each specific T S, only a single H-bridge is linked (ON (1 or −1)) to M 1 once starting the operation of the BESS, while the remaining two H-bridges are OFF (0) as presented in Fig. 4a, Fig. 4b, and Fig. 4c. In Fig. 4a, M 1 is linked only to Hsw a1 (Hsw a1 is ON (1 or −1)), which means that I a flows through M 1 . In Fig. 4a, Hsw b1 and Hsw c1 are OFF (0), which means that I b and Ic do not flow through M 1 . Similarly, in Fig. 4b and Fig. 4c, M 1 is linked only to Hsw b1 and Hsw c1 , respectively.
The proposed topology is able to create a huge number of idle cells/Ms (up to more than one-third of the total cells/Ms) at any given time of the BESS operation. Accordingly, the proposed SoC balancing strategy is designed to be able to achieve SoC balancing among cells/Ms with/without a huge number of idle cells/Ms as described in Section III. However, the major drawback of conventional topologies is the inability to take advantage of idle cells/Ms. On the other hand, the proposed topology has key advantages, involving the result of dealing with its idle cells using three methods [36]. First, they can be dropped out of the BESS plant, while still achieve the desired P out . Second, they can be served as redundant cells and, therefore, the inclusion of the redundant cells is not required. Third, during peak demand, they can be used to meet the desired P out . As a result, the total cost of the BESS, control complexity, size, and losses were significantly reduced, whereas reliability increased.

C. THE DIFFERENCE IN THE NUMBER OF IDLE CELLS DURING CHARGING/DISCHARGING
The cell involves an internal cell voltage (V int ) and an internal resistance (R int ) according to the basic concept of cell configuration [12]. Therefore, during charging and discharging, (3) is used to calculate the cell output voltage (V C ) based on Kirchhoff's Second Law. As observed in (3), the V C value slightly increases during charging and slightly decreases during discharging due to R int . Therefore, the number of cells required to obtain V out reduced during charging and increased during discharging. Accordingly, the total number of idle cells/Ms during charging is higher than the number of idle cells/Ms during discharging.
The accuracy of the SoC estimation is one of the important keys in cell balancing. Therefore, numerous ways have been developed to achieve an accurate SoC estimation as presented in [37]. In this paper, cell SoC balancing relies on the Coulomb Counting method to estimate SoC, which is designed according to (4). The method algorithm and details are presented in [26].
(4) * Q max , SoC 0 , and I (t) refer to a maximum capacity limit of a cell, initial SoC, and current going either in/out of a cell, respectively.

III. SOC BALANCING STRATEGY OF A THREE-PHASE GRID-SCALE BESS FOR THE PROPOSED TOPOLOGY USING CONTROL STRATEGY
In TCHMMC, V outa , V outb , and V outc are generated by controlling its -TCHMMC-switching statuses as explained in Section II. In comparison with the conventional topologies, TCHMMC is constructed using one branch rather than using three branches. Accordingly, during each T S , Ms are split into three isolated groups (each group consists of numerous Ms, which are connected in series) and idle Ms, where each group is linked to a certain phase (Ph a , Ph b , and Ph c ) as illustrated in Fig. 3. Each individual M may belong to any group of these groups by controlling its related switching statuses (through the control strategy as described in Section II). Note that in conventional topologies, the ZSV method is used to obtain SoC balancing among three branches (three-phase). The ZSV method requires the inclusion of the redundant cells/Ms to be applied, which increases the total cost of BESS, control complexity, size, and losses as explained in Section I . On the contrary, in the proposed topology, V refa , V refb , and V refc are generated via only one branch and, therefore, SoC balancing among branches (phases) is not required (i.e., there is no need to include the redundant cells/Ms), which is the main contribution of the proposed topology in terms of the redundant cells/Ms and SoC balancing control among phases. In this paper, the control strategy aims to obtain SoC balancing among the cells/Ms of the proposed topology. Some control strategies have been proposed in the literature [11], [26], [34] to achieve the cells/Ms SoC balancing into each branch of the BESS branches based on the priority list. The basic concept of the priority list is to prioritise the cells with the lowest SoC during each Ts of the duty cycle during charging and vice versa. Therefore, it is wise to use the priority list to obtain SoC balancing among the cells/Ms in BESS constructed by a multi-level converter, whereby each cell/M is linked to H-bridge/L-bridge. However, the cells can be organised in a hierarchal structure (e.g., the cells in [26] VOLUME 9, 2021 are organised in a hierarchical structure, which consists of four levels as modules, sub-banks, banks, and phases. The cells in [34] are organised on three levels as sub-modules, modules, and phases). Thus, prioritising SoC balancing to cells level before Ms level (cell-prioritised) and the other way round (M -prioritised) had been proposed in [34]. Accordingly, two priority lists can be generated, including a cell priority list ( , all its related cells will be activated regardless of their SoC. Accordingly, several cells with the highest SoC will be activated during charging and vice versa). Note that in the proposed topology (one branch), even if only one cell is activated in M (to generate a certain voltage), M will be considered as activate and, therefore, its remaining cells cannot be used to generate voltage for the remaining two phases.
The cells in the proposed topology are organised in a hierarchical structure (SMs (cells) and Ms). However, SoC balancing cannot be achieved with cell-prioritised or M -prioritised alone in the proposed topology for the following reasons: 1) The fundamental idea of the control strategy when using cell-prioritised alone is to activate the cells, one after another, during each Ts of the duty cycle based on C PL to generate the desired V out . Accordingly, it is suitable for conventional topologies, which use three branches to generate V outa , V outb , and V outc . The proposed topology (one branch) is designed to generate V outa , V outb , and V outc , and the phases are generated one after another depending on the current-prioritised method as explained in this section. Thus, the activated cells and their related Ms are, therefore, assigned in a group to generate the desired V out for a phase before the cells can be used to generate voltage for the remaining two phases. The optimal number of Ms, which should be activated (NUM s ) to generate the desired V out , is calculated in (6). NUC s is the number of cells activated to generate the desired V out , while NUC s K is the least integer after dividing NUC s by K (number of cells in M ). The worst-case scenario happens when the number of Ms activated is close to NUC s which leads to the inclusion of many cells/Ms in only one group. Accordingly, when using cell-prioritised alone in the proposed topology, the drawback can occur when the remaining number of cells/Ms (after producing the desired V out for a phase) is insufficient to generate voltage for the remaining two phases of V outa , V outb , and V outc . Note that the activated Ms in the first group cannot be used again to generate the remaining two phases of V outa , V outb , and V outc during the same T S . 2) The drawback of using M -prioritised alone is that SoC balancing among cells is not achieved because all the internal cells of the activated Ms are activated to generate the desired phase of V outa , V outb , and V outc (except for the last activated M , where its cells are activated one after another until obtaining the desired V out close to V ref ) regardless of their SoC compared with other cells in the inactivated Ms. Note that to achieve SoC balancing among the cells, an additional SoC balancing circuit is used in [34]. In M -prioritised, NUC s is less than or equal to the number of the activate Ms multiplied by K . Accordingly, there are potential drawbacks when using cell-prioritised or M -prioritised alone to achieve SoC balancing in the proposed topology. Therefore, a novel SoC balancing strategy is proposed in this paper to use cell-prioritised and M -prioritised strategy, together to achieve SoC balancing among cells/Ms in the proposed topology. Fig. 7 illustrates the proposed SoC balancing strategy. Generally, to determine the number of the cells required to generate each level of V out , cells are activated one after another until V out is closer to V ref . Thus, as a result of including a significant number of cells in a grid-scale BESS, a long duration is needed to activate the cells/Ms required to generate each level of V out . Accordingly, to minimise the required duration, the cell/M activation algorithm is proposed in this paper as illustrated in Fig. 5 and Fig. 6, respectively (cell activation algorithm is used with the cell-prioritised, while the M activation algorithm is used with the M -prioritised). It activates almost all the required cells/Ms from the first step of looking for the required cells/Ms, thereby leading to an improvement in the operational efficiency of the SoC balancing strategy. Note that cell-prioritised and M -prioritised are used together during each T S of the duty cycle in the proposed SoC balancing strategy to generate V outa , V outb , and V outc as shown in Fig. 7. In Figs. 5-7, a minimum number of cells (C a,b,c min ) and Ms (M a,b,c min ) required to generate any level of V refa , V refb , or V refc is calculated by (7) and (8), respectively. A maximum number of cells (C a,b,c max ) required to generate any level of V refa , V refb , or V refc is calculated by (9). HV C and LV C are the highest and the lowest cell voltage, respectively, whereas HV M is the highest M voltage. The term V ref (a,b.c) refers to the absolute value of V refa , V refb , or V refc .   (7) and (8), respectively. Note that the lowest number and the exact number of cells/Ms required to generate V ref will be too close to each other because the difference between HV C value and LV C value is small (almost zero when SoC balancing among cells is achieved). The difference between the lowest and the exact number of the required cells/Ms will be equal to one cell/M after achieving SoC balancing among the cells because of the Greatest Integer function. The current-prioritised method is introduced to be the first step of the proposed SoC balancing strategy as illustrated in Fig. 7. The operating principle of the current-prioritised method is that during each T S of the duty cycle, the cells/Ms with the highest priority will be activated to generate V refa , V refb , and V refc (consecutively) depending on which V ref has the highest absolute value of its corresponding current (| a |, |I b |, or |I c |) (e.g., the cells/Ms with the highest priority will be activated to generate V refc , V refb , and V refa consecutively when |I c | > |I b | > |I a |), thereby taking advantage of the highest current (I h ) [see Fig. 8] to charge or discharge the cells/Ms with the highest priority throughout the BESS operation. This reduces the duration required to obtain SoC balancing among the cells/Ms compared to the following methods. First, the cells/Ms with the highest priority will be activated to generate V refa , V refb , and V refc consecutively regardless of which one of them has the highest corresponding current (e.g., V refa , V refb , and V refc will be generated consecutively even if |I c | > |I b | > |I a |). Second, dividing the cells/Ms into three groups for only one time and using each certain group of them to generate a certain V ref throughout the BESS operation (e.g., M 1 -M 111 are used to generate V refa , M 112 -M 222 are used to generate V refb , and M 223 -M 333 are used to generate V refc ). Note that using a certain current (I a , I b , or I c ) VOLUME 9, 2021 to continuously charge or discharge a certain group of cells compared with using current-prioritised method (I h is used to charge and discharge the cells with the highest priority), results in charging or discharging the cells with the highest priority by a small current during numerous T S of each duty cycle because a grid reference current is in a sinusoidal waveform as shown in Fig. 8 and Table 2. Fig. 8 demonstrates a three-phase grid reference current (I a , I b , and I c ) and I h during each T S of the duty cycle. Table 2 illustrates the absolute values of the number of coulombs (Q = t 0 I (t)dt ) flowing through the cell with the highest priority during the first half of the duty cycle for Fig. 8. I h and I a are used to calculate Q h and Q a , respectively. In Fig. 8 and Table 2, I a , I b , I c , and I h values are based on (10). As a result, the total number of coulombs (T Qa and T Qh ) flowing through the cell with the highest priority increased by 50 % ( ) when using the current-prioritised method (T Qh = 3 I peak ) compared with using a certain grid reference current (T Qa = 2 I peak ) as illustrated in Table 2. The effect of the utilisation of the current-prioritised method on the duration required to charge a specific cell compared with using a certain grid reference current to charge the same cell is shown in Fig. 9. In Fig. 9, to charge a particular cell from 20 % to 80 % of  SoC, 100 min (duration 1) is required when using I a , I b , or I c compared to 50 min (duration 2) when using I h (a reduction of the duration by 50 % as presented in Table 2). Therefore, the duration required to obtain SoC balancing among all cells will be reduced. Note that SoC balancing among cells in each M should be achieved before Ms, which is achieved by using cell-prioritised and current-prioritised method (cells with the highest priority are charged/discharged by I h ) as presented in Fig. 7. Without using current-prioritised method, the speed of achieving SoC balancing among cells in each M will drop steeply once SoC balancing among Ms is achieved as a result of using Ms-prioritised to generate voltage for two phases (when M is activated based on M PL , all its related cells will be activated regardless of their SoC) as explained at the beginning of Section III, Fig. 6, and Fig. 7. Thus, the duration required to obtain SoC balancing among all cells will be increased. The proposed SoC balancing strategy will utilise cell-prioritised and current-prioritised to make sure that SoC balancing among all cells and Ms is achieved in almost the same duration.  In Fig. 7, the priority of producing each step of V refa , V refb , and V refc during each T S of the duty cycle is determined based on the proposed current-prioritised method.
Ms are sorted depending on their average SoC in vector M PL . Idle Ms (lowest priority) and Ms with the highest priority (based on M PL ) are used together to generate V refa , V refb , or V refc which has the highest related current using the cell activation algorithm while the other Ms are used to generate voltage for the remaining two phases using M activation algorithm. The proposed SoC balancing strategy aims to obtain SoC balancing among cells/Ms through the proposed current-prioritised method and the combination between using cell-prioritised and M -prioritised (cell/M activation algorithm). Moreover, the drawbacks of using cellprioritised or M -prioritised alone, which are described at the beginning of Section III, are addressed in the proposed SoC balancing strategy. Table 3 presents a comparison of the proposed SoC balancing strategy with the existing balancing strategy in terms of the SoC balancing approach and major limitations.

IV. SIMULATION RESULTS OF THE PROPOSED TOPOLOGY AND THE PROPOSED SOC BALANCING STRATEGY
In order to verify the performance of the proposed topology [see Fig. 1a] and the proposed SoC balancing strategy [see Fig. 9], the simulation model has been constructed in MAT-LAB Simulink software (R2017b). The cell model has been built based on [12]. The Coulomb Counting method described in [26], which is used to estimate cell SoC. The simulation model parameters are illustrated in Table 4. In this paper, the Li-ion Polymer cell is utilised, where its nominal capacity and voltage are 20 Ah and 3.65 V, respectively as shown in [38]. The proposed SoC balancing strategy is validated in the proposed topology using two case studies. The different number of cells/Ms is used in each case study. In case study 1, 3996 cells (333 Ms) are used, while in case study 2, 2664 cells (222 Ms) are used. Note that in case study 1, the rated energy capacity equals 290 kWh (= 3996 × 20 × 3.65), whereas it equals 194 kWh (= 2664 × 20 × 3.65) for case study 2. Fig. 10 and Fig. 11 highlight the proposed topology features, while Fig. 12 and Fig. 13 demonstrate the simulation results of the proposed SoC balancing strategy. Fig. 14 shows the process of splitting Ms into three groups during each T S to generate V outa , V outb , and V outc . Fig. 10 shows the ability of the proposed topology to achieve V outa , V outb , and V outc (3.6 kV) and a three-phase AC rated active power (P outa , P outb , and P outc ) (60 kW) when using 3996 cells (333 Ms) or 2664 cells (222 Ms). The number of idle Ms when using 333 Ms or 222 Ms is presented in Fig. 11. In Fig. 10a, V outa , V outb , and V outc are generated with 3996 cells (333 Ms) and 2664 cells (222 Ms). Note that the number of cells/Ms is still high enough to generate its corresponding reference voltages even after reducing the number of cells/Ms to two-thirds (2664 cells (222 Ms)) as shown in Fig. 10a and Fig. 11b. The voltage step equals the  cell voltage as a result of using a short T S (T S = 133 µs). The peak voltage (3.6 kV) for a three-phase of the reference voltage and the output voltage are identical. In Fig. 10b, P outa , P outb , and P outc are generated in both cases of the number   of cells/Ms (3996 cells (333 Ms) and 2664 cells (222 Ms)). P outa , P outb , and P outc of −55 kW and 5 kW are generated during charging whereas 55 kW and −5 kW are generated during discharging. The positive and negative polarities of P outa , P outb , and P outc refer to discharging and charging operation, respectively (i.e., when PF = 1 (ideal case), P out has a negative polarity during charging due to the VOLUME 9, 2021 voltage (V) and the current (I) have different polarities during each T S (Cos (θ ) = 1, P out = IV Cos (θ)). Similarly, the P out polarity is positive during discharging, where the polarity of V and I is negative or positive during each T S . Nevertheless, in practical cases (PF < 1), there is a discharging status (its length depends on PF value) during the BESS charging operation and vice versa, as a result of a phase shift (θ) between I and V [see Fig. 12]. In Fig. 10b, the total of the maximum AC rated active power of a three-phase is equal to 180 kW (60 kW for a phase). In conventional topologies, P out (60 kW) and V out (3.6 kV) will not be obtained when the total number of cells/Ms is reduced to two-thirds compared to the proposed topology. Fig. 11a shows a significant range of idle Ms from 164 to 188 and from 142 to 176 of total 333 Ms during charging and discharging, respectively. Note that 142 Ms are equal to 1704 cells (= 142 × 12). Thus, V out of each phase of V outa , V outb , and V outc can be increased by at least 1420 V (= (1704 × 2.5) ÷ 3) or the total number of cells/Ms can be reduced by 142 Ms (1704 cells). 2.5 V is the cell cut-off voltage. Note that more than one-third of the total cells/Ms is idle. The range of idle cells/Ms during discharging is lower than the range of idle cells/Ms during charging because of the cell voltage drop during discharging (i.e., requires a higher number of cells/Ms to generate V out ) and increases during charging as given in (3). Fig. 11b shows the number of idle Ms into the proposed topology after reducing its total number of Ms from 333 to 222 Ms. However, even with 222 Ms (two-thirds), it has idle Ms, which ranges from 61 to 84 Ms and from 28 to 56 Ms during charging and discharging, respectively. Accordingly, the proposed topology is able to isolate idle cells/Ms from activated cells/Ms during the production of V outa , V outb , and V outc as shown in Fig. 10 and Fig. 11, which is the most attractive feature of the proposed topology. These idle cells/Ms can serve as redundant cells/Ms or are dropped out of a three-phase BESS, thereby, reducing the total number of the required cells. However, the desired P out can be achieved, thereby leading to a reduction in the total cost of BESS, control complexity, size, and losses. Accordingly, the proposed SoC balancing strategy has been validated in the proposed topology when idle cells/Ms serve as redundant cells/Ms (case study 1 (3996 cells in 333 Ms)) as shown in Fig. 12 and when they are eliminated from BESS plant (case study 2 (2664 cells in 222 Ms)) as shown in Fig. 13.
It has been substantiated by the simulation results that the proposed SoC balancing strategy achieved the SoC balancing convergence among cells/Ms regardless of the existing number of idle cells/Ms. Note that SoC balancing among branches (phases) is not required for the proposed topology in this paper as explained in Section III. SoC balancing among cells, Ms, cells in M with the highest average SoC, and cells in M with the lowest average SoC are shown in Fig. 12a,  Fig. 12b, Fig. 12c, and Fig. 12d, respectively. Note that M with the highest/lowest average SoC is determined upon the start of BESS operation. In Fig. 12a, SoC balancing convergence among 3996 cells is achieved in 53 min. Note that in 53 min, the average SoC among all the cells is 70 %, which is identical to the SoC of the cell with the highest initial SoC as illustrated in Table 4. Many cells' traces are horizontal (there is no change in their SoCs) during 0 -53 min, which refers to the idle cells. During 30 -53 min, some of the cells are charging without following the fundamental concept of the priority list (the cells with the highest SoC are charged although there are inactivated cells, which have less SoC). This occurs as a result of using M -prioritised to generate voltage for the two-phase of V outa , V outb , and V outc (cell-prioritised is used to generate voltage for the phase with the highest absolute current (| a |, |I b |, or |I c |)) as explained at the beginning of Section III. This issue arises when M -prioritised is used to activate the cells (as explained at the beginning of Section III), while SoC difference among Ms is small [see Fig. 12b during 30 -53 min] and SoC balancing among cells in each single M has not been achieved [34]. However, the drawback of using M -prioritised is addressed by using the current-prioritised method in the proposed SoC balancing strategy (SoC among cells is achieved in 53 min) in this paper [see Fig. 7]. In Fig. 12b, SoC balancing convergence among 333 Ms is achieved in 38 min. Some Ms are charged, whereas others are discharged during the BESS charging operation (0 -58 min). This occurs as a result of the existence of a phase-shift between I and V (PF < 1) of each phase. Therefore, each phase status is changed from charging to discharging for a short period during each duty cycle of the charging operation, and vice versa as explained at the beginning of Section IV. In Fig. 12c, SoC balancing convergence among 12 cells in M with the highest average SoC is achieved in 53 min compared with 18 min for 12 cells in M with the lowest average SoC as shown in Fig. 12d. The cells in M with the highest average SoC are discharged at the beginning of the BESS charging operation, whereas the cells in M with the lowest average SoC are charged as shown in Fig. 12c and Fig. 12d, respectively. Accordingly, the priority list used in the proposed SoC balancing strategy is validated, where the cells/Ms with the highest priority (cells/Ms with high and low SoC during discharging and charging, respectively) are activated firstly during discharging/charging. The cells' traces in Fig. 12c and Fig. 12b are steeply sloped during 0 -15 min of the charging operation due to the use of I h (current-prioritised method) to discharge/charge the cells with the highest priority, which increases the speed of their discharging/charging compared to other cells. In Fig. 13 (case study 2), SoC balancing convergence among 2664 cells is achieved in 48 min as shown in Fig. 13a while SoC balancing convergence among 222 Ms is achieved in 38 min as shown in Fig. 13b. During 0 -58 min, most of the cells' traces are rising, which indicates that most of the cells/Ms are activated. In case study 1, around 164 Ms (1968 cells) are idle during charging as shown in Fig. 11a, whereas in case study 2, 61 Ms (732 cells) are idle during charging as shown in Fig. 11b. Accordingly, SoC balancing convergence among cells, Ms, and cells in M are achieved using the proposed SoC balancing strategy for both case studies [see Table 4] regardless of the existing number of idle cells/Ms as shown in Fig. 12 and Fig. 13. At any given time, the average SoC among cells/Ms is different when 3996 cells (333 Ms) are used compared to 2664 cells (222 Ms) (e.g., in Fig. 12, the average SoC among the cells/Ms is 73 % in 60 min, while it is 83.4 % as shown in Fig. 13. During each T S , the activated Ms are distributed into three groups (based on SoC balancing strategy proposed in Section III) by controlling their corresponding switches (sw az , sw bz , and sw cz ) as ON (1) or OFF (0) as explained in Subsection B, Section II. M 1 and its corresponding switches are selected to demonstrate the distribution principle of Ms as shown in Fig. 14. Hsw az , Hsw bz , and Hsw cz are used to generate a sinusoidal V out for a three-phase (-1 and 1 for the negative and the positive side, respectively, while 0 for OFF status). Each M can be activated in any group to generate any V out . Nevertheless, it can be activated only in a single group to generate a certain V out every T S as shown in Fig. 14 (e.g., at any given time, only one of sw a1 , sw b1 , and sw c1 is ON. However, M 1 is activated via sw a1 , sw b1 , and sw c1 at different time steps). Hsw a1 , Hsw b1 , and Hsw c1 statuses (ON or OFF) follow its corresponding switches (sw a1 , sw b1 , and sw c1 , respectively) statuses (e.g., only sw a1 and Hsw a1 are ON at 13 s whereas sw b1 , sw c1 , Hsw b1 , and Hsw c1 are OFF).

V. EXPERIMENTAL SET-UP
The experimental work is still going on. Consequently, a general overview of the experimental set-up with some initial results is provided in this paper. The experimental set-up includes twelve cells (Panasonic NCR18650) with a 3.6 V nominal voltage and a 3.35 Ah nominal capacity. Each cell is integrated into an L-bridge while the four L-bridges are integrated into three parallel H-bridges (phase a, phase b, and phase c). These L-bridges and H-bridges are located in a single printed circuit board (PCB) as shown in Fig. 17. Each module (a single PCB) is designed for four cells. Note that the final experimental system will include nine PCBs integrated with 36 cells. The converter control and cell SoC balancing algorithm are implemented in a C2000 LAUNCHXL-F28379D device. Switching signals are sent through a shift register (74HC595) / 8-bit serial-in, parallel-out as decimal numbers using the SPI interface. The   voltage of each individual cell is measured through a difference amplifier (INA117P) and an analog to digital converter (ADC/MCP3208) using the SPI interface. The general block diagram of the experimental set-up of TCHMMC is presented in Fig. 15. The experimental set-up of TCHMMC is presented in Fig. 16 while the detailed breakdown of a single module/PCB of TCHMMC with its relative switches is presented in Fig. 17. The results obtained from this experimental set-up are presented in Figs. 18-21. In Fig. 15, in order to implement converter control and SoC balancing algorithm, 12-bit ADCs are used to measure a three-phase current and cells' voltages during each time step. In addition, a shift register (serial-in, parallel-out) unit is used to overcome the limited number of digital signal pins. In Fig. 16, three modules are used to generate a three-phase voltage where each module is integrated into four cells.     Fig. 19 show a 9-level three-phase output voltage and current, respectively, generated by the 12-cell TCHMMC. In Fig. 20, cells in M are discharged using the fundamental concept of the priority list, thereby SoC balancing among cells in M is achieved at 700 s. Fig. 21 shows the number of cells used to generate each level of the multi-level output voltage. Since each level of multi-level output voltage requires different number of cells, the number of idle cells ranged from 0 to 4 cells which repeats every quarter of a duty cycle.

VI. CONCLUSION
A novel SoC balancing strategy for the proposed topology of a three-phase grid-scale BESS is introduced in this paper. Moreover, a novel cell/M activation algorithm is proposed to minimise the duration needed to activate the cells/Ms required to generate each level of V outa , V outb , and V outc , thereby leading to an improvement in the operational efficiency of the SoC balancing strategy. In the proposed topology, one branch instead of three branches (compared to the conventional topology) is used to generate V outa , V outb , and V outc by integrating each M with three H-bridges connected in parallel. Each cell is independently controlled by linking each one of them with an L-bridge. Accordingly, a threephase bidirectional direct AC-DC conversion is achieved. Furthermore, a three-phase AC rated active power (60 kW) is generated when 3996 cells (333 Ms) are used and reduced by two-thirds (2664 cells (222 Ms)). Accordingly, slightly more than one-third of the total cells/Ms is idle (compared to the conventional topology). Therefore, the total cost of the BESS, control complexity, size, and losses are reduced by eliminating these idle cells/Ms from the BESS plant or by using as redundant cells/Ms. The proposed SoC balancing is, therefore, designed to achieve SoC balancing among cells/Ms with/without these idle cells/Ms (case study 1 and case study 2). In the proposed topology, SoC balancing convergence among branches (phases) is not required compared to the conventional topology. The simulation results of the proposed SoC balancing strategy showed a satisfactory performance, where SoC balancing convergence among 3996 cells, 2664 cells, and 333/222 Ms is achieved in 53 min, 48 min, and 38 min, respectively. During the production of the desired V out (3.6 kV for a phase), a significant range of Ms from 164 to 188 and from 142 to 176 of 333 Ms (case study 1) are idle during charging and discharging, respectively, whereas the idle Ms ranged from 61 to 84 and from 28 to 56 of 222 Ms (case study 2) during charging and discharging, respectively. During charging, SoC balancing convergence among 12 cells in M with the lowest average SoC is achieved in 18 min compared to 53 min for 12 cells in M with the highest average SoC. The converter was experimentally validated using a TCHMMC which includes twelve Panasonic NCR18650 cells divided into three modules.
Further studies on improving the accuracy of SoC estimation, reducing control complexity, and adding a further parameter called State-of-Health (SoH) can be performed in the existing SoC balancing strategy.