The Generation Mechanism and Elimination Strategy of Narrow- and Error-Pulse for Cascaded H-Bridge NL-PWM Modulation

There is a wide application prospect of Nearest level pulse width modulation (NL-PWM) in cascaded H-bridge (CHB) converter, however, it will produce narrow- and error-pulse in the process of implementation, which has a negative impact on CHB efficiency, output voltage quality and safe operation of power devices. In this paper, the NL-PWM strategy is improved based on round function to solve the narrow pulse of traditional NL-PWM, and a step wave delay update strategy is proposed to solve the error-pulse of NL-PWM. This paper analyzes the basic principle of improved NL-PWM and its ability to avoid narrow pulse of power device, shows the harmonic characteristics of improved NL-PWM, analyzes the generation mechanism of error pulse, and calculates the error of output voltage caused by the proposed step wave delay update strategy. The correctness of theoretical analysis and the effectiveness of the proposed method are verified by simulation and experiment. The research shows that the improved NL-PWM can effectively prevent narrow pulse while maintaining good harmonic characteristics, and the proposed step wave delay update strategy can avoid error pulse and has little impact on the output of NL-PWM.


I. INTRODUCTION
Cascaded H-bridge (CHB) converter is a widely used multilevel topology, and it is a research hotspot in the field of high-voltage and high-power converters [1]. CHB has many advantages, such as simple structure, excellent harmonic characteristics, easy modularization, high reliability and easy realization of redundant design, etc. [2], [3]. CHB multilevel converter is widely used in motor drive [4], new energy power generation [5], [6], active filter [7], flexible power transmission [8], static var compensator [9], power electronic transformer [10]- [13] and other fields.
Modulation strategy is the key technology of multilevel converters. It plays an important role in the output waveform quality, system reliability, working efficiency and service life of the converter, and has a great effect on the output The associate editor coordinating the review of this manuscript and approving it for publication was Huiqing Wen . power balance of each sub-module (SM) of CHB. At present, the modulation strategies used in CHB are mainly divided into the following three categories. The first type is highfrequency PWM modulation, which includes carrier phase shift PWM (CPS-PWM) [14], [15], level-shifted PWM(LS-PWM) [16], [17] and space vector PWM(SVPWM) [18]. The second type is nearest level modulation (NLM) [19], which is based on fundamental frequency modulation. And the last one is NL-PWM, which is a combination of high frequency PWM modulation and fundamental frequency modulation [20]. CPS-PWM has been widely studied because of its high equivalent switching frequency, good waveform quality and balanced switching frequency distribution. Compared with CPS-PWM, LS-PWM has better harmonic characteristics and can reduce the switching times. However, it needs additional equalization control, which has high control complexity and cannot achieve equivalent switching frequency doubling. SVPWM has high voltage utilization and good waveform quality, but its voltage vector increases rapidly with the increase of the number of levels, and the modulation process is complicated. NLM adopts a step wave to approximate the sine reference voltage, which has the advantages of low switching frequency, simple voltage equalization control and small switching loss. It is widely used in highvoltage application, but when the number of levels is small, its dynamic response capability and the waveform quality are poor [21].
Reference [20] proposed the NL-PWM method for CHB, also known as hybrid pulse width modulation (HPWM), which combines the advantages of high frequency PWM and fundamental frequency modulation. In NL-PWM, only one SM in each bridge arm works in high-frequency PWM mode, and the other SMs output step waves. While retaining the advantages of NLM, it has the characteristics of less lowfrequency harmonic content of PWM and higher waveform quality. NL-PWM uses voltage sorting method to implement voltage balancing control. The voltages of SMs are sampled and sorted in each voltage balancing period, and the output level of the SMs is controlled according to the sorting results and the bridge arm current direction. The output voltage quality of NL-PWM is compared with CPS-PWM in [22], proving that the output voltage quality of NL-PWM is better than that of CPS-PWM. However, in traditional NL-PWM method, the amplitude of the PWM reference voltage is equal to the amplitude of the triangular carrier voltage, and the SM working in the PWM mode will generate the narrow pulse. This may cause the switch devices failing to turn on or turn off, increase switching loss of devices, and even cause the switching device to be overheated and burned under longterm operation [23], [24]. In practical application, elimination technology of narrow pulse is required to eliminate these impacts. In addition, error pulses with incorrect level will appear during the implementation of NL-PWM, which has a negative impact on the output voltage quality and converter efficiency. The generation mechanism and elimination methods of error pulses have not been studied yet.
In view of the above problems, this paper is organized as follows. Section II analyzes the generation mechanism of the narrow pulse in traditional NL-PWM, proposes an improved NL-PWM based on round function to avoid the generation of the narrow pulse of the power device, and analyzes harmonic characteristics of the improved NL-PWM. Section III analyzes the generation mechanism of NL-PWM error pulse and its influence on the output voltage, proposes a step wave delay update strategy to eliminate the error pulse, and the error of the NL-PWM output voltage caused by the step wave delay update strategy is also analyzed in this section. The theoretical research is verified through simulation in section IV. Section V builds a CHB prototype to verify the correctness of the theoretical analysis. Finally, section VI summarizes the research work of this paper and makes an outlook for the next work.

II. NL-PWM NARROW PULSE AND ELIMINATION STRATEGY A. NL-PWM NARROW PULSE GENERATION MECHANISM
The topology of CHB is shown in Fig. 1, which is composed of N full bridge SMs cascaded. In Fig. 1, L s represents the AC filter inductance, v s is grid voltage, i s is grid current, v smi and v ci are the output voltage and capacitor voltage of the ith-SM respectively. Under stable operation, the capacitor voltages of each SM are equal, that is, v c1 = v c2 = . . . = v c .
NL-PWM is a modulation strategy that combines NLM and PWM. For the bridge arm with N SMs, N − 1 SMs use NLM to output the step wave voltage v step , and the remaining one SM outputs the PWM voltage v PWM . The step wave voltage and the PWM voltage can be superimposed to get the 2N + 1 level output voltage v an which is close to the sine reference wave.
Taking v c as the reference voltage, the output voltage waveform of the bridge is shown in Fig. 2. In the figure, v ac is the sinusoidal reference voltage, and its expression is v ac = MNv c cos(ω r t + θ r ) = MNv c cos y (2) where, M is the modulation ratio; N is the number of SMs in the bridge arm; ω r , θ r are the frequency and initial phase of the sinusoidal reference voltage, respectively. Under the normalization condition, the PWM reference voltage is obtained by subtracting the sinusoidal reference voltage v ac and the step wave voltage v step . The step wave voltage and PWM reference voltage of the traditional NL-PWM method are shown in Fig. 3. At the jumping point of the step wave, the value of the PWM reference voltage is equal to the carrier amplitude, and PWM narrow pulse will appear due to full modulation. In practice, it is necessary to use elimination methods such as modulation wave limiting and switching device delay on-off to avoid the generation of narrow pulse. But these methods will inevitably distort the modulation wave and affect the waveform quality.

B. THE IMPROVED NL-PWM
If the phase of the step wave jumping point can be adjusted, the amplitude of the PWM reference voltage will be changed, thereby the narrow pulses can be avoided. For this reason, an improved NL-PWM modulation using round function to generate a step wave is proposed in this paper. The expression of the step wave voltage v step is where, round(·) represents round function.
Taking v c as the reference voltage, the PWM reference voltage of the improved NL-PWM can be expressed as The reference voltage of PWM is separated by step wave jump point, and its waveform is segmented sawtooth shape. As shown in Fig. 4, it can be expressed as the sum of N parts In Fig. 4, the step wave jumping point can be expressed as As shown in Fig. 4, the value of the PWM reference voltage at the step wave jumping point of the improved NL-PWM is only 0.5, regardless of the value of M . There is no narrow pulse due to the equal amplitude of the PWM reference voltage and the triangular carrier. The amplitude of v ref at the 0 and π radian in the fundamental frequency cycle is 1 − N (1 − M ). When the frequency of triangular carrier f c = 3000Hz and N = 5, only if M is greater than 0.994, the narrow pulse with the width less than 10µs will be generated. As the number of SMs increases, the value of M will continue to increase. If the converter modulation ratio is too high, it will affect the output of inductive reactive power, and this situation is relatively rare. Therefore, narrow pulse can be avoided without additional elimination technology using the improved NL-PWM.
According to the theory of double Fourier transform, the Fourier series expression of the improved NL-PWM output voltage can be obtained where, the expression of A mn is (8), as shown at the bottom of the next page. NL-PWM outputs PWM voltage and step wave voltage at the same time, which belongs to unbalanced modulation, so it is necessary to equalize the voltage of each SM. The improved NL-PWM uses voltage sorting method to realize the voltage balancing of SMs. The output voltage of SMs is determined by the value of v ac , i s and the voltage of the SMs. The specific voltage balancing method of the proposed improved NL-PWM is shown in Table 1.
The power loss of a modulation strategy is mainly caused by the switching of the power devices. In order to reduce the loss of the improved NL-PWM, the switching time of voltage balancing can be set at the step wave jump point. Voltage balancing switching of traditional NL-PWM is carried out in each PWM carrier period. Compared with traditional NL-PWM, the improved NL-PWM can effectively reduce the number of additional switches generated by voltage balancing switching while ensuring the voltage balancing effect, so the power loss of improved NL-PWM is smaller. In addition, NL-PWM method outputs PWM voltage and step wave voltage at the same time. Only one SM works in high-frequency PWM mode, and the other SMs work in fundamental frequency mode. Therefore, the power device switching frequency and power loss of improved NL-PWM is much smaller than that of conventional strategies such as CPS-PWM.

III. NL-PWM ERROR PULSE AND ELIMINATION STRATEGY
A. NL-PWM ERROR PULSE AND ITS GENERATION MECHANISM NL-PWM error pulse and its generation mechanism are shown in Fig. 5. In Fig. 5(b), v PWM is the PWM output voltage under unipolar frequency double modulation. v step is the step wave voltage; v an is the CHB output voltage after the step wave and the PWM wave are superimposed. Because each SM of NL-PWM may work in PWM mode, but the number of ePWM channels of DSP is limited, the controller architecture of FPGA + DSP is usually adopted in practical application. The step wave level and PWM level are calculated and generated by DSP, and the distribution between different SMs   is realized by FPGA. The step wave level and PWM level are calculated by DSP, and the distribution of the two between different SMs is implemented by FPGA. In the implementation process, the step wave usually updates its reference value through DSP in a control interrupt, and the corresponding SM outputs the step wave voltage through FPGA after the interruption. While PWM usually adopts asymmetric regular sampling [33], the modulation wave is updated in the control interrupt, but the PWM trigger pulse is loaded and generated at the peak and valley value of PWM triangular carrier. When step wave voltage jumps, the reference voltage of PWM wave will have a step change, but the step wave and PWM modulation wave cannot be updated synchronously due to the loading mechanism of PWM, which will lead to the generation of error pulse.
In the presence of error pulse, the NL-PWM output voltage can be equivalent to the superposition of the correct NL-PWM output voltage and the pulse voltage with the value of ±v c as shown in Fig. 6.

B. STEP WAVE DELAY UPDATE STRATEGY
According to the generation mechanism of error pulse, in order to solve the problem, it is necessary to make the loading time of the step wave level and PWM level as consistent as possible. Since the time required for each execution of DSP control interrupt is not fixed, it is difficult to adjust the end time of control interrupt. Therefore, the end time of control interrupt cannot be corresponding to the peak and valley time of PWM triangular carrier. In order to solve the problem of error pulse, this paper proposes a step wave delay update strategy. In the case that PWM adopts asymmetric regular sampling, the step wave is properly delayed within half of the carrier cycle, so that the step wave voltage and PWM voltage can be updated synchronously, and the problem of error pulse can be solved. The step wave delay update strategy sets the end time of the control interrupt earlier than the peak and valley time of the PWM triangular carrier to complete the update of the step wave reference value. At the same time, an interrupt is set at the peak and valley time of the PWM triangular carrier, and the step wave voltage will complete the loading and output at this interrupt to realize the synchronous loading of the step wave and the PWM wave. Due to hardware delay and other reasons, the time when the step wave voltage changes do not completely correspond to the peak and valley value of PWM carrier. If the delay is too long, the error pulse will still appear. Therefore, it is necessary to analyze the allowable range of the delay time.
The SM working in the PWM mode adopts unipolar frequency multiplication modulation, and the reference voltage amplitude of the improved NL-PWM is 0.5 at the step wave jump point, so the PWM output voltage is 0 within the range of 1/8 carrier period from the peak and valley values of the triangular carrier. Therefore, the delay time t d needs to satisfy the following condition where, f c is the frequency of the triangular carrier. When the above condition is satisfied, even if the change time of step wave voltage does not completely correspond to the peak and valley value of PWM carrier, there will not be error pulse in the output voltage of NL-PWM, as shown in Fig. 7.  The step wave can be regarded as the superposition of N − 1 components with amplitude ±v c . After using the step wave delay update strategy, the schematic diagram of the i-th voltage component is shown in Fig. 8. In the figure, y ik (k = 1, 2, 3, 4) is the phase of the k-th jumping point of the voltage component, and y i1 = −(π − y i ) + y ei1 y i2 = −y i + y ei2 y i3 = y i + y ei3 y i4 = π − y i + y ei4 (12) The expression of y i is shown in (6). y eik = t eik /0.02 * 2π is the phase delay of the k-th jumping point of the voltage component. t eik is the delay time of the jumping point, and the value of t eik meets the following requirement: The Fourier series expression of the step wave voltage v step1 after using the step wave delay update strategy is v step1 = ∞ n=1 (C n cos ny + D n sin ny) where (sin ny i1 + sin ny i2 − sin ny i3 − sin ny i4 ) (cos ny i1 + cos ny i2 − cos ny i3 − cos ny i4 ) Using the step wave delay update strategy, it can be obtained that the output voltage expression of NL-PWM is [A mn cos (mω c t + nω r t)] (15) where, the expression of A mn is shown in (8), and the expression of ϕ dn is It can be obtained from (10) and (15) that, when using the step wave delay update strategy to eliminate the error pulse voltage, the NL-PWM output voltage expression is v an = (NMv c + C 1 + A 01 + P 11 ) 2 + (D 1 + Q 1 ) 2 × cos (ω r t − ϕ 1 ) + ∞ n=2,4,6 (C n +P 2n ) 2 +(D n +Q n ) 2 cos(nω r t − ϕ n ) The delay of the step wave will cause errors between the amplitude and phase of the fundamental component of the actual output voltage and the theoretical value, which will have a negative impact on the output voltage. If the error is too large, it means that the method is not feasible. According to (17), for a CHB with 2-8 SMs, when the carrier frequency f c = 3000Hz and M = 0.9, the amplitude error δ and phase delay ϕ dn of the fundamental frequency component of output voltage after using step wave delay update strategy are shown in Fig. 9. It can be seen from the figure that the amplitude error δ of the fundamental frequency component of the NL-PWM output voltage caused by step wave delay update strategy is less than 0.9%, and the phase delay ϕ dn is less than 9 × 10 −3 π. The errors can be ignored in practical application. According to (7) and (8), the spectrum of improved NL-PWM is shown in Fig. 10(a), and the spectrum of traditional NL-PWM [22] is shown in Fig. 10(b). As can be seen from Fig. 10, the THDs (2 nd -255 th harmonics) of improved NL-PWM and traditional NL-PWM are 33.6% and 34.58% respectively, and the harmonic characteristics of improved NL-PWM are better than traditional NL-PWM with the same number of SMs.

IV. SIMULATION ANALYSIS
According to (10), the spectrum of NL-PWM with the presence of error pulse is shown in Fig. 11. We can see from Fig. 11 that the THD (2 nd -255 th harmonics) of the NL-PWM output voltage after superimposing the error pulse is 35.53%. Comparing Fig. 10(a) and Fig. 11, it can be seen that the error pulse will increase the harmonic content of the low frequency and reduce the NL-PWM output voltage. Therefore, it is necessary to adopt reasonable method to eliminate the adverse effects of error pulse.
According to (17), when using step wave delay update strategy to eliminate error pulse, the spectrum of NL-PWM is shown in Fig. 12. Comparing Fig. 11 and Fig. 12, we can see that the proposed step wave delay update strategy can reduce the NL-PWM output voltage THD (2 nd -255 th harmonics) to   34.53%, effectively eliminating the adverse effects caused by error pulse.

B. VERIFICATION OF THEORETICAL ANALYSIS
In order to verify the effectiveness of proposed NL-PWM methods, a CHB model is established in PSCAD/EMTDC and main parameters of the model are shown in Table 2. Fig. 13 and Fig. 14 show the output voltage simulation waveforms and their enlarged waveforms at the step wave jumping point of traditional NL-PWM and improved NL-PWM, respectively. From the two figures, it can be seen that the pulse width of the traditional NL-PWM is about 3µs at the jumping point, which has a narrow pulse problem.  Whereas, a pulse width of about 40µs occurs for the improved NL-PWM with narrow pulse disappearing. Also, the THDs (2 nd -255 th harmonics) of improved NL-PWM and traditional NL-PWM are 33.69% and 34.56% respectively. The harmonic characteristics of improved NL-PWM are better than that of traditional NL-PWM.
The improved NL-PWM output voltage waveform under asymmetric regular sampling is shown in Fig. 15. Comparing Fig. 5(a) and Fig. 15, we can see that the position of the NL-PWM error pulse is consistent with the theoretical analysis, which proves the correctness of the error pulse generation mechanism. Before and after the error pulse is eliminated, the spectrums of NL-PWM are shown in Fig. 16. It can be seen that the output voltage of NL-PWM has a higher low-frequency harmonic content in the presence of the error pulse, and the THD (2 nd -255 th harmonics) content is 36.21%. After using the step wave delay update strategy, the THD (2 nd -255 th harmonics) content of the output voltage is reduced to 34.48%. The step wave delay update strategy can effectively eliminate the adverse effects caused by the error pulse and improve the output voltage quality of NL-PWM.  In addition, comparing Fig. 11, Fig. 12 and Fig. 16, it can be seen that after error pulse is eliminated, the simulation results of the output voltage spectrum are consistent with the VOLUME 9, 2021  theoretical analysis results, which proves the correctness of the theoretical analysis.
In order to study the error of NL-PWM caused by step wave delay update strategy, a CHB with 2-8 SMs is built under the condition of modulation ratio M = 0.9. When the step wave jumping point is delayed to the peak and valley value of triangular carrier, the amplitude error and phase delay of the fundamental frequency component of NL-PWM relative to the sinusoidal modulation wave are shown in Fig. 17. Comparing Fig. 9 and Fig. 17, we can see that the theoretical analysis of the error of the step wave delay update strategy is correct. Fig. 18 shows the simulation result of the fundamental error of the output voltage due to asymmetric regu-  lar sampling before eliminating the error pulse. Comparing Fig. 17 and Fig. 18, it can be seen that before the error pulse is eliminated, the fundamental frequency component of the output voltage has an error within ±1% in terms of amplitude. The step wave delay update strategy does not significantly increase the amplitude of the fundamental component of the output voltage. In terms of the phase delay of the fundamental wave of the output voltage, the delay update of the step wave improves the phase delay, but the phase delay ϕ 1 is less than 9 × 10 −3 π after the error pulse is eliminated. The influence can be ignored in practical application.

V. EXPERIMENTAL VERIFICATION
In order to verify the feasibility of the proposed NL-PWM narrow-and error-pulse elimination method in the actual system, this paper built a three-phase CHB prototype as shown in Fig. 19 for experimental verification.  The main parameters of the prototype are shown in Table 3. The AC side of the CHB prototype is connected to the AC power grid, and the DC side is connected to a resistor to simulate a DC load. Fig. 20 and Fig. 21 show the phase voltage experimental results of the improved NL-PWM and the traditional NL-PWM, as well as the local amplified waveforms in the case of narrow pulse at the jumping point. The waveforms in the lower half of the figures are the amplification of the waveform in the red box in the upper half of each figures. In order to ensure the safety of the experiment, the narrow pulse less than 10µs will be delayed to 10µs. It can be seen from      Fig. 23 show the experimental results of the phase voltage before and after the error pulse is eliminated, respectively. Comparing Fig. 5(a) and Fig. 22, it can be seen that the position of NL-PWM error pulse is consistent with the theoretical analysis. Comparing Fig. 22 and Fig. 23, it can be seen that the error pulse shown in Fig. 22 does not exist at the corresponding position of the output voltage waveform shown in Fig. 23, and the error pulse elimination effect is obvious, which can explain the correctness of the NL-PWM error pulse theoretical analysis and the effectiveness of the delayed update strategy in eliminating error pulse. After the error pulse is eliminated, the CHB phase voltage THD (2 nd -255 th harmonics) is reduced from 35.56% to 33.79%, and the frequency spectrum is shown in Fig. 24. Comparing Fig. 11, Fig. 12, Fig. 16 and Fig. 24, it can be seen that the experimental results of the phase voltage spectrum are basically consistent with the simulation and theoretical analysis results, proving that the proposed step wave delay update strategy has good results in practical application. Also, the THD (2 nd -255 th harmonics) of traditional NL-PWM in Fig. 20 (error pulse is eliminated) is 34.22%, and the harmonic characteristics of improved NL-PWM are better than that of traditional NL-PWM.

VI. CNOCLUSION
Aiming at the problem of narrow-and error-pulse in the implementation of NL-PWM, this paper proposed an improved NL-PWM based on the round function and a step wave delay update strategy. Through theoretical analysis, simulation and experimental verification, the following conclusions can be drawn: (1) The improved NL-PWM based on the round function can avoid the narrow pulse of traditional NL-PWM while maintaining good harmonic characteristics.
(2) The step wave delay update strategy can effectively solve the problem of error pulse in NL-PWM, and it has a little negative impact on the output voltage of NL-PWM. This paper focuses on CHB converter. The next step is to study the implementation methods of NL-PWM in other converter topologies such as MMC to further improve the application scope and practical engineering application value of NL-PWM. Since 2006, he has been working with NCEPU. He is also a member of the State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources. His research interests include power quality and multilevel converter. VOLUME 9, 2021