Transient Process Optimization for Dual-Arm Cluster Tools With Wafer Revisiting

In wafer fabrication, it is imperative to minimize the transient process of cluster tools for the sake of on-demand and preventive maintenance. Due to the trend of multi-type and small-batch production, transient processes appear more and more frequently. Thus, the optimization problems of transient processes have gained increasing attention from both industry and academia. The requirement for wafer revisiting tend to complicate this problem significantly. However, only a few studies take such a challenge for cluster tools with wafer revisiting. This paper focuses on the schedule optimization of transient processes for dual-arm cluster tools with wafer revisiting. To accelerate transient processes, including both start-up and close-down ones, we adopt a program evaluation and review technique to analyze and harness a cluster tool’s state evolution. We then propose computationally efficient algorithms to speed up transient processes. Finally, we provide illustrative examples to show their applications and validate their effectiveness.


INDEX TERMS
PERT Program evaluation and review technique. Θ A state at which a PM or the robot is empty.

M
The system state.
The pth wafer that is released to the system with its qth operation being processed, p ∈ N n , q ∈ N 2k+1 , k ∈ N 5 1 . R b (W p (q)) The pth wafer is being held by the robot and will be delivered into process step b for its qth operation, b ∈ 3 , p ∈ N n , q ∈ N 2k+1 , k ∈ N 5 1 .
Time taken for the robot to unload a wafer from the PM or loadlock. β Time taken for the robot to load a wafer into the PM or loadlock. µ Time taken for the robot to move among two different modules. λ Time taken for the robot to execute swapping operation at a process step.

I. INTRODUCTION
To achieve higher quality, productivity, and yield, cluster tools with the single-wafer processing technology are widely applied in numerous semiconductor wafer fabrication processes, such as etching, chemical vapor deposition, and rapid processing technology with high temperature. In particular, cluster tools occupy an essential place in large-size wafer fabrication. A cluster tool compactly integrates several process modules (PMs), input/output loadlocks, and a waferhandling robot with a radial way and holds no intermediate buffer.
After being loaded into a cluster tool through loadlocks, raw wafers are delivered into PMs for processing in sequence according to pre-specified order, and finally return to loadlocks when all necessary processes are completed. All these operations are dominated by the wafer-handling robot. The robot is equipped with one or two arms fixed in an opposite direction, leading to the single-arm cluster tool (SACT) and dual-arm cluster tool (DACT, see Fig. 1). Considering their vast investment and production cost, it is of great importance to seek efficient and practical scheduling and control methodologies for cluster tools [1]. However, there is so far no generic solution due to coupling constraints.
For instance, in the wafer fabrication process of low-pressure chemical vapor deposition, the completed wafer must be unloaded from the PM within a restricted time in case of its degradation. This temporal restriction is called the wafer residency time constraint (WRTC). Kim et al. [2] propose a systematic modeling, analysis, and scheduling method for the DACT with WRTCs. Lee and Park [3] derive necessary and sufficient conditions to verify the schedulability of the time-constrained DACT by using the negative event graph. Based on the resource-oriented Petri nets (ROPNs) model, Wu et al. [4], Wu and Zhou [5] present efficient algorithms to find the optimal steady state periodic schedule for the SACT and DACT with WRTCs, respectively. When the residency time is tight, there may not be a feasible schedule under conventional robot strategies. To deal with such a particular issue, Lim et al. [6] develop a novel robot strategy based on the interference-free sequence. Yang et al. [7] provide a general framework to find the optimal schedule for the time-constrained SACT within both process-and transport-bound regions. In order to reduce quality variability in wafer fabrication and guarantee high-quality output, Zhu et al. [9], [52] and Xiong et al. [10] propose efficient methodologies to regulate robot waiting times for reducing the wafer delay time in each process step.
Due to exceptional events, such as processing delay, communication delay, or wafer alignment failure, the activity time is practically subject to random variation [2]. The activity time variation (ATV) may make the wafer residency time delay in PMs exceed reasonable bounds such that the schedule obtained under the assumption of deterministic activity time become infeasible. Thus, it requires that the schedule for cluster tools should possess sufficient adaptiveness and robustness [11]- [15]. Kim and Lee [16] develop a necessary and sufficient condition for identifying the always schedulable case and never schedulable case. A graph-based computational procedure is presented to find the satisfied schedule if the system state belongs to the always schedulable case. However, the criterion concerning the never schedulable case is somehow conservative. Wu and Zhou [17]- [19] design a real-time control strategy to dynamically regulate the robot waiting time to maximally compensate the impact of activity time variations on the wafer residency time fluctuation in PMs. By using this strategy, some never schedulable cases identified in [16] are schedulabe in fact. Besides, a real-time scheduling approach with two-level operational architecture is proposed, exhibiting its optimality in terms of productivity. Based on the idea of [17]- [19], Qiao et al. [20], [21] present efficient algorithms for scheduling the SACT with WRTCs and ATV. Nevertheless, the upper bound of wafer residency time delay provided in [20], [21] is overestimated, which may impede the schedulability test of some cases. Pan et al. [22] obtain the exact bound by several polynomial algorithms. With the unfixed conventional backward strategy, Yang et al. [23] provide an efficient method to calculate the upper bound of wafer residency time delay for the SACT with WRTCs and ATV. By the mixed-integer programming model, Lim et al. [24] present an adaptive scheduling approach to cluster tools with tight wafer residency time constraints and large processing time variations.
In the above discussion, we focus on the cluster tool with nonrevisiting processes, whereas there are still quite a few revisiting ones. For instance, the atomic layer deposition (ALD) is a typical wafer revisiting process (WRP) in semiconductor manufacturing [25]. Wafers in the ALD process require to visit some process steps multiple times such that the film thickness can be precisely controlled. Due to the wafer revisiting, PMs are shared by multiple operations, being prone to deadlocks, which further complicates the scheduling and control of cluster tools. Lee and Lee [26] investigate the scheduling problem of SACTs with WRP for the first time. They develop a mixed-integer programming model to find the deadlock-free optimal schedule. However, the presented method is computationally inefficient due to its exponential complexity. To cope with this issue, Wu et al. [27] adopt ROPNs to describe the ALD process. They propose a necessary and sufficient deadlock avoidance policy and analytical expression to calculate the optimal schedule. Further, Yang et al. [28] develop efficient algorithms to find the optimal scheduling of SACTs with WRP and WRCTs.
For the DACT with WRP, Wu et al. [29] find that the system presents a three wafer cyclic process including three local and global cycles if the conventional swap strategy is applied. Based on the ROPN model, they obtain conditions to find the optimal 3-wafer cyclic schedule (3-WCS). Due to the delay at the revisiting process step in each switching operation from local to global cycle, the system may always be in the transient state, i.e., the lower bound of the systematic cycle time cannot be reached. By reducing the number of local and global cycles, Wu et al. [30] propose a 2-WCS method. Qiao et al. [31] extend the results in [29], [30] and propose a method to calculate the cycle time of the DACT with multiple revisiting times. As verified in [29]- [31], it remains inefficient that scheduling the DACT with ordinary swap strategy, especially the revisiting time k > 2 cases. To overcome this limitation, Qiao et al. [32] present a modified swap-based strategy and derive a 1-WCS. Based on the results in [29], [30], [32], Qiao et al. [33]- [36] propose efficient methods to find the optimal 1-WCS of DACTs under WRCTs and ATV, respectively.
It should be noted that the majority of studies mentioned-above are devoted to the steady state scheduling. Nevertheless, as the wafer lot size contracts continuously, transient processes scheduling plays an increasingly important role due to new wafer fabrication requirements such as lot switching operations [37]- [39] and concurrent processing of multiple wafer types [40]- [44]. For the DACT, Kim et al. [45] prove that the latest/earliest starting policy can minimize its start-up/close-down transient process (SUTP and CDTP for short), respectively. Kim et al. [46] further present a maxplus algebra method to optimize the transient process of DACTs. Based on the ROPN model, Qiao et al. [47] and Zhu et al. [48] propose efficient algorithms to find the optimal schedule of SACTs with WRTCs during the SUTP and CDTP, respectively. Note that in [47], [48], each process step is configured with only one PM. Considering the SACT with parallel PMs, Kim et al. [49] develop a generalized backward strategy. Subsequently, Yang et al. [50] extend the results in [49] and present linear programs to search the optimal feasible schedule for the SACT with WRTCs and parallel PMs. For the SACT with a failure CDTP, Qiao et al. [51] propose efficient response policies. For the linear dual-arm multi-cluster tool subject to WRTCs, Zhu et al. [52] present efficient algorithms to find the optimal integrated schedule for the whole process covering the steady state and transient processes.
Although great efforts [45]- [52] concerning the transient process scheduling have been conducted, these studies are unfortunately focused on the nonrevisiting processes, i.e., inapplicable to the transient process with wafer revisiting. In our previous work [53], we propose efficient algorithms to optimize the SUTP of DACTs with WRP for two times. As for the optimization to more general cases, for instance, transient processes with wafer revisiting for multiple times, including both the SUTP and CDTP, there is no research reported on this problem yet. Thus, our major motivation is to tackle the transient optimization problem for DACTs with wafer revisiting. In this paper, we build an analysis framework based on the program evaluation and review technique to investigate the temporal properties of DACTs with WRP during transient processes. With the system network model, we present computationally efficient algorithms to find the optimized transient process schedule for DACTs under diverse wafer revisiting cases.
The subsequent sections are organized as follows. In Section II, we briefly introduce the ALD process and notations of corresponding activity representations and definitions. In Section III and IV, we analyze the SUTP and CDTP comprehensively and propose optimization algorithms to minimize transient processes, respectively. Section V provides case studies. Finally, Section VI concludes this paper.

A. ATOMIC LAYER DEPOSITION PROCESS
In semiconductor manufacturing, the raw wafer needs to undergo a number of process steps. In general, each process step demands a unique operation. If the wafer fabrication process necessitates the visit of the same process steps for more than one time, this is called revisiting process; otherwise, it is called nonrevisiting one. According to the manufacturing requirement, the revisiting process may contain only one process step or more than two process steps. In practice, the revisiting process with two process steps is widely applied in wafer fabrication. ALD is such a typical revisiting process that the film thickness can be controlled by repeating the deposition operation. Since the ALD with two revisiting steps is a typical wafer fabrication process that is commonly adopted in cluster tools, the results derived from the two-step revisiting process VOLUME 9, 2021 are useful for the other cases. Therefore, for the sake of simplicity, this paper only consider the ALD with two-step revisiting process. In the ALD process, as shown in Fig. 3, there are generally three steps (i.e., Al 2 O 3 deposition, Ta 2 O 5 deposition, and oxidation), and the last two of them are the revisiting process, which will be repeated several times, even more than five times [26]. Let m i and k be the number of parallel PMs for process step i and the number of revisiting times, respectively. Then, the ALD process can be denoted as (m 1 , (m 2 , m 3 ) k ), where (m 2 , m 3 ) k indicates the revisiting process. For the sake of the consistency of wafer fabrication within the ALD process, each step normally is composed of a single PM, i.e., m 1 = m 2 = m 3 = 1. Thus, the wafer flow pattern of the ALD process can be denoted as (PM 1 , (PM 2 , PM 3 ) k ) with (PM 2 , PM 3 ) k being a k-time wafer revisiting process (k-WRP).

B. DESCRIPTION OF SYSTEM STATE AND ACTIVITY
Cluster tools are a type of highly automated manufacturing systems containing complex discrete state evolution and temporal properties.
For the state description, we use W p (q), p ∈ N n , q ∈ N 2k+1 , k ∈ N 5 1 , to represent the pth wafer that is released to the system with its qth operation being processed, and R b (W p (q)) represents the pth wafer is being held by the robot and will be delivered into process step b for its qth operation, where b ∈ 3 , p ∈ N n , q ∈ N 2k+1 , and k ∈ N 5 1 . In particular, process step 0 denotes the loadlock. Then, a state of the system can be denoted as (1))} represents that the first, second, and third wafers (i.e., W 1 , W 2 , and W 3 ) are being processed in PM 3 , PM 2 , and PM 1 , respectively, whereas the fourth wafer is being held by the robot and will be delivered into PM 1 for its first operation at process step 1. There is no doubt that the first operation must be executed in PM 1 , i.e., the robot is at PM 1 , preparing for swapping. Therefore, the definition of the system state results in no confusion or misunderstanding. As for the temporal aspects of the system resources' activities, we use α, β, µ, and λ to denote the robot task time for unloading, loading, moving, and the swapping operation, respectively. Likewise, wafer processing time in PM i is indicated as a i , i ∈ N 3 .

C. CYCLIC SCHEDULING OF STEADY STATE
The SUTP starts from the idle state {Θ, Θ, Θ, R 0 (Θ)}, where Θ indicates that the PM or the robot arm is empty. The challenge lies in reaching the target state quickly as possible. The CDTP starts from the steady state under a given cyclic schedule. That is, the steady state schedule has a significant impact on both the SUTP and CDTP. Therefore, it is necessary to know the cyclic scheduling strategy under the steady state. For the DACT with 2-WRP, a 1-WCS method is proposed in [32]. As for k-WRP with k > 2, it remains unclear whether exist an unified 1-WCS. Instead, Qiao et al. [31] investigate this with the framework of 3-WCS.
According to the 1-WCS presented in [32] for DACTs with 2-WRP, in the steady state, the system starts from state (1))} and then evolves as 5 forms a cycle characterizing the wafer revisiting process, namely so-called the local cycle, whereas the remaining states form a global cycle containing the entire process steps. The evolution from M 1 to M 6 forms a one-wafer cyclic process, containing one local and one global cycle.
With the 3-WCS approach proposed in [31] for DACTs with k-WRP where k > 2, in the steady state, the system should start from state It is obvious that M 1 and M 3k+2 , and M 2 and M 3k+3 are equivalent, respectively. This means that the evolution from M 1 (M 2 ) to M 3k+2 (M 3k+3 ) forms a periodic work cycle. It should be noted that the state transit from M 3 to M 3k−1 involves the revisiting process, whereas the others do not, such as transit from M 1 to M 2 or from M 3k to M 3k+3 . Therefore, the state transformation from M 1 to M 3k+2 or from M 2 to M 3k+3 forms a periodic work cycle containing 3k − 3 local cycles and three global ones.

D. SCHEDULING STRATEGY OF TRANSIENT PROCESSES
Assume that the cluster tool operates with a cyclic schedule during the steady state. When the system reaches its full work cycle, we must ensure the state is compatible with the steady state schedule. That is, the SUTP scheduling shall adapt to the steady state. Similarly, the CDTP is subject to the steady state scheduling. As revealed in [1], [4], [5], [47], [48], [51], the virtual wafer method (VWM) has advantages in a variety of scheduling problems of cluster tools, such as steady state scheduling implementation, PM failure response, and transient processes scheduling. Within the VWM-based scheduling framework, each PM is assumed to be occupied by a virtual wafer when the cluster tool boots up, and the virtual wafer will be loaded into the tool system following the last actual wafer W n . In both the SUTP and CDTP, the system will be manipulated by the cyclic scheduling as it is executed in the steady state. In this way, cluster tools can be efficiently operated in accordance with the steady state during both the SUTP and CDTP.
The virtual wafer scheduling method provides a simple and efficient implementation framework for the transient process. However, some extra activities containing both the robot and PMs are performed due to the processing of virtual wafers. In other words, we can remove these redundant activities by manipulating the actual wafers only; that is, no virtual wafer is loaded into the system. There is no doubt that the transient process can be accelerated after eliminating unnecessary activities. To analyze temporal properties during the transient processes, we adopt a network technique, namely the program evaluation and review technique (PERT) that has been applied in the transient process scheduling for cluster tools [45]. In the PERT paradigm, the precedence relationships of the robot tasks and PMs activities can be expressed graphically as a network model. This means that we can find the optimized transient schedule by searching the critical path of the network. Consequently, in the subsequent parts of this paper, we will adopt the PERT-based approach to conduct the property and scheduling analysis for the DACT with WRP during transient processes, including both the SUTP and CDTP.

III. START-UP TRANSIENT PROCESS SCHEDULING
Within the scheduling framework of 1-WCS and 3-WCS proposed in [31], [32], the target steady state of DACTs with 2-WRP is {W 3 (1), W 1 (4), W 2 (3), R 1 (W 4 (1))}, while for the case of k-WRP with k > 2 it is {W 3 (1), W 2 (2), W 1 (3), R 1 (W 4 (1))}. For the scheduling and control of DACTs with WRP in the SUTP, the crucial problem is how to reach the first target steady state from the idle state in the shortest time. We will discuss how to achieve this goal in subsequent parts.

A. 2-WRP
For 2-WRP, the SUTP consists of two stages. One is the initial stage from the idle state to the first full work cycle state; the other is the regulation one from the first full work cycle state to the target steady state. In the initial stage, the system state evolves as (3), R 3 (Θ)}. As indicated by [53], due to the difference of wafer processing time between PM 2 and PM 3 , in the regulation stage, there are two evolution paths: We use ω i,j to indicate the robot waiting time before its unloading operation at process step i during the transit from M j−1 to M j . Then, to reach M 3 from M 0 , the robot performs the following activities: unloading raw W 1 from the loadlock → moving to PM 1 → loading W 1 (1) into PM 1 → moving to the loadlock → unloading raw W 2 from the loadlock → moving to PM 1 → waiting (ω 1,2 ) for W 1 (1) at PM 1 → swapping at PM 1 → moving to PM 2 → loading W 1 (2) into PM 2 → moving to the loadlock → unloading raw W 3 from the loadlock → moving to PM 1 → waiting (ω 1,3 ) for W 2 (1) at PM 1 → swapping at PM 1 → moving to PM 2 → waiting (ω 2,3 ) for W 1 (2) at PM 2 → swapping at PM 2 → moving to PM 3 → loading W 1 (3) into PM 3 .
We use U, L, M, and S to denote the robot activities of unloading, loading, moving, and swapping operation, respectively. Similarly, P i , i ∈ N 3 , indicates the wafer fabrication in PM i . Based on the above robot tasks and PM activity sequences, we can build the PERT model of the transient process scheduling as shown in Fig. 3. In this PERT model, Nodes 0, 1 L , 3 L , and 6 L respectively correspond to states  Let φ O denote the minimum time taken for the DACT with WRP to reach the first target steady state from the idle state. Correspondingly minimum taken time based on the VWM is denoted as φ V . With the PERT model, we can calculate φ O by searching the critical path in the network. We use T k to indicate the time taken from the idle state {Θ, Θ, Θ, R 0 (Θ)} (represented by Node 0) to the terminal state (Node k).
Observing the system PERT model, our eventual goal is to identify which secondary end Node (i.e., Nodes 9 1U and 9 2U ) will be reached at first. By searching the PERT model, we can recursively calculating T k from the initial Node 0 to the final node. From Node 0 to Node 1 L , there is only one operation sequence (represented by U → M → L). This takes at least α + µ + β time units. Then, we have T 1 L = T 0 + α + µ + β. However, to reach its succeeding node (i.e., Node 1 U ), there are two operation sequences. One executes wafer processing in PM 1 , taking a 1 time units; the other performs a series of robot tasks (represented by M → U → M), taking 2µ + α time units. Thus, we have T 1 U = max{T 1 L + a 1 , 2µ + α}. Similarly, we can successively calculate T 2 U , T 3 U , · · · , T 9 1U , and T 9 2U . Finally, we have φ O = T 12 = min{T 9 1U , T 9 2U } + λ. Therefore, we have the following algorithm.
According to the system state revolution process as well as corresponding operation sequences, we can build the PERT model (shown in Fig. 4) of the DACT with k-WRP from the idle state to the first target steady state. In this PERT model, Nodes 0, 1 L , 3 L , 6 L , and 6 U correspond to states M 0 , M 1 , M 2 , M 3 , and M 4 during the first stage, respectively. Since M 4 , the system starts to execute the revisiting process (i.e., the local work cycle) multiple times. Accordingly, in the local work cycles, states M 5 , M 6 , · · · , M 3k , and M 3k+1 correspond to Nodes 9 U , 11 U , · · · , (6k − 1) U , and (6k + 1) U . In the final stage containing two global work cycles, states M 3k+2 , M 3k+3 , and M 3k+4 correspond to Nodes 7 U , (6k + 4) U , and (6k + 7) U . For the DACT with k-WRP under k > 2, similar to Algorithm 1, we have the following algorithm.

A. 2-WRP
In the first stage, i.e., after the beginning of CDTP while before W n−3 is completed and loaded into the loadlock, the system state evolves as: During such a state transition, the robot performs the following activities: moving to PM 2 → waiting (ω 2,2 ) for W n−3 (4) at PM 2 → swapping at PM 2 → moving to PM 3 → waiting (ω 3,2 ) for W n−2 (3) at PM 3 → swapping at PM 3 → moving to PM 2 → waiting (ω 2,3 ) for W n−1 (2) at PM 2 → swapping at PM 2 → moving to PM 3 → waiting (ω 3,3 ) for W n−3 (5) at PM 3 → swapping at PM 3 → moving to the loadlock → loading completed W n−3 into the loadlock .
In the third stage, i.e., after M 7 while before W n−1 is loaded into the loadlock, the system state evolves as: During this process, the robot performs the following activities: moving to PM 2 → waiting (ω 2,8 ) for W n−1 (4) at PM 2 → unloading W n−1 from PM 2 → moving to PM 3 → waiting (ω 3,8 ) for W n (3) at PM 3 → swapping at PM 3 → moving to PM 2 → loading W n (4) into PM 2 → moving to PM 3 → waiting (ω 3,9 ) for W n−1 at PM 3 → unloading W n−1 from PM 3 → moving to the loadlock → loading completed W n−1 into the loadlock .
based on the VWM is denoted as Φ V . Therefore, we can calculate Φ O for the DACT with 2-WRP according to the following algorithm.

V. ILLUSTRATIVE EXAMPLES
In this section, several examples are provided to demonstrate the preceding section' results. In the following examples, the time unit is second, abbreviated as s.
In this case, the bottleneck of the revisiting process is the second process step. For 2-WRP, by combining the VWM-based 1-WCS in [32], it will take 446 s and 410 s to reach the first target steady state and complete the CDTP. However, it takes 402 s and 341 s to do so via Algorithms 1 and 3, respectively. For k-WRP with k > 2, with the VWM-based 3-WCS in [31], it will take 1106 s, 1424 s, and 1742 s to reach the first target steady state and 898 s, 1216 s, and 1534 s to complete the CDTP, when k is 3, 4, and 5, respectively. By using Algorithms 2 and 4, it takes 814 s, 963 s, 1122 s, and 688 s, 946 s, 1204 s, respectively. Algorithms presented in this paper obtain a great reduction in transient processes schedule.
to Algorithms 1 and 3, whereas it takes 614 s and 551 s respectively by using the VWM-based 1-WCS. For k-WRP when k are respectively 3, 4, and 5, it takes 1536 s, 1986 s, and 2436 s to reach the first target steady state by the VWMbased 3-WCS, whereas it merely needs 1098 s, 1280 s, and 1551 s respectively by Algorithm 2. As for the CDTP, according to Algorithm 4, it will take 961 s, 1318 s, and 1675 s, respectively, while it takes 1312 s, 1762 s, and 2212 s by the VWM-based 3-WCS, respectively. Algorithms proposed in this paper outperform appreciably beyond the VWM-based scheduling approach for the transient processes with WRP.
We also provide two cases (No. 3 and 4 in TABLE 1) with significant differences between the robot task time and processing times. Details of these cases provided in this section can refer to TABLE 1. Compared with the VWM-based scheduling approach in [31], [32], the PERT-based method achieves significant time reduction. Especially as the increase of k, the time taken for the SUTP decreases more significantly than the VWM-based schedule. As a whole, in terms of time, the PERT-based scheduling method for the transient process is superior to the VWM-based cyclic scheduling approach, even though the latter one is easier to implement.

VI. CONCLUSION
As the growing tendency of high-mix and low-volume production, the wafer lot size decreases steadily, leading to an increasing number of the transient process. In particular, wafer revisiting makes this scheduling problem more complicated. This paper is concerned about the transient process scheduling problems for DACTs with WRP. For the sake of the simplicity of cyclic scheduling in implementation, existing research tends to adopt a virtual wafer scheduling method to operate transient processes for DACTs with WRP, resulting in extensive redundant activities. To resolve such a problem, we adopt a PERT-based model to analyze transient processes of DACTs with WRP comprehensively. Moreover, we present computationally efficient algorithms to optimize transient processes. The numerical experimental results indicate that the proposed approach performs much better than the virtual wafer scheduling method. Future studies are expected to extend the proposed method to transient process scheduling for cluster tools with WRP and WRTCs. It is also meaningful to investigate parallel PMs and other complex cases caused by disruptive events reported in [17]- [21].