Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances

In this work, a capacitorless one-transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) metal–oxide–semiconductor field-effect transistor was designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was utilized within the device because of several advantages, including its low fabrication cost and the feasibility of its use in high-density three-dimensional (3D) memory arrays. An asymmetric dual-gate structure is proposed to perform the write “1” operation and achieve high retention characteristics. The proposed 1T-DRAM cell demonstrates a high sensing margin of <inline-formula> <tex-math notation="LaTeX">$8.73~\mu \text{A} / \mu \text{m}$ </tex-math></inline-formula> and a high retention time of 704.4 ms compared to previously reported 1T-DRAMs, even at a high temperature. In addition, the effect of grain boundaries on the memory performance of the proposed device was investigated, and the results validated the excellent reliability of its retention characteristics even in the presence of grain boundaries (>64 ms at <inline-formula> <tex-math notation="LaTeX">$T =358$ </tex-math></inline-formula> K).


I. INTRODUCTION
Capacitorless one-transistor dynamic random access memory (1T-DRAM) has attracted a great deal of attention as a substitute for conventional one-transistor one-capacitor (1T-1C) DRAM. Given the difficulty of capacitor fabrication, the researchers have proposed the 1T-DRAM, which eliminate the need for capacitor altogether as a substitute for the conventional DRAM. The 1T-DRAM does not use an external capacitor, and instead relies on the principle of floating body effect. 1T-DRAMs have the advantage of simple fabrication and excellent compatibility with logic devices [1]- [11]. However, the smaller dimensions of these devices tend to limit The associate editor coordinating the review of this manuscript and approving it for publication was Sneh Saurabh . their retention characteristics because of the stronger electric field between the body and the source/drain junctions. The stronger electric field increases the recombination/generation rate of excess holes and the down-scaled 1T-DRAMs have the short retention time [12]. Therefore, 3D memory arrays can be a solution to increase the retention time of 1T-DRAMs. 1T-DRAMs based on polycrystalline silicon (poly-Si) have attracted attention due to the feasibility of obtaining highdensity 3D memory arrays. Poly-Si-based transistors have previously been employed in 3D memory technology because of their significant advantages related to integrated fabrication technology [13]- [15].
In this work, a poly-Si metal-oxide-semiconductor fieldeffect transistor (MOSFET) based 1T-DRAM cell with an asymmetric dual-gate structure, to realize superior memory performance, was investigated through a technology computer-aided design (TCAD) simulation. The memory performance characteristics of the proposed 1T-DRAM cell, namely, its sensing margin and retention time, were obtained and analyzed based on parameters calibrated against the experimental data in [13] to ensure high accuracy. Moreover, the effect of grain boundaries (GBs) within the poly-Si layers on the reliability of the device was investigated. Fig. 1 shows a schematic view of the poly-Si-MOSFETbased 1T-DRAM cell with an asymmetric dual-gate structure to realize high memory performance. The main gate is used to perform both the conventional MOSFET operation and the program operation, while the control gate is employed to perform the program, erase, and hold operations. Furthermore, an underlap structure is proposed to reduce the electric field in the depletion region between the body and the source/drain region, resulting in an increase in the retention time. The work-functions of the main gate (WF MG ) and the control gate (WF CG ) are 4.85 and 5.3 eV, respectively. Poly-Si can be used as a material of the main gate. Additionally, Ni and Ir can be used as materials of the control gate [16], [17]. Due to the high work-function of the control gate, the energy band diagram near the control gate is raised, thus creating a sufficient potential well for hole storage in the body.

II. DEVICE STRUCTURE AND SIMULATION METHOD
The main gate length (L g1 ) is 70 nm, the control gate length (L g2 ) is 50 nm and the gate dielectric (HfO 2 ) thicknesses (T ox ) are 3 nm each. The doping concentrations of the source, body, and drain regions are 1 × 10 20 cm −3 (ntype), 1 × 10 18 cm −3 (p-type), and 1 × 10 20 cm −3 (n-type), respectively. The device parameters for the proposed devices are summarized in Table 1. The geometric parameters of the cell, including its underlap length (L underlap ) and body thickness (T body ), are regarded as the main design variables, given that they have a critical influence on the cell's memory characteristics. The device design and analysis were performed using the Sentaurus TCAD simulation tool. In the simulation, the Fermi-Dirac statistical model, the nonlocal band-to-band tunneling (BTBT) model, the Shockley-Read-Hall (SRH) recombination model, the Auger recombination model, the trap-assisted-tunneling (TAT) model, the doping- dependent and field-dependent mobility models, the bandgap narrowing model, and the quantum confinement effect were all considered to maximize the simulation accuracy [18]. Furthermore, the trap distribution in the GBs of the poly-Si was calibrated using the experimental data in [13], which is shown in Fig. 2(b). In Fig. 2(b), the GB had four trap states, depending on the energy level: acceptor-like shallow trap, acceptor-like deep trap, donor-like shallow trap, and donorlike deep trap. As shown in Fig. 2(a), the simulation results show a good agreement with the measured data using the calibrated parameters and the experimental data in [13].  Table 2. Program operation was performed using the BTBT mechanism. During the erase operation, the holes that accumulated at the control gate side of the body region drifted toward the drain region because of the absence of a potential barrier. As shown in the figure, the proposed 1T-DRAM cell obtained a high sensing margin  [13]. (b) GB trap distribution calibrated using the experimental data in [13]. of 8.73 µA/µm at T = 358 K. In the proposed device, the electrical characteristics of the body region critically affect the memory performance. Therefore, various geometric and electrical parameters, including L underlap , T body , and the hold bias of the control gate (V GS2_H ), were modulated to optimize the device performance. Fig. 4(a) shows the program operation carried via the BTBT mechanism in the vertical direction between the main gate and the control gate. The tunneling-based program operation is used considering that the tunneling mechanism requires less power consumption compared to that used by the impact ionization mechanism. Furthermore, during the program operation, static-power dissipation can be avoided because there is no bias at the drain region. As shown in Fig. 4(b), by applying a positive bias of 2.0 V at the main gate and a negative bias of −1.7 V at the control gate, BTBT occurs and holes tunnel from the main gate side to the control  gate side in the same direction as the electric field, which enhances the tunneling rate. The excess holes accumulate at the control gate side of the body region due to the potential well, which facilitates hole storage, formed by the high workfunction of the control gate.  BTBT tunneling occurs in the body region, a large number of excess holes gather in the body region. When excess holes exist in the body region, the 1T-DRAM is in the ''1'' state. During the erase operation, the stored holes are removed by the negative bias on the drain region. The state of the 1T-DRAM cell without excess holes is defined as the ''0'' state. As shown in Fig. 5(a), there is a significant difference in hole density between states ''1'' and ''0'', particularly in the area close to the control gate. As shown in Fig. 5(b), this difference entails a different energy band diagram for states ''1'' and ''0'' during the hold operation; a larger hole density can be seen in state ''1''. It also seems that positive voltage is applied by the excess holes in the body region and this has the same effect as energy barrier lowering. Fig. 6(a) shows the contour maps of the electron current density in the proposed 1T-DRAM cell during the read ''1'' and read ''0'' operations, respectively. Fig. 6(a) shows that the current density of read ''1'' is larger than that of read ''0''. The read operations are conducted via conventional MOSFET operation by setting V GS1 to 1.0 V and V DS to 0.5 V. As shown in Fig. 6(b), the existence of excess holes in the storage region affects the electric potential of the body region. Excess holes appear as if positive voltage is applied by the holes in the body region during the read ''1'' operation, and this has the same effect as lowering V th , resulting in a higher read current. This difference in hole density corresponds to the difference between the read ''1'' current and the read ''0'' current, and is the value of the sensing margin of the 1T-DRAM

A. EFFECT OF L underlap VARIATIONS
The 1T-DRAM attempts to return to an equilibrium state during the hold time after program or erase operations. It is very important to analyze the time required for the device to return to the steady state because this is closely related to the retention time which is an indicator of memory performance. In order to accurately analyze the factors affecting retention time, it is important to know which factors have a significant impact on recombination/generation rates in the hold ''1'' and hold ''0'' states. Looking first at the hold ''1'' state which occurs after the program operation, the excess holes are gradually released through the body-to-source and body-to-drain junctions during the hold time. The rate of evacuation holes from the body is represented by the SRH recombination rate of the proposed poly-Si MOSFET-based 1T-DRAM cell with different L underlap during the hold ''1'' operation. In Fig. 7(a), the recombination rate reduces as the L underlap increases. The recombination rate is related to the electric field. Fig. 7(b) shows the electric field of the proposed device with different L underlap along the lateral direction. As shown in the figure, the electric field at the depletion region decreases as L underlap increases because of the wider depletion region under the underlap structure. Therefore, the weakening of the electric field surrounding the storage region leads to a decrease in hole recombination [19]. When the cell is in the hold ''0'' state, its return to equilibrium depends on hole charging mainly via BTBT generation. In this state, the most critical factor for generation is BTBT tunneling. BTBT tunneling affects the return of the device to equilibrium because it generates excess carriers in the body region during the hold ''0'' state. As shown in Fig. 7(c), the BTBT generation rate decreases with increasing L underlap because of the widening depletion region under the underlap structure as shown in Fig. 7(c). Consequently, the increase of L underlap plays a role in reducing both SRH recombination in the hold ''1'' state and BTBT generation in the hold ''0'' state, which help to improve the retention time of the proposed 1T-DRAM. Fig. 8 shows the sensing margin and retention time of the proposed device as a function of L underlap . As L underlap increases, the influence of the control gate with high workfunction decreases. This causes the depletion area of the channel to be reduced, and this results in an improvement in the transfer characteristics related to the sensing margin. Consequently, the sensing margin is enhanced by increasing L underlap . However, the retention time increases up to L underlap of 10 nm but then subsequently decreases. Retention time is affected not only by the generation/recombination rate but also by the number of holes. As L underlap increases, the physical size of the quantum well that can store holes in the body region decreases. Additionally, the generation/recombination rate decreases as L underlap increases. Below an L underlap of 10 nm, the generation/recombination rate decreases and hole density decreases, but retention time increases because the number of holes is sufficient. When L underlap is more than 10 nm, the generation/recombination rate also decreases, however, hole density in the body region is not sufficient to cope with the decreasing number of holes by generation/recombination. As a result, when L underlap is greater than 10 nm, the retention time decreases. As shown in the figure, the proposed 1T-DRAM cell had the highest performance when L underlap = 10 nm, with a high retention time of 424 ms. Fig. 9(a) shows a contour map of the recombination rate of the proposed 1T-DRAM cell with varying T body . As indicated in the figure, the recombination rate decreases when T body increases. As shown in Fig. 9(b), a body thickness of 10 nm has a sufficiently high sensing margin, but its retention time   is not sufficient to satisfy the International Roadmap for Devices and Systems (IRDS) (<64ms) [20]. The retention time degrades because of the decrease in the number of excess holes in the storage region. The BTBT rates during program operation are also reduced because of the decrease in the vertical electric field. In addition, it has a high retention time at a body thickness of 15 nm, but a poor sensing margin that is less than 3 µA/um [21]. Consequently, the proposed 1T-DRAM cell has the highest retention time of 424 ms when T body = 12 nm. Fig. 10(a) shows the variation in the energy band diagram of the proposed 1T-DRAM cell with different V GS2_H . When a bias is applied at the control gate, the potential energy of the body region increases, forming a larger storage region. Fig. 10(b) shows the retention time of the proposed device with different V GS2_H as a function of hold time. The retention time is enhanced because of the larger storage layer with lower V GS2_H . However, when V GS2_H is less than −0.2 V, the retention time decreases because of the hole  generation caused by tunneling through the thin barriers at the source/drain junctions. Therefore, it can be concluded that the proposed 1T-DRAM cell has superior performance with a high sensing margin of 8.73 µA/µm and a high retention time of 704.4 ms when V GS2_H = − 0.2 V. It obtains a long retention time of 704.4 ms at 358 K, and this is almost 11 times longer than that required of DRAM cells by the IRDS [20].

D. EFFECT OF GBs IN 1T-DRAM
In poly-Si thin-film-based devices, randomly generated grain boundaries (GBs) exist in the poly-Si region [22]- [24]. Considering that traps in the GBs adversely affect device performance, the effect of GBs on the proposed device should be analyzed to ensure its reliability. To definitively determine the effects of the GBs, the proposed 1T-DRAM cell was simulated including a single GB. In the simulation, L g1 was set to 70 nm. Therefore, a single GB was assumed to be located at the center of the body region, given that the grain size of poly-Si is several hundred nanometers [22]- [24]. The trap distribution of the GB, which was applied within the simulation, was calibrated using experimental data [13] as shown in Fig. 2(b). Fig. 11 illustrates the read currents of the proposed 1T-DRAM cells as a function of a hold time both with and without the GB. As indicated, the read ''1'' and read ''0'' currents are degraded with the GB present. The sensing margin decreased accordingly from 8.73 to 6.58 µA/µm.
As shown in Fig. 12(a), the energy barrier formed by electrons that are captured in the GB trap prevents current flow from the source to the drain. In addition, the hole recombination and generation rates increase as a result of the TAT mechanism through the GB traps, as shown in Fig. 12(b). However, the proposed device still exhibited a high retention time of 340.1 ms at T = 358 K even with the GB, proving its high reliability.
When GBs exist in the poly-Si body region, the location and the number of GBs is uncertain because of the random generation of grains. Therefore, the effect of the GB location on the proposed 1T-DRAM cells was determined as a function of hold time. When the GB is located at positions b, c, and d ( Fig. 13(a), inset), there is little effect on the memory performance. However, when the GB is located at positions a or e, the read ''1'' and read ''0'' currents are increased. Since the GB-induced energy barrier is located in the depletion region, the effect on the electron flow decreases. In particular, when the GB is located at e, the read currents become larger because the energy barrier decreases due to drain bias, similar to the drain induced barrier lowering phenomenon [25]. Therefore, the sensing margin has the highest value of 7.46 µA/µm when the GB is at e. However, the retention time such a device is at the lowest value of 207.94 ms, although this is still demonstration of excellent retention characteristics (>64 ms when T = 358 K). Fig. 13(b) shows the sensing margin of the proposed 1T-DRAM cells with different GB number as a function of hold time. The GB number is limited to 4 because the body region is not large enough to have accommodate a larger number of GBs. The sensing margin decreased from 6.58 to 3.38 µA/µm when the number of GBs increased from 1 to 4. This is because the increasing GB-induced energy barrier disturbs the current flow and thus decreases the read currents and the sensing margin. The retention time also decreases when the number of GBs in the proposed 1T-DRAM cell increases. This increases because of the enlarged region in which TAT occurs. However, in cases like that, the number of GBs is 4, which means that the grain size is approximately 14 nm, and the high retention time of 82.45 ms is obtained when T = 358 K, indicating high retention performance (>64 ms when T = 358 K). Moreover, considering grain size, the proposed 1T-DRAM cell exhibits superior reliability in terms of memory characteristics even at a high temperature. Additionally, as can be clearly seen in Table 3, the 1T-DRAM proposed in this study exhibits excellent memory performance when compared to other devices reported previously.

IV. CONCLUSION
In this work, a novel 1T-DRAM based on a poly-Si MOS-FET with an asymmetric dual-gate structure was designed and investigated with TCAD simulations. Various geometric and electrical parameters were varied to optimize the memory performance. The simulated 1T-DRAM cell achieved a high sensing margin of 8.73 µA/µm and a high retention time of 704.4 ms with the optimized parameters of L underlap = 10 nm, L g1 = 70 nm, L g2 = 50 nm, T body = 12 nm, T ox = 3 nm, and V GS2_H = − 0.2 V. Furthermore, the proposed 1T-DRAM cell demonstrated excellent reliability in terms of its retention characteristics (>64 ms when T = 358 K) with various GB locations and numbers. Therefore, our proposed 1T-DRAM has significant potential to replace the conventional 1T-1C DRAM via implementation of a highdensity 3D memory array.

ACKNOWLEDGMENT
The EDA tool was supported by the IC Design Education Center (IDEC), South Korea.