An 0.4–2.8 GHz CMOS Power Amplifier With On-Chip Broadband-Pre-Distorter (BPD) Achieving 36.1–38.6% PAE and 21 dBm Maximum Linear Output Power

A broadband 180 nm CMOS power amplifier (PA) operating from a frequency bandwidth of 400 MHz to 2.8 GHz is presented in this paper. The PA is integrated with an inductor-less Broadband-Pre-Distorter (BPD) to enhance its linearity for wide bandwidth. The BPD consists only of MOS transistors, resistors, and capacitors which contribute to the wideband operation thus independent of the Q factor of passive inductors which contributes to the effectiveness of many other APDs available. The integrated BPD improves the Amplitude Modulation-to-Amplitude Modulation (AM-AM) and Amplitude Modulation-to-Phase Modulation (AM-PM) deviation of the PA across maximum linear output power of 21 dBm. Utilizing a silicon area of 1.69 mm2, mounted on Roger’s RO4000/FR4 PCB, the BPD-PA produces a maximum output power of more than 22 dBm for 2.4 GHz bandwidth with a minimum power gain of 15 dB. The corresponding peak power added efficiency (PAE) of more than 35% is achieved across the operating bandwidth. The fabricated BPD-PA meets the Adjacent Channel Leakage Ratio (ACLR) specification of −30 dBc at a maximum linear output power of 21 dBm (3 dB back-off from maximum output power) when tested with 20 MHz LTE signal at 1.7 GHz.

The significant contributors to the non-linearity effect in CMOS PAs are the intrinsic non-linear trans-conductance and the non-linear gate-source capacitance, C gs . Various linearity and efficiency enhancement techniques have been extensively proposed to overcome the aforementioned drawbacks in CMOS PAs. In [6], an adaptively controlled biasing technique is utilized in a common-source PA to reduce its gain and phase distortion by controlling its gate bias voltage when the RF signal is more than a certain threshold. A hybrid class-G Doherty is proposed in [7] where it uses a mixed-signal linearization technique to optimize its amplitude and phase modulation through digital PA operation and analog phase compensation. In [8], it is proposed that the phase modulation distortion of a 2-stage PA operating in millimeter-wave (mmW) has been optimized by utilizing a compensation transformer integrated at its input. An external harmonic injection technique is also proposed as a technique to enhance linearity and efficiency as in [9]. A secondharmonic injection at the PA's output enables the voltage and current wave-shaping that optimizes the overall performance of the PA.
Besides that, linearization techniques such as Analogue Pre-Distortion (APD) and Digital Pre-Distortion (DPD) techniques are also customarily utilized [10]. Pre-distortion is an execution of cancelling out the non-linearity of PA by generating a distorted characteristic that is opposite in terms of amplitude and phase profiles as compared to that of PA. If the pre-distorter generates an intermodulation product that is equal in magnitude and out-of-phase to that of the PA, then an ideal cancellation of IMD products is achieved. These opposite characteristics between the stages cancel out the 3 rd -order intermodulation (IMD3) product produced [11]. Yet, the DPDs are highly complex in its integration [12] and consumes large chip area while APDs use variable phase and gain shifters which only works for narrowband [13], [14].
Multitudinous efforts have been put into achieving broadband operation with CMOS PA previously. In [15], a 130 nm CMOS common drain PA with an integrated transformer produces a broad bandwidth operation by cascading two amplifier stages. An interstage broadband matching network is constructed to compensate for the first and second stage's frequency response to achieve a flat in-band gain. Moreover, a 180 nm stacked Class-J PA has been proposed in [16], where an optimum 2 nd -order harmonic load impedance is matched at different frequencies to obtain high efficiency in broadband. Unlike [12] which emphasizes the 2nd-order harmonic termination only, [17] presents a 180 nm SOI CMOS wideband PA with adjacent channel leakage ratio (ACLR) improvement through the utilization of 2 nd and 3 rd -order harmonic traps. The harmonic traps act as a short circuit at 2 nd -harmonic and an open circuit at 3 rd -harmonic.
Furthermore, [18] demonstrates a 45 nm CMOS PA with the combination of voltage-mode Doherty and Class-G switched capacitor technique. The switched capacitor PA is based on the fragmentation of a voltage mode Class-D PA in which the capacitor and a totem-pole driver are divided into small unit cells. When a segment of unit cells is turned on, the output voltage is controlled proportionally to the number of active unit cells which improves the efficiency for wide bandwidth. Besides, [19] also presents a switched capacitor technique that has been utilized to tune the frequency of the PA. Fabricated in 65 nm CMOS, the switched capacitor PA is constructed in series with a fixed inductor and a digitally programmable capacitor that enables frequency tuning.
Also, a dual-mode CMOS 180 nm PA with dynamic load modulation is presented in [20] to reduce the effect of the peak-to-average power ratio (PAPR) on the PA's load impedance. The dynamic load modulation is realized with a π-type matching network to optimize the PA's efficiency for wide bandwidth. Besides this, a power-control loop is utilized to reconfigure the PA's operation mode by sensing the input signal PAPR in real-time. This is followed, in [21], a transformer-based two stages dual-radial power splitting/combining technique is proposed which is equipped with an in-phase RF power splitting/combining competency. Instead of the conventional current combining method, [22] uses a series combining transformer (SCT) to combine the output power and achieve the load modulation in a voltage combining Doherty PA. The challenge lies in preserving the linearity and efficiency of the PA across a broad bandwidth. In some literature, even though the frequency response is providing broad bandwidth, the linearity and efficiency performances are only reported for single frequency such as in [16], [20], and [21]. The linearity and efficiency performances of the PA degrade drastically when the operating frequency is shifted from the center frequency.
This paper proposes a Broadband-Pre-Distorter (BPD) linearization mechanism that extends the linear operating bandwidth of a CMOS PA with a minimum trade-off with its Power-Added-Efficiency (PAE). Unlike APD which utilizes inductors (thus narrowband), the proposed BPD technique comprises MOS transistors, resistors, and capacitors to be area-efficient while reducing the IMD3 distortion generated by the main PA. This paper is organized as follows. Section II describes the principle of operation of the BPD-PA. Section III discusses the measurement performance of the PA and finally, Section IV concludes.

II. BROADBAND-PRE-DISTORTER-POWER AMPLIFIER (BPD-PA) A. CIRCUIT DESIGN
The schematic of the proposed broadband CMOS BPD-PA is depicted in Fig. 1. The operating bandwidth of the BPD-PA ranges from 400 MHz to 2.8 GHz while providing the desired gain and output power. The designed BPD-PA consists of an input matching network (IMN), BPD, main PA, output matching network (OMN), and biasing circuits integrated onchip. The main PA is operated in class AB mode and the gate voltage is supplied by utilizing a current source configured biasing circuit comprised of R 6 , M 5 , and R 7 . On the other hand, the biasing circuit for BPD consists of R 2 , M 1 , and R 3 . M 1 and M 5 are diode-connected transistors that minimize the effect of C gd thus greatly reduces the impact of bias modulation on the PA. The simplicity of the biasing circuits also saves the chip area.
The IMN is configured with R 1 (100 ), L 1 (4.83 nH), C 1 (1 pF), and C 2 (0.3 pF). C 1 also serves as a DC block capacitor. Referring to Fig. 1, Y represents the impedance before IMN whereas X is the impedance once IMN is added. With the aid of R 1 , a wideband S 11 is achieved as illustrated in Fig. 2. Other than that, the OMN consists of L 3 (1.98 nH), C 7 (1.5 pF), and C 8 (10 pF), where C 8 is the DC block capacitor to prevent DC current flow from supply V DD . L 2 (11.64 nH) is the RF choke for the main PA and capacitor C 6 (0.5 pF) is used to reduce the harmonic frequency. As a result, the PAE increases by 6%. Also, C 5 (20 pF) serves as the capacitive coupling between the BPD and main PA. The drain supply, V DD for the BPD and main PA are 3.3 V. The drain supply of the biasing circuits is given as V B1 = 1.2 V and V B2 = 1.5 V respectively. The BPD is built upon M 2 (280 µm/0.3 µm), M 3 (10 µm/0.34 µm), M 4 (750 µm/0.18 µm), C 3 (55 fF), R 4 (15 ), and a parallel RC feedback R 5 (15 ) and C 4 (55 fF). M 2 is a thick oxide PMOS transistor, while M 3 is a thick oxide NMOS transistor. M 2 and M 3 act as a capacitive load, thus producing a capacitive impedance at the output of the BPD. Thick oxide transistors have higher breakdown voltage levels, thus utilized to sustain the drain voltage supply of 3.3 V to achieve higher linear output power. The capacitive output impedance produces an opposite phase response to the inductive output impedance of the main PA which is dominated by L 2 . Parallel RC feedback (R 5 and C 4 ) extends the capacitive response over a large bandwidth, thus producing a broadband phase cancellation, resulting in broadband linearity and flat gain responses.

B. PRINCIPLE OF OPERATION
Since the 3 rd -order intermodulation product (IMD3) is the main contributor for side lobe spectral regrowth in a PA, predistortion is one of the techniques customarily utilized to minimize it. Commonly, this is realized through the instigation of a distortion characteristic that is opposite to the PA's distortion. If the pre-distorter generates an IMD3 that is equal in magnitude but out-of-phase to that of the main PA, then an ideal IMD3 cancellation is achieved. Fig. 3 depicts the concept of pre-distortion in a block diagram [23].
where V out is the output voltage of the main PA, V pd is the output voltage of the pre-distorter, V in is the input voltage of the RF signal, and a n and b n are the gain terms of the pre-distorter and main PA respectively. By exploiting this concept, the proposed BPD is capable of achieving the IMD3 cancellation across a wide frequency range. Inherently, the BPD generates a 3 rd -order component which is equal in magnitude but 180 • out-of-phase in contrast to the main PA's 3 rd -order component. Referring to Fig. 1 and substituting a n and b n from (2) and (3) with parameters from the circuit, the following power series expansion elucidates the interrelation of the BPD's and main PA's IMD3 products: where V main is the output voltage of the main PA, V bpd is the output voltage of the BPD, V in is the input voltage, Z main,n is the n th -order output impedance of the main PA, Z bpd,n is the n th -order output impedance of the BPD, g m4,n is the n th -order transconductance of M 4 and g m6,n is the n th -order transconductance of M 6 . Considering only the fundamental and 3 rd -order components, and substituting (5) into (4), we'll obtain: in )] 3 (6) Solving (6) and nullifying the 3 rd -order interaction components: normalizing (8) in the subject of the linear fundamental gain, g m6,1 Z main,1 /(g m4,1 Z bpd,1 ) 3 , yields: which is equivalent to: From (10), it can be concluded that to achieve IMD3 cancellation, the 3 rd -order component of the BPD needs to achieve an opposite response in contrast to the 3 rd -order component of the main PA. This can be viewed in terms of opposite amplitude-modulation to amplitude-modulation (AM-AM) and amplitude-modulation to phase-modulation (AM-PM) responses referring to the fundamental component [24]. Therefore, the fundamental gain component for the BPD and main PA required to be 180 • out-of-phase response too, as given in (11): Both Z bpd,3 and Z main,3 in (9) are in the form of complex numbers, in where the real part of Z bpd,3 is acquired through the resistances from the feedback (R 4 and R o3 ) while, the imaginary part is contributed by C 3 , C 4 , and C 5 . On the other hand, the real part for Z main,3 is determined by M 6 's output resistance (R o6 ), and the imaginary part is contributed by L 2 . Fig. 4(a) and Fig. 4(b) depict the small signal equivalent circuits of the BPD and the main PA, respectively. The gate-source capacitance of M 6 , (C gs6 ) is evaluated as a load of BPD. Based on the small-signal equivalent circuits, the BPD's and main PA's gain are derived. From the derivation, it is descried that the BPD's voltage gain, Av bpd expresses a capacitive response as in (12) as shown at the bottom of this page, while the main PA's voltage gain, Av main expresses an inductive response as in (18). A positive phase response is observed in (12) due to the dominance of g m4 and at the same time, a negative phase response is observed in (18) due to dominance of the g m6 . Av bpd is expressed as in (12), where; The g m2 , g m3 , and g m4 are the transconductance, R o2 , R o3 , and R o4 are the output resistance, and C gs2 , C gs3 , and C gs4 are the gate-source capacitance of transistors M 2 , M 3 , and M 4 respectively. C gs6 is the gate-source capacitance of transistor M 6 . Meanwhile Av main is: where g m6 is the transconductance and R o6 is the output resistance of transistor M 6 .
48834 VOLUME 9, 2021 The relationship between Av and S21 is given as follows: where Z o is 50 in our work, Z in is the input impedance of the each stages. Utilizing (19), the frequency response in terms of S 21 is given in Fig. 5 for the BPD, main and the complete wideband linearized PA.
The wideband operation of the BPD-PA is established by utilizing the gain compensation technique between the BPD and main PA stages. As shown in Fig. 5, the BPD produces a rising gain across frequency, while the main PA produces a descending gain across frequency. The capacitive response of the BPD generates high gain at a higher frequency band. In contrast, the inductive response of the main PA generates high gain at a lower frequency band. The gain compensation of both stages generates a wide frequency bandwidth from 0.4 to 2.8 GHz.
The main PA's gain magnitude and phase are dominated by L 2 thus, exhibiting an inductive response as expressed in (18). On the other hand, the BPD is constructed to be capacitive, which is dominated by C 3 , C 4 , and C 5 as expressed from (12) to (17). Therefore, the countervailing of the main PA's inductive effect by the BPD's capacitive output leads to a wideband distortion cancellation from 0.4 GHz to 2.8 GHz. The simulated locations of Z bpd , Z main , and Z L are delineated in Fig. 6. As aforementioned, it can be observed that the main PA's impedance is inductive, while the BPD's impedance is capacitive. The load impedance after integration of the BPD-PA and matching networks is shifted closer to 50 in where it provides an optimum flat broadband gain (S 21 ) across the operating frequency. The OMN is also designed  to achieve an optimum output power across frequency points and thus, a load-pull simulation has been performed as shown in Fig. 7. The contour is plotted with a 1 dB step up to maximum output power of 28 dBm. Here, it can be observed that Z L of Fig. 6 is located at the range of 24 to 27 dBm.
Furthermore, referring to (20) as shown at the bottom of this page, the cancellation after linearization observed that the C gs4 from M 4 (referring to Z o ) is the only capacitance effect that still exists. This shows that the source of the non-linearity has been reduced to C gs4 which is less significant as compared to the parasitic elements inherited within the main PA. This mitigates the amplitude and phase deviation that ensued where R 24 = R 02 R o4 VOLUME 9, 2021 the flat AM-AM and AM-PM responses across the output power, thus conforming broad bandwidth and linearity across frequency. Fig. 8(a) illustrates the simulated opposite AM-AM response produced by the BPD and main PA. The BPD produces a compressing AM-AM response which is opposite to the expanding AM-AM response of the main PA across output power. A flat AM-AM response and increased gain have been achieved up to near compression point across the output power after the two stages have been combined as shown in Fig. 8(b). By considering a deviation of ±0.5 dB, a flat gain is achieved across output power of 18.8 dBm at 0.4 GHz, 23 dBm at 1.7 GHz, and 20.1 dBm at 2.8 GHz, ahead of non-linear compression.
Also, Fig. 9(a) illustrates the simulated opposite AM-PM response of the BPD-PA, where substantial phase deviation across output power is observed in the main PA before the implementation of the BPD. As depicted in Fig. 9(b), the BPD integration abates the phase deviation, resulting in a phase deviation of ±4 • up to output power of 23 dBm at 1.7 GHz (±3 • for 19.8 dBm at 0.4 GHz, ±4 • for 20.1 dBm at 2.8 GHz) conforming that the PA has been linearized. An AM-PM distortion of more than 5 • is equivalent to gain compression of more than 1 dB [25]. The BPD's effectiveness is further validated through the IMD3 and power spectral density (PSD) simulations. The IMD3 simulation has been conducted across the frequency and its result is presented before and after the BPD integration in Fig. 10. By adopting the IMD3 specification of −30 dBc, it can be observed that before the BPD's integration the PA fulfills the specification up to 20 dBm output power at 1.7 GHz (16.5 dBm at 0.4 GHz, 18 dBm at 2.8 GHz). After employing the BPD, it can be perceived that the IMD3 has been enhanced in where the linear output power which fulfills the specification is extended up to 24 dBm at 1.7 GHz (22.3 dBm at 0.4 GHz, 21.7 dBm at 2.8 GHz). The enhanced linear output power validates that the cancellation of the IMD3 product does occur after the BPD's integration with the main PA.
Moreover, the PSD simulation was carried out at 1.7 GHz before and after the BPD integration. It can be observed in Fig. 11 that the spectral regrowth at the sideband frequency is −25 dBc at 24 dBm output power before the implementation of the BPD. After the implementation of the BPD, the spectral regrowth is significantly mitigated to −38 dBc at the same output power condition of 24 dBm in where it satisfies the 20 MHz LTE modulation signal requirement.  The PSD simulation also validates the BPD's capability in reducing the spectral regrowth when tested with modulated signals.

III. MEASUREMENT RESULTS
The proposed BPD-PA is fabricated in a 180 nm CMOS process and integrated on Roger's RO4000 dielectric materials with FR4 cores, two-layer circuit board. The photomicrograph of the BPD-PA which consumes an area of 1.69 mm2 was captured using the eVue digital imaging system. The BPD-PA together with the PCB implementation is illustrated in Fig. 12. Fig. 13 depicts the simulated and measured S-parameters and stability factor of the designed BPD-PA. In measurement, the maximum small signal gain, S 21 achieved is 16.5 dB. The BPD-PA has an operating bandwidth of 2.4 GHz, from 0.4 to 2.8 GHz. The input return loss, S 11 and output return loss, S 22 are less than −10 dB across the aforementioned frequency bandwidth. The BPD-PA also exhibits unconditionally stable characteristics across the operating bandwidth as depicted in Fig. 13. The continuous wave (CW) measured performance at different frequencies for the designed BPD-PA is illustrated in Fig. 14. When measured at 1.7 GHz, it achieves a saturated     This is the region where the effect of the BPD on distortion cancellation is occurring. The BPD extends the linear output power by fulfilling the ACLR specification at high output power levels. Fig. 17 illustrates the current consumption of the BPD-PA with respect to the output power and ACLR at 1.7 GHz. It can be observed that the current consumed by  the BPD-PA is 105 mA at maximum linear output power of 21 dBm where the ACLR specification is met. The resulting power consumption is 347 mW at the maximum linear output power. Since the PCB has a good grounding structure, it allows the current to quickly flow to ground without heating the chip which further increases the efficiency.  Besides that, Fig. 18 shows the normalized PSD of the BPD-PA across the frequency under 20 MHz LTE signal. It can be seen that the sidebands of the PSD are kept below −30 dBm/Hz which indicate the fulfillment of the spectral specification. Fig. 19 depicts the performance of the BPD-PA across the aforementioned frequency bandwidth. Across the frequency bandwidth, the maximum output power varies from 22 dBm to 24 dBm while the peak PAE varies from 33% to 38.6%. The output power at 1 dB compression point (P 1 dB ) and its corresponding PAE are also plotted in Fig. 19. As can be seen, the P 1 dB achieved a minimum and maximum values of 20 dBm and 22.4 dBm respectively, followed by PAE@P 1 dB values of 29.7% and 35.1% respectively. Table 1 summarizes the performance of the proposed BPD-PA in comparison with recent published works.

IV. CONCLUSION
A broadband BPD-PA operating from 400 MHz to 2.8 GHz has been proposed. The integrated BPD resolves the AM-AM and AM-PM deviation faced by the main PA thus contributes to the linearity enhancement. Compared to APDs which utilize inductors that result in narrowband due to dependency on the Q factor, our BPD consists of only MOS transistors, resistors, and capacitors which contribute to the wideband operation. It is also area-efficient since the use of inductors is eradicated albeit a little more power consumed as compared to passive loads. A flat AM-AM response and a less than 4 • AM-PM deviation have been achieved across output power for a wide frequency range. With CW signal, the BPD-PA achieved a maximum output power of 24.3 dBm with a corresponding power gain of 16.5 dB as well as a peak PAE of 38.6% at 1.7 GHz. The BPD-PA also fulfills the 20 MHz LTE signal's ACLR requirement of −30 dBc for output power up to 21 dBm. The designed BPD-PA serves to be a good solution to be implemented in broadband transmitters, with a reduced trade-off in PAE.