Design and Analysis of Simultaneous Wideband Input/Output Matching Technique for Ultra-Wideband Amplifier

A simultaneous wideband input/output matching technique for ultra-wideband (UWB) low-noise amplifier (LNA) is proposed in this paper. Feedback resistors leading the gate inductors combined with inductive dividers at output ports achieve an extended bandwidth and good input/output return loss. Moreover, $Q$ -factor improved vertical solenoid inductors are used in the matching networks for high gain and low noise figure (NF). The proposed matching technique, not only enhances the bandwidth, but also achieves a high gain and a low NF for the fabricated 3.1-10.6-GHz monolithic 180-nm CMOS UWB amplifier. Operating at low supply voltage, the measured power consumption is 18.9 mW, the measured gain of the UWB LNA is 15.02 dB, and the NF is 3.1 dB. Moreover, the measured input/output reflection coefficients S11 and S22 are lower than −9.4 dB and −15.8 dB, respectively, covering the full-band UWB frequencies. Compared to previously published full-band 3.1-10.6-GHz 180-nm CMOS UWB LNAs, the proposed LNA measurements demonstrate high gain, low NF, low supply voltage, low power dissipation, and good input/output reflection coefficients.


I. INTRODUCTION
The demand for radio frequency (RF) and high data rate communication systems has led to the use of higher frequencies and larger bandwidths [1]- [11].
While the size of transistors continues to shrink, the supply voltage must be scaled down proportionally, due to the reliability of the gate oxide [5]. However, the low transconductance of the MOSFET at high frequencies affects significantly the design of low voltage and low power RF front-ends. To improve circuit performance, a network for simultaneous wideband input and output matching is proposed in this work. Wideband input matching is achieved by a feedback resistor at the input inductor of the cascode input stage. Moreover, an inductive divider is used at the output of the LNA for a better reflection coefficient S 22 . Using these approaches, the small signal gain and the NF of the UWB LNA covering all UWB frequencies, are improved. This paper is organized as follows. In Section II, the proposed UWB LNA with wideband input and output matching networks is introduced and design considerations of the The associate editor coordinating the review of this manuscript and approving it for publication was Yuh-Shyan Hwang. bandwidth enhancement technique are presented. Section III provides experimental results and the characterization of the LNA. Finally, conclusions are provided in Section IV.

II. PROPOSED MATCHING TECHNIQUE FOR UWB LNA
The operating principles and the performance limitations of several circuit topologies for wideband LNAs are presented. The first topology, shown in Fig. 1(a), uses a resistive termination of the input port to provide an input impedance of 50 . Although this topology attains a good reflection coefficient (S 11 ) over the band of interest, the noise performance that is achieved is low. Fig. 1(b) illustrates the second architecture using a selfbiased inverter amplifier with resistive feedback as the first stage of the UWB LNA design [7]. With dual feedback and LC-ladder matching network, the architecture provides broadband matching for a common-source amplifier. However, the noise performance is limited because of the input matching network where resistive losses increase the minimum possible noise figure (NF min ) of the circuit.
The third circuit topology employing a common-gate MOSFET device is shown in Fig. 1(c). The advantage of FIGURE 1. Circuits with widely used wideband input matching topologies: (a) resistive termination, (b)self-biased inverter amplifier with a feedback resistor, (c)common-gate MOSFET device, (d)resistive shunt-shunt feedback.
common-gate (CG) LNA is its low input impedance, which can easily be adjusted and matched to 50 . Note that the dominant noise source in CMOS devices is channel thermal noise [6], [10]. This source of noise is typically modeled as a shunt current source at the output circuit of the MOS-FET. Fig. 1(d) depicts the widely used architecture for UWB LNAs. Based on the cascode configuration and on a resistive shunt-shunt feedback, the architecture allows extending the bandwidth of the LNA [10] and improving the gain, the stability and the isolation between the output and the input.
To enhance the circuit performance of an UWB amplifier in terms of bandwidth, gain, NF, supply voltage, and DC power dissipation, a novel bandwidth enhancement technique (feedback resistors R F1 , R F2 , leading gate inductors L g2 , L g3 and inductive dividers L D3 and L D4 combined with C F2 and R F2 at output ports) is proposed in this work, as shown in Fig. 2. The design considerations of the proposed matching technique and application for an UWB amplifier are presented in details as follows.

A. SIMULTANEOUS WIDEBAND INPUT/OUTPUT MATCHING CONSIDERATIONS
To achieve a high gain, the matching circuit at the input of the LNA is essential. Fig. 3(a) shows a widely used narrowband input matching technique; the input impedance of the circuit can be derived as [12, p. 173] Z g = s(L g1 + L S1 ) + 1 sC gs1 + g m1 L S1 C gs1 (1) where g m1 is the device transconductance and C gs1 is the parasitic capacitance between the gate and the source terminals of the active device M 1 . Moreover, the inductors L S1 and L g1 are selected to resonate with C gs1 and to cancel the imaginary part of the input impedance. The value of the C gs1 is 150 fF. The values of the L S1 and L g1 are 0.16 nH and 1.4 nH, respectively. Setting the imaginary part of (1) to zero, the resonance frequency can be expressed as At matching, the input impedance of the LNA is equal to Z o , the resistance of the signal source. Given that the real part of (1) is equal Z o , it follows that Therefore, the inductance of L S1 can be determined by the parameters Z o , C gs1 , and g m1 . Although the input matching network consisting of L S1 , L g1 , and C gs1 shown in Fig. 3 (a) can be perfectly achieved, the matching is suitable only for a narrowband LNA design. For wideband input matching, resistive shunt-shunt feedback is adopted in regular LNAs, as shown in Fig. 3(b). However, the noise performance and the gain of the circuit in Fig. 3(b) are still limited, compared to Fig. 3(a).
To further improve the input/output reflection coefficients and small-signal gain, a cascode resistive shunt-shunt feedback with a bandwidth enhancement technique (feedback resistors R F leading gate inductor L g1 and combining with inductive dividers at output port) is proposed in this work, as shown in Fig. 3(c). The input impedance of the proposed circuit can be written as Z in = Z g //Z f_in , where Z g is the input impedance of the amplifier stage without the feedback circuit, and Z f_in is the impedance looking into the feedback resistor R F . The impedance Z g can be written as (1), and the passives L g1 , L S1 , C gs1 are determined by (2)-(3).
The impedance Z f_in can be formulated as where C gs1 and C d2 are the parasitic capacitors. In a typical design,s 2 C gs1 L g1 + L S1 + sg m1 L S1 1, 1 are satisfied. Consequently, the expression of Z f _in in (4) can be approximated by (5) Setting the imaginary part of (5) to nil allows determining the resonance frequency f o2 of the circuit in Fig. 3(c) where C d2 is the parasitic capacitance between the drain of M 2 and the inductor L D1 . The value of the C d2 is 250 fF. Moreover, the inductors L D1 and L D2 are selected to provide the required output impedance. The values of the L D1 and L D2 in this work are 0.4 nH and 8.9 nH, respectively.
Considering (1) and (5), the overall input impedance (Z in ) of the proposed circuit shown in Fig. 3(c) can be written as (7), as indicated earlier.
In this UWB LNA, the circuit parameters are C gs1 =150 fF, Fig. 4 plots the calculated input return loss S 11 with respect to frequency for Z g , Z f_in , and Z in (= Z g //Z f_in ) of the proposed matching circuit in Fig. 3(c). As seen in Fig. 4, the wideband input matching can be effectively achieved by introducing a pole of frequency f o2 . . Calculated input return loss S 11 with respect to the frequency for Z g , Z f_in , Z in (= Z g //Z f_in ; R F leading L g1 ) of the proposed topology in Fig. 3(c) and Z in (R F lagging L g1 ) of the conventional topology in Fig. 3(b).
Consider the circuit topology in Fig. 3(b) of regular matching with feedback resistor R F lagging gate inductor L g1 , the overall input impedance of the circuit can be written as Z in is plotted in Fig. 4 and it is found that the proposed input matching circuitry (feedback resistor R F leading gate inductor L g1 and combining with inductive divider at output) achieves a better input return loss from 3.1 to 10.6 GHz than the regular circuit in Fig. 3 For UWB amplifiers, the design of output impedance matching is also critical. However, it is seldom considered for UWB LNAs in the literature. Considering the proposed circuit topology in Fig. 3(c), the output impedance Z out without feedback resistor R F can be expressed as where Z o2 is the output impedance of the cascode stage. The output impedance Z f_out looking into the feedback resistor R F can be written as where C in is a DC block, and its value is 4.11 pF. The combination of an inductor L D2 and a capacitor C byss is the RF choke. Considering (9) and (10), the overall output impedance of the proposed circuit in Fig. 3(c) is Fig. 5 shows the calculated output return loss S 22 with respect to the frequency for Z out_wo_fb and Z out of the proposed LNA. It is indicated that not only the output reflection coefficient S 22 is significantly improved, but also the bandwidth (S 22 <−10 dB) is effectively extended.
Consider the regular output matching circuit topology shown in Fig. 3(b), the overall output impedance can be driven as which is also plotted in Fig. 5. Compared to the conventional design, the presented inductive divider circuitry at output not only achieves much better output return loss (S 22 ), but also extends the bandwidth. Fig. 6 shows the small-signal equivalent circuit of the proposed UWB LNA plotted in Fig. 2, where C gs1 , C gd1 , C gs3 , and C gd3 are the parasitic capacitances, and R Lg2 , R Ld1 , R Ld2 , and R Ld4 are losses from the on-chip inductors L g2 , L d1 , FIGURE 5. Calculated output return loss S 22 with respect to the frequency for Z out_wo_fb , Z out of the proposed topology in Fig. 3(c) and Z out (R F lagging L g1 ) of the conventional topology in Fig. 3(b).

B. SMALL-SIGNAL GAIN AND NOISE FIGURE CONSIDERATIONS
L d2 , and L d4 , respectively. For simplification of the analysis procedure, the parasitic capacitance C gd1 and C gd3 are neglected. Moreover, it is assumed that the currents flowing through the intrinsic resistors (r o1 , r o3 ) and the forward-body biased currents (g mb1 v bs1 , g mb3 v bs3 ) are much smaller than the current sources (g m1 v gs1 and g m3 v gs3 ). Therefore, the smallsignal gain of the proposed UWB LNA can be expressed as where The ω o,in1 and ω o,in2 are the series resonance frequencies, and Q in1 and Q in2 represent the Q-factors of input networks at the frequencies (ω o,in1 and ω o,in2 ) for LNA's first VOLUME 9, 2021 FIGURE 6. Small-signal equivalent circuit for the proposed full-band 3.1-to 10.6-GHz UWB LNA employing the simultaneous wideband input/output matching technique (feedback resistors R F 1 , R F 2 leading gate inductors L g2 , L g3 and combining with inductive dividers at output ports). and second stages, respectively. According to Section II(A) and Fig. 4, it is known that the created series resonance frequencies (ω o,in1 and ω o,in2 ) indeed improves the input reflection coefficient (S 11 ) and effectively extended the bandwidth. Moreover, the Q-factor of the input matching network (Q in1 ) can be improved by using fully-integrated on-chip vertical solenoid inductors due to improved Q-factor (Q Lg2 ) than that of conventional planar inductors, leading to high gain.
The noise factor of the proposed circuit topology with simultaneous wideband input/output matching technique (feedback resistor R F leading gate inductor L g1 and combining with inductive divider at output port) shown in Fig. 3(c), is expressed in (34). It is known that the coefficients (κ and ξ ) in (31) and (33) have influences on overall NF in (35). It is also observed that the coefficients (κ and ξ ) are function of ω o,in1 . By utilizing the proposed matching technique, the bandwidth is extended due to the series resonance frequency (ω o,in1 ). Moreover, it minimizes the coefficients (κ and ξ ) in (31) and (33), leading to a reduced noise factor F and noise figure NF. From (34) and (35), it is found that using Qfactor improved vertical solenoid inductors in this work can lead to reduced NF.
Moreover, to minimize the body leakage current, the 5-k resistors are inserted between the bodies and supply voltages (V b1 , V b2 , and V b3 ), as shown in Fig. 2. This can lead to the minimized body leakage currents of 59.7 pA, 35.8 pA, and 2.05 pA, respectively.

III. EXPERIMENTAL RESULTS
The LNA was fabricated in a 180-nm CMOS process and the size of the fabricated chip is 0.945 × 0.82 mm 2 , excluding the testing pads. The microphotograph of the chip is represented in Fig. 7. On-wafer probing was used to characterize the UWB LNA. The losses of the measurement setups were de-embedded and calibrated in the experimental results. In this work, the MOSFETs (M 1 -M 3 ) operate in saturation region with supply voltages of V DD1 =1.5 V and V DD2 =0.75 V, leading to the measured overall DC power dissipation of 18.9 mW. In [13]- [15], the adopted 1.5-V supply voltage is also widely used for low-voltage low-power 180-nm CMOS circuits. For applications, the used 0.75-V supply voltage can be generated from a bandgap circuit [16]. Fig. 8(a) shows the measured and simulated S-parameters of the UWB LNA with simultaneous wideband input/output matching technique (feedback resistors R F1 , R F2 leading gate inductors L g2 , L g3 and combining with inductive dividers at output ports). It is observed that the measured maximum gain (S 21 ) of the UWB LNA is 15.02 dB. In addition, the measured 3-dB bandwidth of the UWB LNA is 2.4 GHz to 13 GHz, while the gain (S 21 ) varies from 12.02 dB to 15.02 dB. This results in 138% fractional bandwidth. Fig. 8(b) illustrates the measured, simulated, and calculated input return loss (S 11 ) of the LNA. As shown from this figure, the measured input return loss (S 11 ) of the UWB LNA is below −9.4 dB. Fig. 8(c) illustrates the measured, simulated, and calculated output return loss (S 22 ) of the UWB LNA. It shows that from 3.1 to 10.6 GHz, the measured S 22 of the LNA is below −15.8 dB. According to Fig. 8(b) and Fig. 8(c), the derived formulas (7) and (11) in Section II can be used to evaluate the input and output impedances.
The measured and simulated NF of the proposed UWB LNA is depicted in Fig. 9. It is observed that the measured minimum NF of the LNA is 3.1 dB. Moreover, the measured NF of the LNA covering the full-band UWB frequency (3.1-10.6-GHz) varies between 3.1 dB to 4.4 dB. Furthermore, the differences between the calculated noise figure (35) and the measured result are within 1 dB in entire UWB.  This justifies the transistor noise model used in this work for predicting NF. Fig. 10 represents the measured input-referred third-order intercept point (IIP 3 ) of the UWB LNA. The characterization is carried out by using two-tone tests, and the frequencies of these two-tones for the UWB LNA are at the maximum gain frequency of 4.9 GHz with 1-MHz spacing.   Fig. 10, the value of IIP 3 for the UWB LNA is −6 dBm. Fig. 11 shows the simulated IIP 3 of the fabricated 3.1-10.6-GHz wideband LNA, and the average IIP 3 over the entire frequency band is −6.1 dBm. It is known that the linearity (IIP 3 ) of a receiver is typically dominated by the following stages (e.g., mixer or IF amplifier) [22]. Moreover, the IIP 3 greater than −18.1 dBm is acceptable for a UWB system [23]. Fig. 12 depicts the measured and simulated group delay of the fabricated UWB LNA. It observed that a minimum group delay of 71.3 ps is achieved. The measured and simulated stability factor (K-factor) is shown in Fig. 13, indicating that the UWB LNA is stable (K > 1) in the entire frequency band. Table 1 summarizes the measured performance of the proposed UWB LNA shown in Fig. 2, and compares them to the performances of previously published full-band 3.1-10.6-GHz 180-nm CMOS UWB LNAs. It is confirmed from table 1 that the proposed UWB LNA achieves low supply voltage with low DC power dissipation of 18.9 mW, high gain of 15.02 dB, low NF of 3.1 dB, and good input/output return loss −9.4 dB/−15.8 dB. It is observed that the output return loss (S 22 ) is significantly improved by using the proposed technique. In addition, figures of merit (FOM) for LNA   presented in [19] can be written as

IV. CONCLUSION
This work has proposed an UWB LNA using a simultaneous wideband input/output matching technique (feedback resistors R F1 , R F2 leading gate inductors L g2 , L g3 and combined with inductive dividers at output ports). Wideband input matching is achieved by the addition of a pole resulting from an inductive divider at the output port and whose frequency f o2 is given by (6). Moreover, the wideband 46806 VOLUME 9, 2021 FIGURE 14. Equivalent circuit of the proposed circuit in Fig. 3(c) including the noise sources.
output matching is significantly improved owing to the R F leading L g at the input port and the inductive divider at the output port, as illustrated in Fig. 5. Furthermore, the NF of the LNA is improved owing to the series resonance frequency (ω o,in1 ) in the wideband input matching network, leading to a low noise figure covering the full UWB. Measurement results show that the fabricated UWB LNA, using simultaneous wideband input/output matching technique, compares favorably with similar designs.

APPENDIX NOISE FIGURE FORMULATION
In this appendix, the NF of the proposed circuit shown in Fig. 3(c) is analyzed. It noted that the dominant noise source for MOSFET devices is the channel thermal noise [6], [10]. Moreover, this type of noise source is typically modeled as a shunt current source at the output circuit of a MOSFET, and its value can be formulated as where k is the Boltzmann constant, T is the absolute temperature, γ is a bias-dependent factor, g d0 is the zero-bias drain conductance of the device, and f is the frequency. Operating in saturation, the value of γ is 2/3 for long-channel devices.
As for a deep-submicron MOSFET, (21) has to be modified as where g m is the transconductance of MOSFET, and α is the ratio of g m to the zero-bias drain conductance g d0 . The values of α and γ of deep-submicron MOSFETs are typically less than 1 and greater than 1, respectively [20]. Thus, this will result in a raised channel thermal noise i 2 n,d for the deepsubmicron MOSFET.
From Fig. 14, the output noise power density due to the source resistance R S at the frequency of interest ω o,in1 can be formulated as Moreover, the output noise power density due to the series resistors R Lg2 and R gate1 can be written as Furthermore, the dominant noise contributor internal to a UWB LNA is the channel current of MOSFET for the amplifier's first stage. Its output noise power density arising from this channel thermal source around the frequency ω o,in1 is Substituting (21) into (25), the formula (25) can then be rewritten as In addition, a gate noise current i 2 n,g will be induced due to the capacitive coupling from a channel noise current i 2 n,d . From [21], the induced noise current at gate terminal is presented by where g g = ω 2 C 2 gs 5g d0 · The δ is the coefficient with a value of 4/3 for long-channel devices. The channel noise current i 2 n,d and the induced gate noise current i 2 n,g are closely related with a coefficient c, VOLUME 9, 2021 which is defined as [20], [21] c ≡ i n,g i * n,d i 2 n,g i 2 n,d For this work, the values of δ and c are 3.4 and 1.0j for the 180-nm MOS, respectively [24]. As a result, the output noise power density from the internal noise current at the frequency of interest ω o,in1 can be divided into two categories. The first term represents the combined effect of the drain noise current and the correlated portion of the gate noise current, and it is given by S a,i n,d ,i n,g ,c ω 0,in1 = κ · S a,i n,d ω 0,in1 = 4kT γ κg d0 The second term is with the uncorrelated gate current noise, which can be written as S a,i n,g ,u ω 0,in1 = ξ · S a,i n,d ω 0,in1 = 4kT γ ξ g d0 ω 2 0,in1 R 2 S g m1 L S1 R S where ξ ω 0,in = δα 2 5γ 1 − |c| 2 1 + 1 To evaluate the NF reduction of the UWB amplifier, the calculated total output noise including (23), (24), (30), and (32) is divided by the total output noise due to the source resistance (23). Assuming the bandwidth is 1 Hz, it yields the noise factor F, which can be derived as Consequently, the noise figure can be given as NF = 10 log 10 F For this work, the values of α, γ , and g d0 for the 180-nm MOSFETs are 0.6, 1.8, and 2.5 mS respectively [24], [25]. Moreover, the value of R gate1 for the W /L =152µm/180nm NMOS in this work is 42 .