A Hysteresis Space Vector PWM for PV Tied Z-Source NPC-MLI With DC-Link Neutral Point Balancing

The Photo-voltaic (PV) tied Z-source Neutral-point clamped multilevel inverter (Z-NPC-MLI) is used in solar grid connected applications due to its single stage conversion and better performance. Though the Z source inverters adaptation is accepted in grid connected technology, the need for suitable controller and PWM scheme are necessary to meet out the performance such as shoot through switching, neutral point balancing, and harmonic reduction. The space vector pulse width modulation (SVPWM) strategy is a prominent modulation technique for Z-source NPC-MLIs due to the flexibility to select the appropriate voltage vector. Previous publications have shown the control of a Z-source MLI using the SVPWM with and without modification of shoot through switching. However, the current controller (CC) based SVPWM is not matured, which is the most essential consideration for the grid connected inverter to provide neutral point balancing, shoot through control for low harmonic distortion and a high quality current. With all these aims, this paper presents a PV tied Z-NPC-MLI grid connected system with a unique hysteresis current control SVPWM (HSVM) strategy with neutral point (NP) balancing control and direct current control in the inverter input side. Also, the proposed HSVM is assuring the grid connection with high quality voltage and current waveforms. This CC based SVPWM for Z-NPC MLI has been validated through simulation and FPGA based experimental investigations. The results are confirmed the feasibility and reliability of the proposed HSVM for the PV tie grid connected Z- Source NPC-MLI.


I. INTRODUCTION
Renewable resource (RER) is inevitable in the present power generation system (PGS) era which recently witnessed an exponential growth worldwide, and is expected to continue in the same direction. After hitting about 401GW of solar photo-voltaic (PV) power capacity by the end of 2017, global solar PV capacity is expected to hit 800GW soon [1]. The photo-voltaic (PV) power generation needs a two-stage power conversion (DC to DC by buck-boost converters and DC to AC by inverters). Nevertheless, due to this two-stage power conversion and converters usages, the overall system cost and efficiency is not desirable, since it involves more active and The associate editor coordinating the review of this manuscript and approving it for publication was Alon Kuperman . passive components [2]. After the arrival of Z source inverters [3], the two-stage power conversion (DC to DC and DC to AC) is made possible through single stage(DC to boosted AC), which reduced circuit size, losses and cost [4]. Hence Z-source inverter is considered an interesting topology for drives and PV applications [5]- [7] The combining Z source concept with multilevel inverters (MLIs) is most successful in terms of reduced conversion stage, enhanced system performance [8], [9]. Particularly, Neutral-point clamped (NPC) MLI is the good choice among other MLI topologies due to their circuit structure and operation is quite similar to conventional six switch voltage source inverter (VSI) [10].
In Z source inverter, the boost operation is decided by the shoot through (ST) switching state, in which the inverter input DC-link voltage is short circuited via Z source inductors and capacitors [11]. When the pulse width modulation (PWM) is used in the Z source inverter, it is fully capable to handle ST events for handling the inverter internal issues such as DC-link control and to improve quality of the output. The PWM approaches are investigated by adjusting the carrier positions and altering the shoot through (ST) for minimum, constant and maximum boosting methods. The SVPWM strategy provides opportunity to deal the switching sequence directly [12], [30], which facility is not possible in carrier based PWM. The P. C. Loh et.al has proposed SVPWM for controlling three-phase three-level Z-MLI with 24 ST options [13]. Followed by [14] F. B. Effah et.al developed a new set of ST options, where the authors used 12 ST states. These attempts have well concluded about controlling the inverter voltage. However, the current control is not attempted which the main factor of dc-link capacitor balancing.
In grid connected power systems, to overcome the transformer usage issue, researchers have proposed different PV powered transformerless (TL) inverters for both single and three-phase systems [15,16]. There are many innovations in single phase TL inverter topologies, in which the idea is to only mitigate the leakage current by adding the extra power switches in the main inverter circuitry. In three-phase networks, the researchers are totally involved with PWM and current control design algorithms [17], [18]. The Z source MLIs are the better choice for PV applications compared to two-level VSIs, with respect to reduction of harmonic content output waveforms and common mode voltage (CMV) suppression filters and EMI filters. According to TL grid tied inverter, the control of the inductor current along with the grid voltage synchronization is essential. Therefore, the combined current controller (CC) and voltage control PWM is interesting for such TL grid connected system. There are a variety of CCs are available for controlling the electrical power [19]. Among them, the hysteresis current controller (HCC) is a potential one, as it has simple control competence associated with PWM methods [20], [21]. Very few attempts have been made on SVPWM based HCC [22], [23]. However, these methods are involving difficult mathematical operation to locate the active switching vector and also the capacitor balancing is very hard to attain. In practice, maintaining these capacitors is much challenging. This deceptive curtail reduces the NP capacitor's lifespan due to the NP fluctuation between the capacitors crops the high voltage and current harmonics, which leads to the inferior grid power quality. There are few attempts made for capacitors balancing through the separate balancing circuits as well as PWM algorithms [24]- [27], [31]- [33]. Here, rather a circuit based balancing; PWM algorithms gave an attractive result. Among the reported PWM methods and their ideologies, the SVPWM based consideration was superficies [29]. Based on the above organized discussion, the TL PV tied grid system requires a stable power converter, current controller and PWM technique for the straight forward operation, less cost, and high performance. In context with capacitor balancing in Z source NPC MLI, few examples found in [28], [31] using SVPWM and carrier level-shifted based control, which are not discussed about the current control.
With this motivation, this paper suggests the three-phase three-level PV connected Z source-MLI for the utility grid. The Hysteresis current control based SVPWM (HSVM) control system is designed for the grid synchronization. The proposed HSVM eliminates the low frequency oscillations using suitable ST (Upper and Lower ST), with regular switching events, which ensures the DC-link capacitors balancing along with current control. The proposed system is simulated and verified through MATLAB/Simulink software. The experimental prototype 2-kW solar panels attached grid connected three-phase three-level Z-NPC-MLI is established and the validation is done through Xilinx family SPARTAN-6 controller. The results obtained from the simulation and experiment is confirming the technical feasibility and advantages such as reduced harmonics and neutral point balancing of the proposed HSVM.
In addition the results have shown the uniqueness of the proposed current controller involvement with SVPWM for improving the inverter performance. The section II elaborates about the Z source NPC-MLI topology, concepts of shoot through, and design concepts of Z network. The HCC based SVPWM for Z-NPC-MLI is presented in section III. Section IV brings out the simulation and experimental verifications. Finally, conclusions are summarized in section V.

II. Z-SOURCE NPC-MLI TOPOLOGY
The Z-source concept applied to MLI gives more advantages like suppression the voltage ripples, flexible shoot through state and neutral point balancing. Therefore, this session describes the Z-NPC-MLI power circuit, its operation and the design of Z Network components along with analysis of topology.

A. Z-NPC-MLI
The Fig.1 shows the power circuit topology of Z-NPC-MLI in three-phase three-level structure, which consists of three legs, and each leg has four power switches (S 1A − S 4A ) with VOLUME 9, 2021 2 clamping diodes (D A1 and D A2 ). The Z source impedance elements (L 1 = L 2 = L, C 3 = C 4 = C) are connected in the input side and obtaining power from DC-link. Two DClink capacitors (C 1 , C 2 ) are serially coupled with DC input source, which split the DC-link voltage as V DC /2 for making the multilevel output as 0, V DC /2, and V DC . In the load side, each inverter leg is connected to grid by using inductor (L A = L B = L C = Lg). The Z-NPC-MLI is operating with shoot through (ST) and non-shoot through (NST) modes. In ST mode, the input DC supply is short circuited through inverter switch and Z -network inductors, to store the energy in the inductors, L1 and L2. During NST mode, the DC power is converted to AC power (through normal inverter switching).
The Z source impedance elements (L 1 = L 2 = L, C 3 = C 4 = C) are connected in the input side and obtaining power from DC-link. Two DC-link capacitors (C 1 , C 2 ) are serially coupled with DC input source, which split the DClink voltage as V DC /2 for making the multilevel output as 0, V DC /2, and V DC . In the load side, each inverter leg is connected to grid by using inductor (L A = L B = L C = L g ). The Z-NPC-MLI is operating with shoot through (ST) and non-shoot through (NST) modes. In ST mode, the input DC supply is short circuited through inverter switch and Znetwork inductors, to store the energy in the inductors, L 1 and L 2 . During NST mode, the DC power is converted to AC power (through normal inverter switching).
By considering one leg in NPC-MLI, the operation is described by three switch options; 1(both upper switch ON), 0(middle switch ON),-1(both lower switch ON). Including Z source operation with NPC-MLI regular switching operations, the ST mode is created in order to short the input DC supply through inductors by switching ON all the four switches in the leg, which is called as full shoot through (FST). Alternatively, for reducing the switching losses, the top ST (top 3 switches is ON in a leg) and bottom ST (bottom 3 switches is ON in a leg). The table-I describes all the possible combinations of the switching options for Z-NPC-MLI.

B. ST AND NST OPERATION OF Z-NPC-MLI
The ST and NST mode of operation of the circuitry is shown in the Fig.2. During the ST mode, the inverter can be involved either full ST or partial ST [28]. Though, the both methods are shorting the input DC source via inductors L 1 and L 2 , the full ST(FST) is not a best choice of balancing the inductor's charging profile (nonlinearity charging) and it roots the high magnitude of lower order harmonics in the output waveforms. Since the top-ST(TST) and bottom-ST(BST) has an individual control on the L 1 and L 2 charging characteristics, the combination of TST and BST maintains the inductors charging in parallel, which ensures the better quality output waveform [8], [13].

C. DESIGN OF Z SOURCE NETWORK
The In the Z network, calculation of the Z network elements (Inductor(L) and Capacitor(C)) and its charging, discharging and boosting functions are important. During ST period, while considering the symmetry charging and discharging nature on L (L 1 = L 2 = L) and C (C 3 = C 4 = C), the role of the inductor is to limit the current ripple during shootthrough state. The capacitor absorbs the current ripple and achieves a quite stable voltage. The inductor is charged by the capacitor during shoot-through time(T sh ). I is current ripple of the inductor.Inductor and capacitor values are calculated as L = VT sh I and C =Ī L T sh V C respectively. The average current of the inductor can be found fromĪ L = P V PV . The V C is the assumed voltage ripple of the capacitor. V PV is PV output voltage, P is the total power. The voltage across the inductors and capacitors are approaches to V L and V C respectively, This condition is satisfied, since the capacitors C 1 and C 2 are connected in parallel and voltage across the Z source network will be 2V C . In ideal conditions, V L = V C and 2V C = 2V dc . During this condition, the inverter output voltage, V o = 0.
From the Fig 2, considering NST mode of operation (see Fig. 2.a); when diode D 1 and D 2 are in forward bias conduction, The inductor voltage, During TST mode operation as shown in Fig.2.c, the diode D 1 is in conduction and D 2 is in blocking state. Hence, the inductor voltages are obtained as, During BST mode operation as shown in Fig.2.d, the diode D 2 is in conduction and D 1 is in blocking state. Hence the inductor voltages are obtained as, At steady state condition, the Z-network inductors L 1 and L 2 average voltage in one T cycle is zero.
Using V C in NST, TST and BST mode operations, the DClink voltage of the inverter for NST, TST and BST is derived as, Form the Eqs. (11) and (12) during TST and BST, the voltage present in the DC-link is half that of NST. Hence, it is proven that by equally sharing TST and BST mode using input DC-link capacitors (C 1 and C 2 ), the inverter is boosting voltage with proper DC-link balancing, which helps to improve the THD performance on the output voltage and current waveform. The inverter peak ac voltage output, Vx 0 (x={A,B,C}) is resulting as, where B F is boosting factor (B F ≥ 1).

III. HCC BASED SVPWM FOR Z-NPC-MLI
SVPWM technique offers the flexibility in selection of switching states [14]. The hysteresis current control (HCC) method gives an opportunity of harmonics reduction.
To widen the scope of SVPWM, the hysteresis current control strategy has been incorporated to achieve the better harmonic reduction and neutral point balancing in Z source NPC-MLI. The theory of SVPWM presented in view of conventional and proposed techniques. A closed loop PV-tied grid connected control strategy developed is described in this section.

A. OPERATION OF CONVENTIONAL SVPWM FOR NPC-MLI
The Fig. 3 For balanced DC-link condition, the I N should be zero. Table-II shows the different switching of the three phase currents for the three-level NPC-MLI. Here, the ZV and SV have a redundant switching privilege, which helps balancing the DC-link. However, the MV and LV has only unique switching option for a sector. Hence, these vectors not helping for NP self-balancing. The Fig.4 shows the SVD with their different switching states of ZV, SV, MV and LV including phase currents. Now, for creating TST and BST, the proposed SVPWM is considering SVs, since they have a redundant switch- The ST interval for both TST and BST is depend on the boosting factor using Eq (12). In order to maintain the NP self-balancing and volt-sec balancing, the inverter switching selections are starting from A-phase to C-phase in a forward switching and following the reverse same sequence order. The TST and BST switching states timing is sharing from the regular switching, which ensure the symmetry output voltage. For example in Fig.6, when the target vector lies in 1,2 the TST is time calculated from the boosting factor and it is fixed between [0 −1 -1] and [1 −1 −1] without changing switching frequency. Using this method, the number of power switching commutations in a switching cycle is same as traditional NPC-MLI, which ensures the switching losses in the In proposed SVPWM current control method, the hysteresis bands are directly used to employ the four groups of (ZV, SV, MV and LV) vectors in SVD. Here the current control is made based on current error (error vector, − → i ) and available switching options on SVD. The proposed structure is principally employed to retain the − → i Lact close to the − → i Lref inside the hysteresis band values. To compensate for the complication of achieving the CC along with capacitors balancing, the SVPWM is modified based on the hysteresis band 'H'.
Fixed frequency HCC can be obtained by calculating the hysteresis band H using the transient value of the V g and output voltage of PV array.
Based on that, the hysteresis band 'H' is calculated as, where, the variant parameters are V PV , V g , f S and fixed one is filter inductor (L). When the reference current (i Lref ) and actual current (i Lact ) lie in SVD error vector, − → ε i is calculated as, where, − − → i Lref = i Lref α + ji Lref β ; − − → i Lact = i Lactα + ji Lactβ When the − → ε i expressed in the SVD plane with αβ-vector  components frame, the − → ε i can be represented as, From Eq (17), the position of the − → ε i in SVD is calculated and then the switching vectors are selected to keep the − → i Lact close to the − → i Lref . The Fig.8 shows the HSVM with − → ε i and H. Here, the sector and sub-triangle, and its switching state selection is done based on the − → ε i and H. The boundary area is determined by the hysteresis bands (H 1 and H 2 ).
The values of H 1 and H 2 depends on − → i Lref and its control dynamics. The values of H will vary between zero and H (Eq.15). Here the maximum value of the H is related with maximum operation modulation (Modulation Index, M a ). To VOLUME 9, 2021 find the value of − → ε i and H, the proposed SVD operating in three environments which are H 1 , H 2 , and > H 1 + H 2 .
During the H 1 interval the switching selection is directed to use for ZV and SV. Similarly, for H 2 the SV and MV, and when H is beyond H 1 + H 2 , the SV, MV, LV switching states are selected.

C. NEUTRAL POINT/DC-LINK BALANCING
In the proposed HSVM is using nearest three vectors N3V switching selection vector selection [20], [22]. Based on the − → ε i tip, the HSVM choose the sector and sub-triangle, and switch the vertices of the triangle in every switching period for the hysteresis region using all available vector to get zero phase current. For example, if − → ε i tip is situated in H 1 region, the control lies in the triangle 1 Fig.10. Here, the SV switching sequences [0 −1 −1], [110] has chosen as a starting switching state to synthesis the reference vector. Hence, at target reference vector lies in 1 , 3 the vector synthesization is happen in two time to balance the capacitor. Other sub-triangles 1,2 and 1 , 4 are have only one, since they involve MV and LV. As shown in Table-1, and in the LV phase current is zero. However, the MV showing the particular phase current which is causes the small disturbance in DC link balancing. As per the NP fluctuation standard this is considerably small.
Actual load current and reference current tracking performance with fixed H band (5Amps). The tracking performance is executed with 50Hz and 60 Hz reference current. From the waveform, it could see that the actual current is clearly tracking the reference current with decent steady state and transient response. To validate the DC-link capacitors (V C1 and V C2 ) balancing for HSVM, the simulation is performed for both conventional and proposed HSVM, which are shown in Fig. 14 (a) and Fig. 14. (b), respectively. The NP fluctuation (NPF) is calculated from V C1 and V C2 ; From the Eq.(18), the proposed HSVM NPF is very less (calculated as ≈1%) the conventional Z-source SVPWM (calculated as ≈10%), which ensure the output voltage and current waveform quality. Based on the results, the proposed HSVM claims that it is not only controlling current and it is also maintaining the NP current.

D. CLOSED-LOOP PV TIED GRID-CONNECTED CONTROL STRATEGY OF PROPOSED Z-NPC-MLI
The grid-connected PV connected Z-NPC-MLI control blocks representation is shown in Fig. 9. The system is classified into four modules, namely; PV module, boosting X-network, Z-NPC-MLI, and grid interfacing control system. In the solar module, the PV voltage and current are measured and given to P&O technique based MPPT. Here the λ is arrived from MPP gain and given as ST to HCC. The ouput of This I * ref is compared with PV reference current (I PV −ref ) and estimating the final grid reference current dc-component (I ref ), which is multiplied with sin ((w g +f s )+(2πθ g /360)) to calculate the final grid reference current (I ref ). It is also called a inductor reference current (I Lref ). The actual inductor I Lact and I Lref gives the error of inductor current ie based on the − → ε i = (i Lref −i Lact ). Finally, the calculated real-time hysteresis band H using eq (15) and ie gives gate pulses. The error ie and λ obtain the inverter switching options and ST duty cycle for the boosting, current controller and capacitor balancing of the Z-NPC-MLI.

IV. SIMULATION AND EXPERIMENTATION
In order to validate the performance of proposed system. A closed loop PV grid tied Z_NPC MLI system has been modeled in MATLAB-SIMULINK environment and a prototype model with 2kW PV tied grid connected Z NPC MLI system has been developed to carried out the experimentation. Experimental setup is shown in Fig.16. of 2-kWp roof-top PV panels (12 serial-parallel panels, each 250W) feeding a 2-kW three-phase 3-level Z-NPC-MLI grid connected system is developed. Xilinx family SPARTAN-6 FPGA controller is used to implement the hysteresis current control based SVPWM control scheme.

A. SIMULATION STUDY
The 2kW PV array modules are configured (series model) to feed the power to inverter with each module rated at 152.5W. The NPC-MLI maintains the dc-link voltage close to 250V using two (C 1 and C 2 ) 470µF capacitors. The inverter is connected to 300V/50 Hz utility grid through 4 mH inductors. The simulation result of the PV is given in the Fig.11. The effects of variation of solar irradiation on PV observed here around 12hr 33min noon. The observed voltage and current in the range of 320V to 400V and 7A to 10.2 A respectively.
The inverter switching frequency (f sw ) is maintained throughout the operation of the inverter as 5 kHz. Initially, the Z-NPC-MLI is simulated and investigated with grid connected system with fixed hysteresis bands. The inverter boosting factor set a 1.6, the inverter output voltage approach to 337V. The Fig.12 shows the inverter line voltages and  phase value of load current for different operating conditions (different modulation index). During every operation instant, the inverter delivers the voltage and current with reduced harmonics in voltage and current. The Fig. 13 illustrates the voltage and current harmonics spectra for the maximum inverter operating point with m a = 0.9. From the THD spectrum results in Fig.13, it is observed that, the inverter output having the nominal voltage THD (6.48%) and current THD (1.16%), due to the control of DC-link voltage, which are in the acceptable range.
The Fig. 14 shows load current responses while varying hysteresis band and change in reference current frequency. From the result, it can see that the load current tracks the reference current. The Fig. 15(a) and 14(b) shows the voltage across DC link capacitors with conventional SVPWM method and HSVM method respectively. It indicates that Neutral point fluctuation (NPF) of conventional SVPWM method is 10.6% where as 1.2% of NPF of proposed HSVM method [22]. Fig.16 shows the transient response of the proposed HSVM. During the change in load at 0.012msec, the HSVM topology has ensured the enhanced boosting factor and meeting out the load voltage and current requirements together with NP balancing.
The Fig. 17 common-mode voltage presented with different modulation indices. From that results it is understood  the common-mode voltage is maintaining as V dc /2 for all modulation index operations.

B. EXPERIMENTAL STUDY
An experimental prototype model of 2-kWp roof-top PV panels (12 serial-parallel panels, each 250W) feeding a 2-kW three-phase 3-level Z-NPC-MLI grid connected system is developed. The complete experimental hardware set up is shown in Fig. 18. In the experiment, The Xilinx family SPARTAN-6 FPGA controller is used to implement the hysteresis current control based SVPWM control scheme. When VOLUME 9, 2021  the inverter is operated under normal PV panel conditions (temperature: 27 • C and Irradiance: 1000 W/m2), the system deliver output of 300V, 50Hz. The MPPT controller maintains a DC-link voltage as 200V. The spectrum analyzer (YOKO-GAWA) is used for capturing the waveforms and harmonics. The performance of proposed HSVM control method such as voltage, current magnitude harmonics and DC link capacitor Neutral point balancing carried out via simulation; at same conditions the experimentation has been carried out and they are validated. When modulation index (m a ) and boosting factor were set as 0.9 and 1.6(as similar specifications are taken in simulation), the inverter delivers output of ≈300V. At aforementioned operating specifications, the inverter is connected to grid and results are verified. The Fig.19 shows inverter current and reference load current waveform along with inverter output voltage. During this operating condition, the HSVM tracks grid reference and controlling the current with better NP balancing with 1.2%. The Fig.20 shows the  three-phase output line voltage and phase current waveforms of the inverter for m a = 0.9 at 5Amps Load. Similarly, Fig.20 and Fig.21 shows the inverter output voltage and current for m a = 0.8 and m a = 0.9. From the results, it is observed that the output current waveform of the inverter is maintained with boosting the voltage. With the current control method, the DC-link capacitor balancing is maintained, which helps to utilize the maximum inverter DC-link voltage with better harmonics profile on inverter voltage and current waveforms.
In order to validate the features such as low current THD and low NPF, the experimentation is carried out for conventional and proposed HCC based SVM. Fig. 22(a) and Fig.22 (b) shows the experimental results of inverter current for conventional and proposed HSVM respectively. Here,   topology. The Fig.23 (a) and Fig.23 (b) shows the experimental results of inverter current harmonics spectra for conventional and proposed HSVM. From the results, the proposed HSVM is having a minimal current THD spectrum as 1.2%, whereas a conventional method current THD spectrum is considerably high (5.4%) compare to HSVM. The Fig. 24 shows the experimental Voltage THD spectra and current THD spectra. By comparing the simulation results of current THD(1.16%), the experimental result of current THD(1.2%) is high due to the non-linear elements selection for Z network (L and C values) in real time.
The Fig. 25 (a) and (b) shows the impedance network capacitor voltages (C 3 and C 4 ) and inductor currents (L 1 and L 2 ) during lower and higher ST duty respectively. In the same operating condition, when m a = 0.9, the inverter DC-link capacitor (C 1 and C 2 ) voltages, V C1 and V C2 are measured and compared for conventional and VOLUME 9, 2021 proposed HSVM and, they are shown in Fig. 26 (a) and Fig.26 (b) respectively. In conventional method, the capacitors voltages (V C1 = 110.6V and V C2 = 90.4V) are fluctuating largely which causes the DC-link (neutral point) unbalancing (the NPF is calculated as 10.6%). This fluctuation causes the higher current THD. However, the proposed HSVM perform with capacitor balancing (V C1 = 101.2V and V C2 = 98.8V) with the NP fluctuation is 1.2%, which helps to utilize the maximum inverter DC-link voltage with better harmonics profile on inverter voltage and current waveforms. Fig. 27 shows the inverter voltage and current with m a = 0.9 at f o = 50Hz.
Based on the experimental results, during the steady state and transient conditions, the proposed HSVM control for Z-NPC MLI has a low value of NPF, and hence, the NP balancing is satisfied. The proposed HSVM can be used for other type of Z-source MLI. The proposed current controller and PWM functioned healthy with inverter and grid differ-   ent operating condition. The observed inverter voltage and current to synchronize with grid is shown in Fig. 28. Here, the current and voltage is maintaining the grid frequency.
The Fig.29 common-mode voltage presented for m a = 0.85. From that results it is understood the commonmode voltage is maintaining as V dc /2. The CVM is maintained for all modulation indices as V dc /2. The European efficiency of the inverter is calculated as 94.6%.

C. COMPARISON OF CONVENTIONAL Z SOURCE SVPWM AND PROPOSED HSVM
The proposed HSVM uses minimal ST compare to conventional Z source SVPWM [8], [11], [13], [14]. In view of the inverter performance, the proposed HSVM is maintaining the I THD (1.2%), and NPF (1.2%) which is very minimal. Comparison of conventional SVPWM and proposed HSVM is presented in Table 3.

V. CONCLUSION
In this paper the three-level Z source NPC-MLI has investigated for PV tied grid connected system. Further also developed the PV tied grid connected system with hysteresis current control combined Z source SVPWM is known as HSVM is developed. The proposed HSVM uses minimal ST compares to conventional Z source SVPWM. In addition the proposed HSVM eliminates the low frequency oscillations using suitable ST (Upper and Lower ST), with regular switching events, which ensures the neutral point DC-link capacitors balancing along with current control. The HSVM maintains the volt-second and inverter voltage boosting competence irrespective of the angular location of the reference vector throughout the inverter operation. A 2 kWp solar panels attached three-phase three-level IGBT based Z-NPC-MLI grid connected system is established with Xilinx family FPGA SPARTAN-6 controller. From the results, it shows that the performance of proposed method is superior than compare to conventional Z source SVPWM in terms of Neutral point fluctuation, current control capability and better harmonic performance. This proposed HSVM method well suited for wind tied inverters, industrial and Electrical vehicles motor applications.