A Class-E-Based Resonant AC-DC Converter With Inherent PFC Capability

This paper investigates the use of the class-E inverter for power factor correction (PFC) applications. Analytical and state-space models are derived showing the class-E inverter’s capability of achieving inherent PFC operation with a constant duty cycle. The inherent PFC operation limits the controller responsibility to the regulation of the output voltage, which is key for resonant converters with challenging control. A converter incorporating a diode bridge, a class-E inverter, and a class-D rectifier is presented for the PFC stage in single-phase offline converters. A prototype is designed to validate the analysis and presented design method. The prototype operates with zero-voltage switching (ZVS) across the load range and achieves up to 211 W of output power at an efficiency of 88%, with an inherent power factor of 0.99 and a total harmonic distortion (THD) of 8.8 %. Frequency modulation is used to achieve lower output power down to 25 W, with a power factor of 0.95, THD of 28 %, and an efficiency of 88 %.


I. INTRODUCTION
Large-scale deployment of switch-mode power supplies to the utility introduces line current harmonics. The injected current harmonics result in voltage distortion and reduce the reliability of the grid [1], [2]. As a result, several international standards expressly limit the magnitudes of input current harmonics and set a limit for the minimum power factor. Thus, a power factor correction (PFC) converter needs to be employed in offline converters for different applications to comply with these standards.
The typical solution for offline converters is a two-stage structure that is illustrated in Fig. 1. A front-end stage ac-dc PFC converter rectifies the ac line voltage to a relatively smooth dc voltage while regulating the input current to follow the ac line voltage. A following dc-link capacitor filters the double-the-line frequency component. Finally, a dc-dc converter provides the current and voltage levels that apply to the load. This work's focus is on the PFC front-end stage of the offline converter.
The associate editor coordinating the review of this manuscript and approving it for publication was Tariq Masood .
Resonant converters operation is based on soft switching, which results in substantially lower switching losses and EMI noise at higher switching frequencies [18], [19]. The soft-switching nature has been previously studied in class-E inverter [20] and class-D inverter [21]. As a result, resonant converters have been investigated for use in many applications, one of which is offline converters, where prior art reported their use in the ac-dc stage [22]- [25], dc-dc stage [26]- [29], or both stages [30]- [32].
This paper investigates the feasibility of employing the class-E inverter for the PFC stage in single-phase offline  converters [33]. Mathematical models are derived for the circuit showing inherent PFC capability with a constant duty-cycle operation. A converter comprising an input bridge, a class-E inverter, and a class-D rectifier is presented. Fig. 2 shows the proposed converter block diagram. The converter operation is based on zero-voltage switching (ZVS) and achieves PFC inherently. The inherent PFC operation limits the controller responsibility to the regulation of the output voltage, which is key for resonant converters with challenging control. At the same time, the soft-switching operation enables the design of PFC converters with high switching frequencies and power densities. This paper is organized as follows: Section II describes the principle of operation of the presented converter. Mathematical models based on analytical and state-space approaches are covered in Section III. Section IV presents the design procedure. Prototype implementation and experimental verification results are illustrated in Section V. Finally, conclusion is provided in Section VI.

II. PRINCIPLE OF OPERATION
The schematic of the presented converter is shown in Fig. 3, which comprises a front-end diode bridge rectifier D 1 -D 4 , a class-E inverter, and a class-D current-driven rectifier. The diode bridge rectifies the ac input voltage. A capacitor C in is connected in parallel with the bridge to suppress the EMI and absorb the reverse current from the inverter. A class-E ZVS inverter drives the resonant tank with a current i r (t), where the shape of the waveform depends on the loaded quality factor of the tank Q L and the duty-cycle D. A class-D rectifier converts the high-frequency current into a dc output voltage V o , where the voltage stress across the rectifier diodes equals the output voltage.
Considering that the switching frequency f s is much higher than the line frequency f l , the input voltage to the inverter v rec (t) is assumed constant across the switching  cycle. With a high-enough quality factor for the resonant tank, the first-harmonic approximation (FHA) approach for modeling resonant converters is valid, and the resonant current is a sinewave with the form where I r is the current amplitude, θ s = ω s t is the current angle across the switching cycle, and φ is the phase shift with the switching node voltage. The switching cycle is divided into four intervals, as shown in Fig. 4, with the corresponding voltage and current waveforms illustrated in Fig. 5, including the voltage across the switch gate v g (t), the drain-source voltage of the switch, i.e. switching node voltage v s (t), the inverter input current i in (t), the resonant current i r (t), and the diodes currents i D5 (t) and i D6 (t).  In interval I (t 0t 1 ), the switch is on and the rectified voltage v rec (t) is higher than v s (t), thus the input current i in (t) increases linearly, charging the input inductor L in . The resonant current is positive and flows in D 6 , while D 5 is in reverse bias. Accordingly, the current flowing through the switch is the difference between i in (t) and i r (t).
In interval II (t 1t 2 ), the switch is still on, and the input current i in (t) keeps charging the input inductor L in , while the resonant current reverses its direction and flows in D 5 with D 6 in reverse bias.
In interval III (t 2t 4 ), the switch is turned off and the capacitor C s starts charging with the input current. Thus, v s (t) begins to increase, yet it is still less than the v rec (t). As a result, i in (t) keeps increasing until it reaches its maximum at t 3 when v rec (t) equals v s (t). Afterwards, the input inductor L in starts discharging in the capacitor C s , resulting in increasing of the voltage stress across the switch to its maximum value by the end of this interval.
In interval IV (t 4 -T ), the switch is still turned off, the resonant current reverses its direction, turning D 5 off and D 6 on. The capacitor C s starts discharging, and the switch voltage reduces until v rec (t) equals v s (t) at t 5 , with the inductor L in discharging as v rec (t) < v s (t). From t 5 to the end of the interval, the inductor L in is charging, and the capacitor C s continues discharging until full depletion. By the end of this interval, the switch is turned on by the gate driver, and a new cycle begins.
If the switching frequency is higher than the resonant frequency f o of the series-resonant tank (L r -C r ), the tank and rectifier represent an inductive load and ZVS can be achieved. That is shown in Fig. 5 where the switch turns on at zero voltage, with a negative current in the resonant tank. By modulating the switching frequency f s with respect to the resonant frequency f o , the converter gain changes and accordingly the output power is modulated. The choice of the duty cycle affects ZVS operation as well as the stress on the switch. Theoretically, the switch voltage stress in a class-E inverter reaches about 3.6 times the input voltage with 50 % duty cycle [34]. However, in practice, this stress could reach more than four times the input voltage due to the nonlinearity of the switch node capacitance C s [35], [36]. Accordingly, this topology is more suited for low-input-voltage applications.

III. MATHEMATICAL MODELLING
In this section, the mathematical models for the class-E inverter are investigated with respect to the input impedance. The conventional analytical and state-space approaches are considered. In the former approach, the design procedure derives the equations from the waveforms, while the latter is based on the basic circuit equations from Ohm's and Kirchhoff's laws. The principle of operation of the class-E rectifier as an input current shaping stage explained in [31], [32] is adopted in this work.

A. ANALYTICAL APPROACH
The analysis of the proposed topology is carried out across the switching cycle and using the approach given in [34], which assumes an ideal semiconductor switch and a high-enough input inductance such that the dc component of the input current I in is only considered. From the principle of operation given in Section II and the V s waveform in Fig. 5, the capacitor C s current can be written as follows The voltage across the switch is then calculated where θ is the variable of integration. Under optimal operation conditions, where ZVS is achieved, the voltage across the switch equals zero by the end of the switching period. Substituting θ s = 2π in (3) and equating to zero, the following expression for the resonant current amplitude is derived.
Considering zero-derivative voltage switching (ZdVS, dv s (2π)/dφ = 0) is also achieved, taking the derivative for (3) with θ s = 2π and equating to zero, the following expressions for the phase shift φ is derived.
It can be seen that φ is a function of the duty cycle D. Following, the rectified voltage can be written as follows As the average voltage across the input inductor is zero, eliminating the first term and substituting (3) in (6) then evaluating the integration gives Dividing (7) by I in gives the following expression for the input resistance.
Since (8) is a function of the duty cycle D and phase shift φ, which is itself a function of duty cycle as shown by (5), then operating with a constant duty cycle results in a constant input resistance that is independent of line changes. As a result, the converter is seen as a resistor from the input across the line cycle and power factor correction is achieved.

B. STATE-SPACE APPROACH
While the analytical approach assumes an ideal switching device and a sinusoidal resonant current to ensure the validity of the FHA approach, in the state-space approach, the design parameters are computed numerically. The state-space approach is used in prior art [37]- [39] to design class-E dc-dc converters with any loaded quality factor of the resonant tank and any size for the input inductor. Accordingly, it is considered in this section for flexibility across different designs. By adding the switch on-resistance to the model, the switch is replaced with a resistor as follows where r on and r off are the equivalent resistances of the switch in on-and off-states, respectively. The circuit has four energy storage components (L in , L r , C s and C r ), which define the dimension of the state vector. The following expressions are obtained by applying Kirchhoff voltage and current laws.
where v C r (θ s ) is the voltage across the resonant tank capacitor C r and R eff is the class-D rectifier effective resistance. By normalizing the impedance in (10) with the effective resistances, it can be rearranged and rewritten in the following matrix forṁ where x is the state vector, A is the system matrix, B is the control matrix, and u is the input vector. From (11), the number of parameters is nine, i.e. ω s , D, Q L , L in , L r , C r , C s , R eff , r s ∈ R 9 , and the solution of the equation is where x n (θ s ) is the natural response of the system and x f (θ s ) is the forced response. These two terms can be calculated as follows [40].
where e Aθ s is the exponential matrix, x(0 − ) is the initial condition vector, and I is the identity matrix, while the currents are normalized with the input current and the voltages are normalized with the input voltage. Since the waveforms are continuous and periodic, the initial conditions can be found by applying the continuity condition of the waveforms such that Substituting (12)- (14) in (11) gives where A on and A off are the system matrices in (11) when r s is equal to r on and r off , respectively. Under optimal operation conditions, where ZVS and ZdVS are achieved, (15) can be re-evaluated and solved numerically using the Matlab fsolve solver. However, there are nine parameters and two optimum operation conditions. Therefore, ω s , D, Q L , L in , L r , R eff , r s ∈ R 7 are chosen as the design parameters, while C r and C s are solved as unknown parameters.
Since (11) is in the form of a first-order differential equation, the solution with oscillating input can also be written as where M and N are solution parameters that are found from the initial conditions, θ l = ω l t is the input current angle across the line cycle, G is the gain vector, and α is the phase shift matrix. Equation (16a) mathematically shows that the response of the system, i in (θ l ) which is the main interest, to the oscillating input voltage has the same frequency of the input and phase-shifted by α. From (16c), it can be proven that the input current is in phase with the input voltage (i.e. α ≈ 0), and hence the converter emulates a resistor.

IV. CONVERTER DESIGN
This section describes the design procedure of the presented converter. Table 1 summarizes the converter design specifications. The converter is designed to operate from US mains input voltage for a rated output power of 300 W and an output voltage of 200 V. A 90-kHz switching frequency is chosen for this design which is intended to prove the analysis and inherent PFC capability. Fig. 6 shows the normalized switches voltage and current stresses with respect to the input voltage and current. A duty cycle of 40 % is chosen for minimal stress on the switch. In the analytical approach, the design procedure based on the FHA approach and given in [34] is followed in this paper. To ensure the validity of the FHA approach, a high-quality factor of seven is chosen for this design. The procedure begins with the calculation of the class-D rectifier effective input resistance.
where R L is the load resistance, V o is the output voltage, and P o is the output power. The phase angle of the resonant current can be written as The capacitor C s is calculated from (19), as shown at the bottom of the next page. The switching frequency is chosen to be higher than the resonant frequency such that the net impedance of the tank is inductive. The inductor L r can be divided into two series inductances, such that L r1 resonates with the capacitor C r at the switching frequency, while L r2 is responsible for the phase lagging shown in (18) and can be calculated from (20), as shown at the bottom of the next page. Then, the resonant capacitor can be found as follows The input inductance Lin should be large enough to ensure a small ripple current through the choke (10 % of dc current), and calculated as follows.
Regarding the output capacitor C f , it needs to be large enough to filter the double-the-line frequency in single-phase PFC applications, and is calculated from the following expression, with η being the efficiency, and ω l being the angular line frequency [32].
The state-space approach is carried out numerically in MAT-LAB. Table 2 lists the calculated values of the components from both models. It can be observed that the values obtained from both models are highly correlated.

V. PROTOTYPE IMPLEMENTATION AND EXPERIMENTAL VERIFICATION
This section covers the implementation of a prototype built based on the analysis and design procedure. Experimental results are then presented and discussed.

A. IMPLEMENTATION
The prototype of the proposed topology is assembled on a two-layer PCB. Fig. 7 shows a picture of the prototype, and Table 3 lists the bill of materials based on the parameters obtained from the design procedure given in Section IV. Compared with silicon devices, wide-bandgap devices have reduced reverse-recovery charge and better figures of merit [41]- [43]. Considering the high voltage stress across the switch, a silicon carbide (SiC) device is more suited for this application than a gallium nitride (GaN) device, as the breakdown voltage limit for commercially available GaN devices is 650 V. Cascode GaN device structures offer higher breakdown voltages up to 900 V, yet that comes with higher on-resistance than otherwise offered by SiC devices, which is a key parameter for soft-switching topologies. The C3M0075120D device by Cree/Wolfspeed is chosen and is driven using a single-channel isolated gate driver (UCC5350SBD by Texas Instruments). From (22), a minimum value for the input choke of 205 µH is needed to guarantee a small ripple on the input current and ensure the validity of the analytical approach equations, where a larger value of 1.3 mH is chosen to help reduce EMI and core loss, and it does not affect the converter operation. Fig. 8 shows the testing lab setup. The converter is tested from US-mains input voltage, delivering up to 211 W of power at 89.5 kHz and 55 % duty cycle, where thermal considerations limited the delivery for the specified output power. Fig. 9 shows the line-frequency waveforms at 211 W load. The input and output voltages are measured using high-voltage differential probes (LeCroy ADP305 and Testec SI 9001), and the current is displayed using a clamp-on current probe (Siemens 7KA1412-8AA). The figure shows the input current to be proportional to the input voltage, with a minor phase difference, achieving a power factor of 0.99 inherently. The dashed waveform is the input current filtered by the moving-average function in MATLAB and shown for clarity.     10 shows the switching-frequency waveforms at 211 W. The resonant current has a sinusoidal waveform, which goes in accordance with the analysis and design procedure based on the FHA approach, and it is about 15 A peak-to-peak. While the input current in the inductor L in is mainly a dc component with 0.4 A peak-to-peak ripple. The figure illustrates the inductive mode of operation, where the resonant current lags the switch node voltage and the switch voltage returns to zero before the switch is turned on, achieving ZVS.

B. EXPERIMENTAL RESULTS
A short interval of reverse conduction of the FET is observed, where the switch-node capacitance is fully depleted before the switch turns on. However, with the reduced reverse recovery charge in SiC devices, the contribution of reverse conduction to the overall power loss is insignificant and can be eliminated with the precise adjustment of the switch driving signal duty cycle. Fig. 11 and 12 show the line-frequency and switchingfrequency waveforms at 25 W. The figures show that a high-power factor is still achieved at the light load, where the ZVS operation is maintained through the adjustment of the switch duty cycle. Fig. 13 shows the obtained efficiency and employed switching frequency across the load range. The results show that the output power can be regulated from 211 W down to 25 W with switching frequency modulation between 89.5 kHz to 104.3 kHz, respectively. The peak obtained efficiency is 88.3 % at 90 W with 96 kHz and a duty cycle of 0.5. The small dips in the efficiency curve are attributed to the partial loss of ZVS, which is corrected by adjusting the duty cycle. For lower output power down to 0 W (e.g. dimming   functionality in LED driver applications), the overall converter can be switched on/off with a low-frequency PWM signal in a burst-mode control fashion. That helps limit the maximum switching frequency of the converter and achieve high efficiency at light loads.
The power quality results are shown in Fig. 14, where a power factor of 0.99 and a total harmonic distortion (THD) of 8.8 % are achieved at full load, while the minimum power factor is 0.95 at 25 W with a THD of 28 %. The harmonic spectra of the input current at the 211 W and 25 W are illustrated in Fig. 15. Fig. 16 shows the power loss breakdown at full load operation. The currents of the different components are obtained from experimental and simulation results, and the loss is calculated based on parameters from the devices datasheets. It can be seen that 26 % of the overall loss is incurred as conduction losses in the switch, whereas 22 % of loss is dissipated in the resonant inductor, while 30 % is lost in the rectifier diodes and 16 % in the bridge, which goes in   accordance with the thermal pictures in Fig. 7. By improving the resonant inductor implementation and the choice of rectifier diodes and bridge, higher efficiency can be achieved. Table 4 compares the proposed work with a number of reported solutions for PFC applications for the low-mid power range. It can be observed that the obtained power factor and THD figures fall within the ranges reported by prior art. In addition, the proposed converter achieves PFC inherently across a wide load range. That provides freedom from the limited bandwidths of commercial PFC controllers and simplifies control requirements. In terms of cost, the proposed solution offers a relatively low number of components, with a single switch, two diodes (in addition to the input bridge) and two magnetic devices. The switch is referenced to ground, with a simple driving circuitry. In comparison with the work in [13], which is also designed to operate from 120 V rms and delivers about the same output power, the proposed converter has a lower efficiency, yet offers a higher power factor and lower THD, with reduced component count and lower cost. VOLUME 9, 2021 Compared with the reported resonant PFC converters, the proposed solution does not require any additional circuit or matching network, which reduces the overall system bill of materials. In addition, as the topology features an input inductor, it requires a simpler input filter and diode bridge implementations, where the input current is not pulsating as in the case of [23].
It is noted that the proposed converter's efficiency is lower than that reported by PWM converters, yet it is on par with several reported resonant converter solutions. Similar to most of the reported solutions, the proposed topology is compatible with universal input mains, as the analysis and modeling results are valid for any input voltage in the range of 85-265 V rms , and inherent PFC functionality is achieved. With respect to the prototype, the switch circuit needs to be designed for the worst-case conditions, which comes with the higher input voltage. In addition, in order to ensure the validity of the FHA equations by operation near-resonance, the output voltage will change across the range of the input rms voltage. That will require the subsequent dc-dc stage to have a wide-input line regulation capability.
As the target of the presented prototype is to demonstrate the inherent PFC capability, there is a space for improvement with an optimized high-frequency design that takes benefit of the ZVS capabilities of the proposed work towards highpower-density implementations with higher efficiencies.

VI. CONCLUSION
This paper investigates the use of the class-E inverter for PFC applications. The circuit analytical model proves that the converter emulates a resistance to the input when operating with a constant duty cycle. That is asserted from the obtained state-space model, where the phase shift between the input current and voltage is shown to equal almost zero. A resonant converter incorporating a class-E inverter with a class-D rectifier is designed for the front-end ac-dc stage in a two-stage offline converter. The inherent PFC operation limits the controller responsibility to the regulation of the output voltage, which is key for resonant converters with challenging control. A prototype is built and tested to prove the concept. The prototype achieves zero-voltage switching and inherent PFC along the load range between 25 W and 211 W, with a peak efficiency of 88 %, a peak power factor of 0.99 and a minimum THD of 8.8 % at full load.