Analysis and Suppression of High Speed Dv/Dt Induced False Turn-on in GaN HEMT Phase-Leg Topology

Gallium nitride high electron mobility transistor (GaN HEMT) is liable to gate false turn-on problem when the gate crosstalk voltage exceeds its threshold voltage in the widely adopted phase-leg topology due to its low threshold voltage and high switching speed. Without considering the gate loop stray inductance, gate internal resistance, nonlinearity of parasitic capacitances and power loop stray parameters, traditional false turn-on analytical method is insufficient to support accurate analysis. And it has been found that GaN HEMT gate-source parasitic capacitance <inline-formula> <tex-math notation="LaTeX">$C_{\mathrm {gs}}$ </tex-math></inline-formula> previously assumed constant is otherwise highly nonlinear and has strong impacts on the gate crosstalk voltage. This paper has measured <inline-formula> <tex-math notation="LaTeX">$C_{\mathrm {gs}}$ </tex-math></inline-formula> by vector network analyzer and constructed an accurate nonlinear model of <inline-formula> <tex-math notation="LaTeX">$C_{\mathrm {gs}}$ </tex-math></inline-formula>, based on which an accurate GaN HEMT behavior model is further fulfilled. The accuracy of the proposed behavior model has been verified by large amounts of experiment results. The proposed GaN HEMT model is used to accurately calculate gate crosstalk voltage and switching losses. Besides, false turn-on induced extra loss has been calculated and is adopted as a criterion to evaluate the severity of false turn-on and optimal design method for false turn-on suppression has been detailed further.


I. INTRODUCTION
Gallium nitride high electron mobility transistor (GaN HEMT) with the merits of high switching speed, low switching and conduction loss and small package size is becoming more and more prevalent in recent years [1], [2]. However, GaN HEMT is liable to false turn-on problem when the gate crosstalk voltage exceeds its threshold voltage in the commonly used phase-leg topology because of low gate threshold voltage and fast switching speed [3]- [5]. In order to avoid false turn-on induced extra switching loss and increase the stability of the power converter, false turn-on problem must be analyzed and suppressed thoroughly.
The associate editor coordinating the review of this manuscript and approving it for publication was N. Prabaharan . By far, some methods have been proposed to address false turn-on problems, and they can be classified into three types. The first type is trying to eliminate the intensity of exciting source that induces gate crosstalk voltage, among which the simplest way is to slow down the turn-on speed of GaN HEMT with large turn-on resistance, but it will increase the overlap loss during the turn-on transient [4]- [7]. By contrast, minimizing the power loop stray inductance by optimized layout and routing or deliberately designed snubber circuit seems more feasible [8]- [10]. Based on the mechanism analysis of crosstalk, the second type of false turn-on suppression method focuses on minimizing the impedance of gate turn-off loop [10]- [13]. Using a small turn-off resistance in the gate turn-off loop by adopting gate drivers with split turn-on and turn-off pins as presented in [10] is widely adopted.
Besides, the area enclosed by the gate turn-off loop is recommended to be as small as possible to minimize the stray inductance and possible EMI noise. While, gate turn-off loop resistance should be deliberately designed to avoid oscillation in the existence of gate turn-off loop stray inductance. Besides, unreasonably small gate turn-off resistance may also induce serious turn-off overvoltage. A programmable active gate driver has been proposed in [11] and it can suppress the crosstalk voltage by dynamically controlling the turn-on speed and gate turn-off impedance without the penalty of extra switching losses. While the control sequence of the active gate driver is very complex and it's not commercially available yet. The last type of false turn-on suppression method is by adopting negative turn-off voltage as proposed in [14]- [17]. This is a very reliable false turn-on suppression method but with the penalty of driving complexity and extra reverse conduction loss.
Though so much false turn-on suppression method, quantitative method for practical usage is still absent. Traditional analytical methods addressing false turn-on problem are mostly applicable to silicon power devices without taken the gate loop inductance and nonlinearity of device parasitic capacitances into account as in [14]- [16]. Thus, they are not accurate enough for the analysis of GaN HEMT. Paper [18] has proposed an analytical model for GaN HEMT false turn-on analysis. However, the nonlinearity of parasitic capacitances is not considered. Besides, the modeling accuracy of false turn-on excitation signal is not guaranteed either. An accurate GaN HEMT device model has been proposed in [19], based on which effects of different parameters have on false turn-on voltage has been analyzed. However, the proposed device model in [19] is too complex for practical usage and the model parameter extraction method is also absent. In addition, the modeling and solving of false turn-on analytical circuit model is also a labor-intensive work. Paper [20] has proposed a GaN HEMT false turn-on analytical model. However, the nonlinearity of device gate-source capacitance has not been taken into consideration and modeling false turn-on excitation signal with a simple ramp function is not accurate enough.
Aiming at these issues, this paper has constructed an accurate behavior model of GaN HEMT with the modeling accuracy of gate-source capacitance enhanced, based on which a precise false turn-on analysis model is constructed further. At the basis of the proposed analytical model, the effects that different parameters have on crosstalk voltage can be accurately calculated. False turn-on induced extra turn-on loss has been adopted as a criterion to evaluate the seriousness of false turn-on and the effectiveness of false turn-on suppression method. Optimal design method for false turn-on suppression has been presented further. The paper is arranged as following: Section I gives an introduction to the pervasive crosstalk and false turn-on problems. The mechanism and analytical model of gate crosstalk and false turn-on is detailed in section II, based on which a quantitative parametric analysis has been conducted to illustrate the negative effect that gate turn-off loop impedance has on false turn-on problem. Nonlinear models of parasitic capacitances are also detailed in this section. To promote the accuracy of the calculated false turn-on voltage, an accurate GaN HEMT behavior model is constructed and verified in section III. Based on the proposed device model, optimal design methods for false turn-on suppression are detailed in Section IV. Conclusions are given in section V.

II. FALSE TURN-ON ANALYTICAL CIRCUIT MODEL
The mechanism of gate false turn-on in a GaN HEMT phase-leg topology is illustrated in Figure 1. When bottom GaN Q 2 hard switches on, there will be a steep positive voltage pulse occurring on the drain-source terminal of top GaN Q 1 , and vice versa. Owing to the existence of miller capacitance C gd , there will be displacement current flowing through C gd to gate-source capacitance C gs and gate turn-off loop, which will result in crosstalk voltage at the gate of GaN Q 1 at off state. Once the induced gate-source crosstalk voltage surpasses the intrinsic low threshold voltage of GaN, false turn-on will be triggered unfortunately.

A. CONSTRUCTION OF CIRCUIT MODEL
Gate false turn-on problem is not specific to GaN HEMT. It's also common to traditional silicon and wide band-gap SiC power devices. While traditional methods have overlooked the influence that gate turn-off loop stray inductance has on crosstalk voltage. Aiming at this problem, an analytical circuit model is constructed to quantitatively calculated the crosstalk voltage with gate turn-off loop stray inductance taken into account as illustrated in Figure 2.
R goff and L goff shown in Figure 2 represent gate turn-off loop resistance and stray inductance respectively. For the sake of simplicity, drain-source voltage V ds is modeled with a ramp function where drain-source voltage increases from zero to DC-link voltage V dc in time interval T r . The s-domain model of V ds is given in equation (1). According to Figure 2, gate-source voltage V gs in the s-domain is represented in equation (2) as where C iss represents the input capacitance and is the sum of C gs and C gd . To get an analytical solution of crosstalk voltage, C gs and C gd are assumed to be constant first. According to equation (1) and (2), V gs in the time-domain is given as Defining ζ represents the damper factor of the second order system shown in Fig. 3. When ζ is less than one, the system is an under-damped system. Then f (t) and g(t) is represented as Attenuation factor α and angular frequency ω in equation (4) and (5) are given in formula (6) and (7) respectively as However, when ζ is greater than one, the system is an over-damped system. Then f (t) and g(t) are represented as Angular frequency in equation (8) and (9) is different accordingly and is given as

B. PARAMETRIC ANALYSIS
As can be seen from equation (3) that time-domain V gs expression is a complicated function of excitation and other circuit parameters. However, the effects that electrical parameters have on the gate crosstalk can be revealed by means of parametric analysis. Circuit parameters used for parametric analysis are listed in Table 1, in which GaN device related parameters come from the datasheet of GS61008P manufactured by GaN Systems corporation. According to the deduced solutions of the analytical circuit model in equations (3)∼(9) and parameters given in Table. I, the gate-source crosstalk voltage can be calculated out under different combination of R goff and L goff as shown in Figure 3.
In Figure 3, each solid line represents the maximal gatesource crosstalk voltage contour and each dashed line represents the contour of minimal gate-source voltage during the crosstalk induced gate ringing period. The red dash dot line shown in Figure 3 illustrates the underdamped and overdamped boundary determined by the circuit parameters. From Figure 3 the following conclusion can be drawn: (1) There is no need to design the gate turn-off loop as an overdamped system. Though large turn-off resistance can suppress the minimum gate-source voltage undershoot in the ringing period, it will increase the possibility of gate false turn-on.
(2) Gate turn-off loop inductance has detrimental effects on the gate crosstalk overshoot and the accompanying ringing effect. So it's important to optimize the layout and routing of gate turn-off loop to minimize the gate turn-off loop inductance.  (3) For a given power semiconductor, the gate threshold voltage is known. Under a given or an estimated dV ds /dt excitation, the combination of R goff and L goff that prevent false turn-on can be figured out by parametric analysis as illustrated in Figure 3. For GaN GS61008P, the gate minimal threshold voltage is 1.1V. If assuming the analytical circuit model is accurate, then the area encircled by the calculated 1.1V gate-source crosstalk voltage curve AB and the coordinate axes determinates all the safe combinations of R goff and L goff .
Though has taken gate turn-off loop inductance into consideration, the calculated gate crosstalk voltages still divert from the experiment measurement results. Thus, for accurate gate crosstalk voltage calculation, the modeling accuracy of nonlinear parasitic capacitances and crosstalk excitation signal has to be promoted.

C. NONLINEAR SIMULATION MODEL OF FALSE TURN-ON PROBLEM
In this section, nonlinear parasitic capacitances of GaN HEMT are modeled first, then more precise gate crosstalk voltage can be calculated. Parasitic capacitance C gd is a nonlinear function of drain-source voltage V ds as widely illustrated in the device datasheets. Here, C gd is modeled by equation (11) as where, k 0 ∼ k 4 are fitting parameters. The nonlinearity of capacitance C gs is liable to be omitted, because C gs given in device datasheet keeps almost constant as varying of V ds . While it has been found that C gs is a highly nonlinear function of gate-source voltage V gs and the nonlinearity of C gs has a serious effect on the gate crosstalk voltage. Here, vector network analyzer E5061B with dc bias capacity is adopted to measure the gate-source impedance of GS61008P under different gate-source offset voltage. According to the measured gate-source impedance, the extracted C gs is illustrated in Figure 4.  Equation (12) below is proposed to model nonlinear capacitance C gs and the accuracy of the modeling equation has been verified by the fitting result as shown in Figure 4.
In equation (12), a 0 ∼ a 5 are fitting parameters. All the fitting parameters shown in equation (11) and (12) are listed in Table 2.
The nonlinear capacitance models (11) and (12) are implemented in the Matlab/Simulink as illustrated in Figure 5(a), where the nonlinear capacitance is modeled with a controlled voltage source and the initial voltage of the capacitance can be set by initializing the value of the integrator.
With the implementation of the nonlinear parasitic capacitance model, a more precise false turn-on voltage simulation circuit model is derived as shown in Fig. 5(b). To promote the accuracy of the simulation result, gate internal parasitic resistance R gint has also been considered in Figure 5(b).

D. NONLINEAR FALSE TURN-ON SIMULATION MODEL VERIFICATION
To verify the correctness of the proposed nonlinear simulation model of false turn-on problem, a GaN HEMT based half-bridge test board has been designed and the corresponding circuit diagram is same as that shown in Figure 1. A double pulse test has been carried out on the experiment board.
By using Ansys Q3D, the gate turn-off inductance is extracted to be 3.6nH, and other experiment circuit parameters are listed in Table 3. Experiment measured drain-source voltage rise time T r and gate crosstalk voltages V gs of the top GaN HEMT under different gate turn-off resistances are listed in Table 3. According to the measured V ds rise time T r in Table 3, gate-source crosstalk voltages of top GaN can be calculated as shown in Table 3 based on the constructed simulation model in Figure 5(b).
From Table 3, it can be seen that the simulated gate crosstalk voltages are close to the measurement results, which proves that the proposed nonlinear simulation model can be used to calculate the gate crosstalk voltage accurately under given gate turn-off loop inductance and drain-source voltage rise speed. Besides, proper gate turn-off voltage can be chosen to prevent the happening of false turn-on accordingly.

III. GAN HEMT ACCURATE BEHAVIOR MODEL BASED FALSE TURN-ON PROBLEM ANALYSIS
Though the false turn-on analysis nonlinear model proposed in section II.C can be used to accurately calculate the crosstalk gate-source voltage, it works only when the drainsource voltage rising time is known. However, in practical design, drain-source voltage rising time can't be estimated in advance, which makes the nonlinear model not applicable for practical usage. To solve this problem, an accurate GaN HEMT behavior model is proposed in this section and a device model based false turn-on problem analysis method is detailed further.

A. CONSTRUCTION OF ACCURATE GAN HEMT BEHAVIOR MODEL
The subcircuit of the proposed model is shown in Figure 6. The model composes of a controlled current source I ds used to describe the static behavior of GaN HEMT in both the first and the third quadrants. As an electrothermal model, terminal T j and T c shown in Figure 6 represent the junction temperature and case temperature respectively. Loss power of GaN HEMT can be calculated by the product of drain-source voltage and channel current at the simulation runtime.
Thermal resistance and thermal capacitance boxed by dashed line as shown in Figure 6 represent the internal package thermal impedance network. T j and T c are connected to loss power and thermal impedance network, and they can be used to simulate the junction and case temperatures under different working and cooling conditions by externally adding thermal sources or thermal impedance to these two  Figure 6 are drain, gate and source pin respectively. R g(int) is the gate internal resistance. C gs , C gd and C ds are the parasitic capacitances used to model the dynamic characteristics of GaN HEMT. Due to the compact package of GaN HEMT, parasitic inductances are not considered in this paper. While, if needed, they can be extracted out by impedance analyzer measurement as conducted in [21]. Besides, it has to point out that the common source inductance coupling the gate and power loop together has complex effects on the crosstalk voltage. On the one hand, common source inductance has different effects at the different stages during the turn-on process as detailed in [22]. Thus, common source inductance affects the turn-on speed and the corresponding drainsource voltage rising speed that exciting cross talk voltage. On the other hand, common source inductance enclosed in the gate and power loop where crosstalk occurs also increases the calculation complexity of crosstalk voltage. Fortunately, to GaN HEMT, there is a source sense (SS) terminal for gate driver, which can minimize the common source inductance. Moreover, if needed, the effect that common source inductance has on crosstalk voltage can be figured out by adopting the proposed GaN HEMT behavior model below.

pins. Terminals D, G and S shown in
The equation used to model the electrothermal output characteristics of GaN HEMT in the first quadrant is given as where a 1 ∼ a 9 are fitting parameters. The electrothermal output characteristics of GaN HEMT in the third quadrant VOLUME 9, 2021  can be accurately modeled as in equation (14) I where b 1 ∼ b 9 are also fitting parameters. In this paper, output characteristics data is extracted from the datasheet of GS61008P first, then commercial optimization tool 1stopt in [23] is adopted to fulfil the parameter fitting process as listed in Table 4.
According to modeling equations (12), (13) and the fitted model parameters, the transfer and output characteristics of GS61008P under different junction temperature can be calculated out as illustrated in Figure 7.
From Figure 7, it can be seen that the electrothermal output characteristics of GS61008P in both the first and the third quadrant can be precisely modeled by the proposed modeling equations.
As to the modeling of nonlinear parasitic capacitances, the models of capacitance C gs and C gd have been constructed in section II.C. At the same time, the modeling equation of capacitance C gd is also applicable for the modeling of capacitance C ds . Modeling parameters of GS61008P C ds are listed in Table 5.
According to the modeling parameters given in Table 2 and  Table 5, the parasitic capacitances of GS61008P as function of V ds are illustrated in Figure 8.
From Figure 8, it can be seen that the nonlinear parasitic capacitance can be precisely modeled by the proposed modeling equations.

B. EXPERIMENT VERIFICATION AND DISCUSSION
To verify the correctness of the proposed GaN HEMT model, a half-bridge test board is designed as shown in Figure 9.
The circuit diagram corresponding to Figure 9 is the same as Figure 1. A double pulse test is carried out on the experiment board, where the current of the load inductor is charged to a preset value during the first turn-on period of the bottom GaN HEMT and gate crosstalk voltage of the top GaN HEMT will be triggered during the hard turn-on process of the bottom GaN HEMT at the beginning of the second turnon pulse. By adopting Ansys Q3D, the top/bottom gate loop turn on/off inductances and power loop inductance can be extracted as listed in Table 6. In addition, unless otherwise stated, the default electrical parameters in the experiment are also listed in Table 6.  According to the electrical parameters in Table 6 and the constructed GaN HEMT device model, the double pulse test virtual prototype can be constructed in simulation program for integrated circuits emphasis (SPICE) simulator LTspice. To verify the correctness of the constructed virtual prototype, comparisons between the experiment measured and simulated dynamic switching waveforms during bottom GaN hard turn-on period under different top GaN gate turn-off voltages are illustrated in Figure 10∼Figure 12.
In Figure 10∼Figure 12, V dsi , I dsi and V gsi (i = 1, 2) represent the drain-source voltage, drain-source current and gate-source current of the top GaN when i equals 1 and the bottom GaN when i equals 2. V gs1(int) represents the internal gate-source voltage of the top GaN without considering the voltage drop on the internal gate resistance, and I ch1 represents the channel current of top GaN obtained by SPICE simulation. Before the turn-on of bottom GaN Q 2 , top GaN Q 1 free-wheels the load current. So the channel current of Q 1 is negative at first. As the switching on of bottom GaN Q 2 , the drain-source voltage of Q 1 rises up sharply, which evokes displacement current flowing through C gd of Q 1 and consequent crosstalk voltage. From Figure 10∼Figure 12, it can be seen that (1) The virtual prototype based dynamic switching waveforms match the experiment measurement results quite well, which can effectively verify the correctness of the constructed device model, extracted parasitic parameters and circuit models. Besides, it also means that the virtual prototype can be   used to calculate the crosstalk voltage and further facilitate the analysis of false turn-on problem.
(2) Based on the simulation model, the gate internal crosstalk voltages and channel current which are not measurable by experiment can be calculated, and this is valuable to determine the occurrence and seriousness of false turn-on. At the same time, in Figure 10∼Figure 12, the gate internal crosstalk voltages are larger than the measured, which shows that it's more reliable to determine whether false turn-on has happened by simulation results. In addition, false turn-on not only increases the turn-on loss E on of hard switching-on device, but also brings about extra false turn-on loss E cr , in which E cr can only be calculated by simulation as listed in Table 7.
From Table 7, it can be drawn that the simulated turn-on loss is in consensus with the experiment calculation, which can further verify the correctness of the constructed VOLUME 9, 2021  (3) In Figure 10 and Figure 11, crosstalk voltage has exceeded the threshold voltage of GaN, and this can be verified by the forward conducting channel currents I ch1 in Q 1 . As gate turn-off voltage going low, the gate false turn-on can be relieved and even averted as illustrated in Figure 11 and Figure 12, which implies that the optimal gate turn-off voltage can be determined by parameter scanning simulation.
To further verify the correctness of the constructed gate crosstalk voltage calculation SPICE circuit model, an experiment under power loop inductance L ds equaling 13.6nH is conducted. In which, the value of L ds is changed by regulating the wire length of the print circuit board (PCB) jumper in the power loop. Comparisons between the simulated and experiment measured dynamic switching waveforms are illustrated in Figure 13. Besides, an experiment under dc-link voltage equaling 70V is conducted and the experiment waveforms are shown in Figure 14.
From Figure 13 and Figure 14, it can be seen that the simulated gate crosstalk voltages are in consensus with the measurement results and the simulated dynamic waveforms match the measured results quite well, which shows that the proposed gate crosstalk voltage simulation model goes under different power loop inductances and dc-link voltages.

IV. SIMULATION BASED PARAMETRIC ANALYSIS
As the correctness of the constructed simulation model has been verified in section III above, based on the simulation model, parametric analysis will be conducted in this section to exemplify the false turn-on suppression methods.

A. OPTIMAL DESIGN OF GATE TURN-OFF RESISTANCE AND INDUCTANCE
Based on the SPICE simulation model and default electrical parameters listed in Table 6, the simulated turn-on loss E on of Q 2 and false turn-on induced loss E cr of Q 1 when gate turn-off resistance R goff(ext) of Q 1 changes in the range of 0.1∼10 and gate turn-off inductance L goff1 of Q 1 changes in the range of 0.1nH∼10nH are shown in Figure 15.
From Figure 15, it can be seen that false turn-on has always happened when switching Q 1 off with 0V voltage. E cr is in positive proportion with the increasing of R goff(ext) and L goff1 . Owing to the existence of gate internal resistance and fast turn-on speed, it's insufficient to suppress false turn-on by decreasing R goff(ext) or L goff1 . At the same time, as the increasing of R goff(ext) or L goff1 , false turn-on induced extra loss E cr of Q 1 becomes comparable to the turn-on loss E on of Q 2 and false turn-on has also increased the turn-on loss of Q 2 substantially. Thus, when turning Q 1 off with 0V voltage, R goff(ext) and L goff1 should be deliberately designed. Contour of E cr under different R goff(ext) and L goff1 is illustrated in Figure 16.
From Figure 16, it can be drawn that the optimal design region of R goff(ext) and L goff1 shown by the shaded area can be figured out once the acceptable false turn-on induced loss limitation 0.5 µJ has been determined.

B. OPTIMAL DESIGN OF GATE TURN-OFF VOLTAGE
As can be seen from section IV.A that controlling R goff(ext) and L goff1 can't suppress false turn-on totally at some cases. By comparison, turning GaN off with negative voltage seems to be a more reliable method. Contours of false turn-on induced extra loss E cr under V goff1 equaling −1V and −2V are illustrated in Figure 17(a) and Figure 17(b) respectively.
From Figure 17, it can be seen that the acceptable R goff(ext) and L goff1 region increases as the decreasing of the negative turn-off voltage. Thus, the PCB design difficulties of gate loop can be relieved. However, as the negative turn-off voltage will increase the deadtime free-wheeling loss, optimal turn-off voltage should be determined according to the acceptable maximum E cr and preset R goff1 − L goff1 design region. As illustrated by the shaded area in Figure 17(b), if E cr should be controlled below 0.01µJ and the gate turn-off inductance will be designed to be as large as 6nH, then gate turn-off voltage should be optimally controlled to be no more than −2V.

C. OPTIMAL DESIGN OF POWER LOOP STRAY INDUCTANCE
Under given gate driving condition, power loop stray inductance L ds will determine the rising speed and peak of drain-source voltage V ds known as false turn-on exciting source as mentioned above. Thus, the effect that L ds has on false turn-on must be investigated considerably.
Based on the default experiment parameters listed in Table 6 and the constructed simulation model, the simulated E cr , E on and the sum of both E cr and E on under different R goff(ext) and L ds are illustrated in Figure 18.
From Figure 18, it can be seen that the severity of false turn-on deteriorates as the increasing of L ds especially when R goff(ext) is large. Though E on decreases as the increasing of L ds , E cr has increases to an extent comparable to E on . Considering that large L ds also causes large turn-on and turnoff overvoltage as in [8], [21], [24], [25], thus L ds should be controlled as small as possible by optimal PCB layout and routing of power loop at the very beginning of power converter design.

V. CONCLUSION
This paper has proposed a comprehensive false turn-on problem analysis and suppression method in GaN HEMT phase-leg topology. False turn-on analytical method and its deficits have been analyzed first, based on which a more precise false turn-on circuit model is proposed with gate-source nonlinear capacitance accurately modeled and gate internal parasitic resistance taken into consideration. For the accurate modeling of false turn-on excitation, an accurate GaN HEMT electrothermal behavior model has been proposed further, based on which GaN HEMT half bridge SPICE simulation model is constructed. Experiment results show that the constructed simulation model can calculate the false turn-on accurately. Besides, based on the constructed circuit model, false turn-on suppression by optimal design of gate driving electrical parameters and power loop stray inductance by parametric analysis can be implemented.
LI PU received the B.S. degree in electrical engineering from the Huazhong University of Science and Technology, in 2016.
He is currently working with Ultra High Voltage Transmission Company Kunming Bureau, China Southern Power Grid. His research interests include wide bandgap power semiconductor device and high voltage power converter.
DONGDONG CHEN received the B.S. degree in electronic information engineering from Zhejiang University, Hangzhou, China, in 2013, and the Ph.D. degree in electrical engineering from the College of Electrical Engineering, Zhejiang University, in 2018.
He is currently a Vice Professor with the Minnan University of Science and Technology. His research interests include power electronics systems design, power converter digital control, and optimal design. WU LIANG (Student Member, IEEE) received the B.S. degree in hydropower engineering from the Huazhong University of Science and Technology, Wuhan, China, in 2015, and the Ph.D. degree in electrical engineering from Zhejiang University, Hangzhou, China, in 2020.
He is currently an Engineer with Huawei Technologies Company Ltd., Dongguan, China. His current research interests include the application of wide band-gap (WBG) semiconductors, high-frequency power conversion, resonant converters, and optimization of power converters. VOLUME 9, 2021