A Physic-Based Explicit Compact Model for Reconfigurable Field-Effect Transistor

In this paper, a compact model for the double-gate Reconfigurable Field-Effect Transistor (RFET) is presented. Firstly, the physics-based surface potential model is derived by solving Poisson’s equation at different channel regions. Then an explicit expression of drain current is analytically obtained based on the theory of band-to-band tunneling at the Schottky junction. The proposed model shows excellent agreement with TCAD simulations which have been calibrated with experimental data. Finally, the compactible model is implemented in Verilog-A language without convergence problem, and proven by the RFET-based logic circuit.


I. INTRODUCTION
With the rapid development of neuromorphic computing, high-throughput data put forward with substantial requirements for downscaling and power-efficient electronic circuits. However, it becomes increasingly challenging to simply reduce the size of devices based on conventional complementary metal-oxide-semiconductor (CMOS) technology due to their physical limitations. The reconfigurable fieldeffect transistors (RFET) have emerged as a promising candidate for the single device with tunable polarity [1]- [4]. Instead of conventional physical doping, feature gated Schottky junctions of the RFETs can controllably inject electrons or holes into the channel. In this case, the RFETs can provide both n-and p-FET device patterns by adjusting the bias of the polarity gate [5]- [8]. When one gate injects electrons into the channel, and the other gate stops the holes, then the n-type RFETs are obtained. Similarly, the p-type can also be obtained by reversed bias. By increasing the number of functions per transistor rather than reducing the size of the device [9]- [11], the RFETs are expected to provide reliable and reprogrammable CMOS operation, which are The associate editor coordinating the review of this manuscript and approving it for publication was Aimin Song . beneficial to pave the way to silicon circuits that go beyond Moore's law.
Recently, several RFETs have been fabricated based on top-down or bottom-up processes [12]. The experimental results show a high on/off ratio (∼10 9 ) and extremely low gate leakage (∼10 −14 A), which make such a device concept desirable for energy-efficient circuit applications. Besides, a high-density synaptic device based on RFET has been proposed to build XNOR binary neural network [13]. Besides, the impact of work-function modulation, gate/spacer-channel underlap have been investigated through numerical simulations [14], [15].
To further understand the mechanism of the RFET, optimize its device characteristics and perform circuit design, it is essential to develop a physics-based compact model. An analytical surface potential and drain current model is reported in [16] by solving drift-diffusion equation in the channel with Schottky tunneling at the source/drain contact. However, the drain current of this model is expressed as an implicit function of quasi-fermi potentials. The complex computational process may cause convergence issues during circuit simulation. Besides, for low drain biases, the model results mentioned in [16] are not in good agreement with the simulations. Thus, the major objective of this paper is to provide a compact model that has no convergence and accuracy problem in circuit simulation. Meanwhile, the proposed model is expected to be a SPICE compatible model and universally applicable.
In this paper, a closed-form surface potential-based model for the double-gate RFET is put forward, which is performed in the x and y two-dimensional plane. The silicon channel is divided into three regions to solve the 2D Poisson's equation. To begin with, the surface potential model is developed using several boundary conditions. Then the charge density model is derived from the current continuity equation. Finally, the drain current model for the RFET is given based on the theory of band-to-band tunneling induced by the Schottky junctions. After Taylor expansion and proper approximation, an explicit analytical compact drain current model is developed. The accuracy of the proposed model is validated by numerous TCAD simulations after calibration with the experimental data. Besides, the explicit nature of the model makes it suitable to be a SPICE compatible model, which is beneficial for circuit simulations.
The remainder of this article is organized as follows. Section II describes the device structure and the simulation environment. Section III introduces the derivation of explicit surface potential, charge density and drain current model for the RFET. In Section IV, the implementation of the proposed compact model in Verilog-A is discussed, which is useful for RFET-based circuit simulations. Finally, Section V concludes this article. Fig. 1 shows the structure of the double-gate RFET. To note that, the source/drain contacts are metallic (typically NiSi 2 ) to induce lateral Schottky junctions, which is also beneficial to decrease the parasitic capacitance and resistance. In order to modulate the device polarity electrically, the control gate (gate1) and polarity gate (gate2) are applied. Simulations are performed by technology computer-aided design (TCAD) simulations [17]. Based on the experimental data reported in [4], the same structure of RFET is employed to calibrate the simulation setup. Carrier recombination includes Band-to-Band recombination, Shockley-Read-Hall (SRH) recombination and Auger combination. The Wentzel-Kramers-Brillouin (WKB) approximation is employed for the band-to-band tunneling (BTBT) model, with electron and hole tunneling masses as 0.3 m 0 and 0.2 m 0 [16]. The  thermionic-field emission model has been applied at the (S/D) Schottky junctions, and the Schottky barriers for electrons and holes are considered to be 0.58 eV and 0.54 eV respectively [18]. Besides, the quantization effects are taken into consideration by introducing electronic quantum potential and hole quantum potential. Besides, high-field Saturation model, Lombardi mobility model, and Philips unified mobility model are included in the Mobility model. It can be observed from Fig. 2 that the transfer characteristic curves plotted with the TCAD simulator agree well with the experimental results, which proves the validity of our simulation environment. In the following studies, the parameters used in this work are presented in Table 1.

II. DEVICE STRUCTURE AND SIMULATION SETUP
The simulated energy band diagrams of both ON-states and OFF-states are shown in Fig. 3. To make the device acts as an n-type FET, the voltages of gate1, gate2 and drain are kept positive. This causes the edge of the conduction band to bend down, which makes it easier for the electrons to tunnel from the source into the channel region. For p-type FET, the voltages of three electrodes mentioned above are kept negative, which makes the conduction band bend upwards. In this case, holes are likely to tunnel into the channel.

III. MODEL DEVELOPMENT A. SURFACE POTENTIAL MODEL
As shown in Fig. 1, the silicon channel is divided into three regions. Region 1 and Region 2 are Schottky-gated with gate1 and gate2, while Region 3 is not modulated with an external gate. Firstly, the two-dimensional (2D) Poisson's equation can be solved to obtain the surface potentials in Region 1 and Region 2.
where ϕ 1/2 (x, y) refers to the electrostatic potential of Region 1 or Region 2. ε ox and ε Si are the permittivities of silicon dioxide and silicon respectively. N C is the doping concentration of the silicon channel. The boundary conditions along y-direction (channel thickness) can be given as is the voltage applied on gate1 or gate2, and V FB is the flat band voltage.
Using the parabolic approximation [19], the electrostatic potential for Region 1 or Region 2 can be written as Assuming ϕ 1/2 (x, 0) = ϕ 1/2 (x, t Si ) = ϕ 1/2 (x), the surface potential for Region 1 (ϕ 1 (x)) and Region 2 (ϕ 2 (x)) can be solved and expressed as The boundary conditions along x-direction (channel length) can be expressed as where χ is the electronic affinity, W m is the metal workfunction. V d and V s are the voltage applied on the drain and source respectively. Besides, k is an even number for the n-program and an odd number for the p-program.
In order to obtain the potential distribution in Region 3, the gradual channel approximation is employed. The surface potential for Region 3 can be expressed as Because of the continuity of the surface potential and its first derivative, the boundary conditions can be given as Using the boundary conditions mentioned above, the surface potential ϕ L 1 and ϕ L 2 are solved for both n-and p-type RFETs, as shown in Fig. 4.

B. CHANNEL CHARGE DENSITY MODEL
Based on the surface potential, the electric field E of the channel surface along the x-direction can be calculated.  The model and simulation results are shown in Fig. 5 for both n-and p-type RFET. Then the relationship between the carrier mobility (µ) and the surface electric field can be given as A kind of continuity equations which describe charge conservation is shown below where R net,n and R net,p are the electron and hole net recombination rates, respectively. In addition, by solving the current continuity equation, the current density in the n-type and p-type channel can be expressed as J n = qµ n n(x)|E n (x)| (12a) When the channel reaches its equilibrium state, the carrier concentration does not change, so ∂n/∂t and ∂p/∂t are considered to be zero. By combining Equations (11a) and (12a), (11b) and (12b), the charge densities of both n-type and p-type channels are derived, which are shown in Fig. 6.

C. DRAIN CURRENT MODEL
Using the Kane's model [20], the band-to-band generation rate (G BTB ) can be derived as The band-to-band tunneling probability is used to calculate the drain current across the Schottky barrier nearby the source.
46712 VOLUME 9, 2021 where A, B and D are Kane's tunneling parameters given by [21]. E avg = E g qx refers to the electric field on average, E g is the bandgap of silicon, and x is the tunneling path from x 1 to x 2 shown in Fig. 3(a) and (b). x 1 represents the starting point of the tunneling, and x 2 represents the ending point of the tunneling. The expressions of x 1 and x 2 can be calculated by [22] x 1 = λ ln θ a + θ 2 a − 4C 1 D 1 2C 1 (15a) Besides, the electric field is obtained by The expression of E x and E y can be obtained from (4a) and (3), respectively. The electric field can be given as The unary Taylor expansion is applied to the E x and subsequently binary Taylor expansion is applied to E, the expression can be simplified as Applying the interval of integration for both x-direction and y-direction, the expression of the drain current is obtained. (here the width of the device is considered to be 1 µm and the parameter D is considered to be 2 for the direct tunneling process).
After calculating the integration rearranging, the drain current for the RFET is finally obtained where ξ (x) and ζ (x) are given by In equation (20), the parameters a and b explicitly contain the drain voltage V d , the source voltage V s , and the gate voltages, which shows the explicit nature of this model.
The transfer characteristic (I d − V g ) characteristics of the RFETs are plotted in Fig. 7 with different channel doping concentrations. For the band to band tunneling, the value of drain current depends on the tunneling probability of carriers. When the applied voltage (V g1 ) increases, the electric field intensity in the barrier area increases, which shortens the tunnel length. Thus, the carriers are more likely to tunnel. As a result, the current becomes larger. When V g1 is small, the electric field in the barrier area under different channel doping concentrations is considered to be approximately equal, which leads to almost the same I off . For a given voltage that is large enough, the RFET with high channel doping concentration has higher electric field intensity in the barrier area, which makes carriers tunnel more easily. As a result, higher channel doping concentration leads to larger saturation current.
From Fig. 8, the transfer characteristic curves of the RFET at different temperatures are depicted. As the temperature rises, the energy of the carrier increases, so the probability of tunneling increases. When V g1 is small, the tunneling of carriers largely depends on temperature, and thus the leakage current increases accordingly with temperature.
As the gate voltage goes up, the electric field intensity in the barrier area gradually plays a leading role. When the voltage rises to a certain value, the impact of the evaluated temperature is weakened, and the drain current is mainly determined by gate voltage. In this case, the electric field intensity generated by the voltage (V g1 ) in the barrier region is the same even at different temperatures, which means that the carriers have almost the same probability to tunnel. Thus, as the gate voltage is high enough, the change  of drain current at different temperatures tends to be small. In the calculation processes mentioned above, the Fermi level E Source F strongly depends on the value of temperature, so parameter 1 is influenced by the temperature. As a result, the impact of temperature on the drain current is very significant.
The output characteristics curves of the RFET are shown in Fig. 9. It also shows that the model is in good agreement with TCAD simulations for both n-and p-type RFET.

IV. RFET-BASED LOGIC GATE CIRCUITS
As the polarity gate and control gate are located at two Schottky junctions of the RFETs, it has the potential for high-density integration and low cost, which are suitable for future applications in large-scale integrated circuits.
For circuit validation, the proposed model is implemented in Verilog-A. Here, an RFET-based inverter logic gate circuit is simulated by Cadence Virtuoso. To form an inverter,  two RFETs are connected in series between the supply and ground, and the value of the capacitance is 10 fF, as shown in Fig. 10. One is biased at n-type and the other is biased at p-type. Fig. 11 plots the transient simulation result of an inverter. It can be seen that the proposed INV performs the function successfully. Besides, it shows fast switching speed and full swing output, which performs better performance than conventional CMOS logic operations.

V. CONCLUSION
In this paper, we have presented a compact physics-based model for the surface potential, charge density and drain current of the reconfigurable field-effect transistors (RFETs). The model shows excellent agreement with TCAD simulation data over broad bias. Finally, RFET-based circuit simulation is performed in Verilog-A, which demonstrates that the proposed model is suitable to be a SPICE compatible model.

APPENDIX
For equation (16), the total electric field intensity is equal to the vector sum of the transverse and vertical electric fields, which means E = E 2 x + E 2 y . The relationship between the electric field and the potential in the tunneling region is obtained as where E x and E y are the transverse electric field and vertical electric field respectively. Substitute them into equation E = E 2 x + E 2 y , equation (17) can be obtained. The Taylor expansion applied to equation (17) is shown below. By applying unary Taylor expansion to the E x , E x can be expressed as Assuming C 1 − D 1 = b and C 1 + D 1 = a, the total electric field can be obtained.
In order to simplify the calculation, the coefficient −1 is ignored here. Next, the computational process of binary Taylor expansion is shown below.
To prove the validity of the integration mentioned in equation (20), we will provide a detailed integral process in this section.
After integrating the variable y, the integration can be expressed as by using some approximations, it can be calculated that Now equation (20)