Characteristics of Parallel Carry-Free Three-Step MSD Additions

Since the modified signed digital (MSD) redundant representation was proposed in the 1950s, lots of achievements have been made in MSD arithmetic. By inspecting the processes of the parallel carry-free three-step MSD addition, the transformations for such additions are studied in detail in this paper. The characteristics for parallel carry-free three-step MSD addition are proposed and the correctness is proved. Then seven groups of transformations that have characteristics of three-step MSD addition are presented. These groups of transformations are dual or self-dual, and some of them have simpler forms than the typical transformations consisting of $T, W, T', W', T_{2}$ . The general design mode of parallel carry-free three-step MSD additions and its applications in ternary optical computer (TOC) are further proposed. At the same time, single adder (multi-adder) reconstruction mode, processor bits allocation strategy, and light path diagrams are given. The optical experiments of MSD additions for three groups of MSD addition transformations show that the results of these transformations are correct. This work provides the theoretical basis for the design of the ternary optical computer adder.


I. INTRODUCTION
Addition is the most fundamental arithmetic operation in most processors. But the problem of carrying propagation from the least-significant-bit to the most-significant-bit in conventional binary addition inevitably affects the computing speed. People commonly meet the difficulties in massive parallelism, high speed,and huge data processing in the electronic computer. To solve these problems, mathematicians and computer scientists have long been looking for fast and effective algorithms and have therefore proposed many non-binary number systems [1]- [3], such as the redundant number systems [4]- [6]. O Akbari et al. proposed a fast yet energy-efficient reconfigurable approximate carry look-ahead adder [7].
In the 1950s, A. Avizienis proposed the signed-digit representation [4], which eliminated the carry propagation chains for operands. The redundancy in number representation makes the fast and parallel addition and subtraction possible. Soon afterward, the modified signed-digit (MSD) representation is presented, which The associate editor coordinating the review of this manuscript and approving it for publication was Tomás F. Pena . belongs to a redundant-number set of radix-2. In 1986, B. L. Drake, R. P. Bocker, et al. applied modified signed-digit representation to optical computing [8], [9] and suggested an optical architecture. It offered fully parallel carry-free arithmetic operations. Now studies on optical computing algorithms and techniques have been made much progress and the optical computing modes have shown remarkable advantages in meeting the requirements such as parallel, carry-free, and fast computing. According to the value of the radix, the signed-digit representation contains the subsets of MSD number [5], [8]- [11], trinary [2], [3], [12], [13], quaternary [14]- [16] and negabinary signed-digit number [17], and so on. According to the steps of optical computing, the MSD additions are now usually classified in terms of the number of steps involved, i.e., three-step [5], [8]- [11], two-step [12]- [14], [18]- [20] and one-step algorithms [17], [21]- [24]. These two-step additions or one-step additions generally use more complex optical structures or focus on some specific data sets. The MSD number system with the radix r = 2 and the digit set {1, 0, 1} is a typical signed-digit system. Since the MSD representation for optical computing was adopted VOLUME 9, 2021 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ in 1986 [8], and MSD arithmetic algorithms have been carried out deeply and several research directions and branches in optical computers have appeared. Scientists naturally consider using optical components to make optical computers, especially the all-optical computers [25], but the progress in design and development are not rapid. A new computational rule for redundant binary adder generating the intermediate sum and intermediate carry in posibit and inverted encoding of negabits representations replacing the redundant digits are proposed [26]. Since the principle and structure of the ternary optical computer was proposed by Jin Yi et al. [27], [28], lots of work has been done in this field [29]- [32]. Ternary optical computer (TOC) uses two polarized lights with orthogonal polarization states and a null light state to express information, and uses such device as liquid crystal pixel array to rotate the polarization direction of light in order to make light state conversion. It can have millions of processor bits to realize various operations. TOC has such features as easy processor bit scalability, huge processor bits, bitwise allocability, bitwise reconfigurability, parallel computing, and low power consumption and so on, which makes it more suitable for fast processing large batches of data with complex operations. In 2017, a prototype SD16 (short for ''ShangDa 2016'', and ''ShangDa'' means Shanghai University) of the ternary optical processor (TOP) is constructed in Shanghai University, every module has 192 processor bits and has the functions described above. Much progress has been made in the design and development of the ternary optical computer [33]- [36].
In this situation, as early as 2010, the authors began to consider the problem of parallel carry-free MSD addition. By the summer of 2013, Shen Yunfu gave the rules of MSD addition transformation that can satisfy parallel computing. In 2016, many complete sets of transformation rules were formed and applied in the design of actual optical computer processors and one set of the MSD transformations is used to perform carry-free MSD addition in SD16. This work is summarized in this paper.
In this paper, by studying MSD number system with the radix r = 2 and the redundancy digit set {1, 0, 1} and inspecting the generation of transfer and weight digits in MSD addition, the authors study three-step algorithms realizing MSD addition and obtain several groups MSD addition transformations. After executing these logic transformations, the weight and transfer digits and the final sum digits can be generated in three steps. In Section II, we give a brief introduction to MSD representation and the typical three-step MSD addition. In Section III, by inspecting the typical three-step MSD addition, we give the characteristics for parallel carry-free three-step MSD addition and the corresponding ternary logic transformations with these characteristics. In Section IV, we give the general design mode of parallel carry-free three-step MSD additions and its applications. Then optical experiments of MSD addition transformations are carried out. Finally, we summarize our work in Section V.

II. BRIEF INTRODUCTION TO MSD ADDITION
MSD system was proposed by Avizienis in 1961 [4], for any decimal number A = a n a n−1 · · · a 1 a 0 .a −1 · · · can be represented by an MSD number representation shown in formula (1).
Here we discuss the MSD number system of radix r = 2. The modified signed-digital redundant representation uses {1, 0, 1} to present numbers, which is simply a binary system with no sign bit, where the symbol1 stands for -1.
where a i ∈ {1, 0, 1} and i is an integer. Any decimal number A except for 0 has many MSD representations. For example, Let A and B be two MSD numbers a n a n−1 · · · a 1 and b n b n−1 · · · b 1 respectively. Then the n-bit MSD addition of A and B can be carried out in three steps according to TW transformations in Table 1, and its computing processes are listed in Table 2 [29]. We will call it TW-MSD addition.

III. CHARACTERISTICS FOR PARALLEL CARRY-FREE THREE-STEP MSD ADDITION A. CHARACTERISTICS OF CARRY-FREE THREE-STEP MSD ADDITIONS
Since the TW transformations mentioned in Section II is only a special case of the ternary logic transformations discussed in this paper. For the sake of generality and distinguish from TW-MSD addition, we use five ternary logic transformations Y , F, Y , F , S instead of T , W , T , W , T 2 , and the new five transformations are called YFS transformations for short.
Let A and B be two MSD numbers a n a n−1 · · · a 1 and b n b n−1 · · · b 1 respectively. The mode of carry-free 49602 VOLUME 9, 2021 three-step MSD addition of A and B with five ternary logic transformations Y , F, Y , F , S on {1, 0, 1} is described as follows.
Step 1: Apply the Y transformation to the numbers A and B bit by bit to obtain a result denoted with y. Append one 0 at the end of y and denote the result with y too. Meanwhile, apply the F transformation to A and B bit by bit to obtain a result denoted by f . Add one 0 at the head of f and denote it with f too.
Step 2: Apply the Y transformation to y and f bit by bit to obtain the result y . Append one 0 at the end of y and still denote it with y . Meanwhile, apply the F transformation to y and f bit by bit to obtain the result f . Add one 0 at the head of f and denote it with f too.
Step 3: Apply S transformation to y and f bit by bit to obtain s. Now s is the sum of A and B.
Computing processes of the general MSD addition are described in Table 3. Next, we discuss the establishment conditions of the YFS transformations to realize the carry-free three-step MSD addition.
Theorem 1: Given five ternary logic transformations Y , F, Y , F , S on {1, 0, 1}, suppose that they satisfy the following equations (2), (3), and (4) Then for any n-bit MSD numbers A = a n a n−1 · · · a 2 a 1 and B = b n b n−1 · · · b 2 b 1 , the sum s of A and B can be done in three steps with the processes described above using trans- Furthermore, if the two cases which y i−1 = f i = 1 and y i−1 = f i =1 don't occur in the processes of addition, then the group consisting of five transformations Y , F, Y , F , S is a ternary transformations group of parallel carry-free MSD addition.
Proof: The theorem can be proved by mathematical induction on n.
Consider any two n-bit MSD numbers A and B, A = a n a n−1 · · · a 2 a 1 and B = b n b n−1 · · · b 2 b 1 .
If n = 1, the sum of A and B is a 1 +b 1 . a 1 +b 1 = y 1 ×2+f 1 at the first step, 0 Here, y 1 + f 2 has no carry-bit according to the assumption of the theorem. The computing processes are listed as follows.
Suppose that the proposition is true when n = k − 1. Now let n = k. Denote C = a n a n−1 . . . a 3 a 2 and . Now we do MSD additions A + B and C + D by applying transformations Y , F, Y , F , S respectively. By induction assumption, e n+2 e n+1 . . . e 3 e 2 is the sum of C and D.
We list the processes of MSD additions A + B and C + D in Table 4.
Obviously, we have s i = e i for i = 4, 5, · · · , n + 2. Now it only needs to prove that s 3 s 2 s 1 = e 3 e 2 ×2+(a 1 +b 1 ) is correct, which is to prove (5). Denote the right side of (5) by V . By the condition of the theorem, obviously, e 2 = 0 + f 2 = f 2 . Since the cases y 2 + f 3 = 2 and y 2 + f 3 = −2 do not appear according to the condition of the theorem, the equation e 3 = y 2 + f 3 always holds. Similarly, We have the following relations.
Thus, we have proved that V = s 3 × 2 2 + s 2 × 2 + s 1 . That is, the proposition is true when n = k.
Hence it is obvious that the theorem is proved by the induction.

B. THE TERNARY LOGIC TRANSFORMATIONS WITH CHARACTERISTICS OF THREE-STEP MSD ADDITION
In this section, we will find the ternary logic transformations which satisfy the condition in Theorem 1. Now we inspect the processes of carry-free MSD addition.
For any two MSD numbers A = a n a n−1 a n−2 · · · a 2 a 1 and Now consider a general addition mode on the number set {1, 0, 1} based on Table 5. But this addition operation is not closed on the number set {1, 0, 1} because 2 and -2 are not in {1, 0, 1}. Now we split them based on radix-2. Obviously, 2 = 1 × 2 + 0 and −2 =1 × 2 + 0. Write 2 as a two-tuple (1, 0) and −2 as a two-tuple (1, 0). The sum s of a and b of 1-bit data in Table 5 can be represented by two-tuple (t, w) with s = t ×2+w, where t, w ∈ {1, 0, 1}. Table 6 lists the possible two-tuple representations for all values in Table 5. Obviously, t is a transfer digit and w is a weight digit in two-tuple (t, w).  Table 6 by splitting the transfer digit and weight digit, we can obtain 16 possible transformation groups, each of which consists of two transformation tables. But some of them do not satisfied the MSD addition requirements of Theorem 1.

Considering various combinations of all the values in
For any five transformations Y , F, Y , F , S on {1, 0, 1}, suppose that they satisfy conditions (2), (3) and (4) and the additional condition that y i−1 = f i = 1 or1 don't occur in the processes of MSD addition in the theorem. Now we discuss when the situations y i−1 = f i = 1 or y i−1 = f i =1 appear from the last step to the first step of the processes of three-step MSD addition.
Since 1 = 0 × 2 + 1 = 1 × 2 +1, and1 = 0 × 2 +1 = 1 × 2 + 1, we need to consider all combinations by checking the processes of the computing steps in Table 3. According to condition (7), y i−1 is associated with the equation Now, we list 8 basic transformation conditions. For brevity, we denote them: Considering the combination of basic conditions, we have the four basic combinatorial relations: ( The incompatible cases may occur in the following two computing modes: * a i a i−1 The corresponding transformation tables are presented in Tables 7-13. Here the symbol * and # can be any digit from {1, 0, 1}. The letters labeled t, w, v, x are optional which satisfy the corresponding relations 1 = t × 2 + w and1 = v × 2 + x, that is, (t, w) = (1,1) or (0, 1) and (v, x) = (1, 1) or (0,1). By selecting the values of t, w, v and x in Table 7, we will obtain four groups of transformations Y and F .
Furthermore, we will obtain another nine forms of transformation S by selecting the values # and * from {1, 0, 1}. This will provide great convenience in designing ternary optical adders.
Definition: (i) Two ternary logic truth tables M and N are said to be dual if one table becomes another by exchanging the symbols 1 and1 in one table.
(ii) M is said to be self-dual if M remains unchanged when the symbol 1 and1 are exchanged each other in M . (iii) Given two sets τ and τ of transformations with same number, τ and VOLUME 9, 2021   τ are said to be dual if there is a one to one relation from τ to τ so that the corresponding transformations are dual. Especially, a set of transformations τ is said to be self-dual if any transformation in τ is self-dual. By the above definition, we have the following: (1) The set of transformations T , W , T , W , T 2 is self dual.
The dual carry-free MSD addition transformations are usually regarded as the same.
The transformations in Tables 8 and 9 are dual. The transformations in Tables 10 and 11 are dual.
Similarly, we have the simplified forms 13A and Table 13B  of Table 13.
Next, we prove that the cases y i−1 = f i = 1 and y i−1 = f i =1 mentioned in Theorem 1 cannot appear during the processes of three-step transformations Y , F, Y , F , S for any group of transformations successively. The correctness of TW-MSD addition has been recognized by scholars. But for other transformations listed in Table 8-13, due to paper limitations, we can only list the following conclusions.

Theorem 2: For any two MSD numbers A
= a n a n−1 · · · a 2 a 1 and B = b n b n−1 · · · b 2 b 1 , the cases y i−1 = f i = 1 or y i−1 = f i =1 cannot appear after applying the transformations Y , F, Y , F in Table 8 to A and B successively.
Proof: To shorten the length of this article, the proof is omitted. (Please refer to Appendix A).
Theorem 3: For any two MSD numbers A = a n a n−1 · · · a 2 a 1 and B = b n b n−1 · · · b 2 b 1 , the cases y i−1 = f i = 1 and1 cannot appear by applying any VOLUME 9, 2021 set transformations Y , F, Y , F of Table 9-13 to a and b successively.
Proof: The proof is similar to Theorem 2 and is omitted here. (Please refer to Appendix B).
Theorem 4: All transformations Y , F, Y , F and S given in Table 7-13 have the characteristics of parallel carry-free three-step MSD addition.
Proof: The theorem is proved by Theorem 1, Theorem 2 and Theorem 3.  Figure 1 is the construction schematic diagram of TOC. It consists of two parts: an upper computer (a master computer, a common PC) and a lower computer (a slave computer, or the ternary optical processor). The master computer is responsible for task management and communicating with users as well as the slave computer. That is, it generates the reconstruction information and receives information from the optical processor. TOC uses two polarized lights with orthogonal polarization states and a null-light state to express information, and uses such device as liquid crystal pixel array to rotate the polarization direction of light in order to perform light state conversion. It can have millions of processor bits to realize various operations. One of the core units in ''Ternary optical processor'' is the ''Optical state converter''; another is ''Reconfigure unit'' for reconstructing frame and induction, which realizes the three light states transition. The processor reconstruction makes TOC reconstruct its functions for various operators required by the user. The input numbers are a and b, where a is used as the data of main optical path through the Signal Generator of Main Light Path, and b is used as the data of control optical path through the Signal Generator of Control Light Path. The calculated result beam is sent to the TOC decoder by the control system in the slave computer to obtain the user's binary result data.  Figure 2 is a prototype SD16 developed based on the above construction schematic of TOC. Each of its modules has 192 processor bits and can load up to 64 modules. Therefore, each prototype SD16 has a maximum of 12,228 processor bits. At present, each processor bit can be reconfigured into a bit of any ternary (including binary) logical operator, and some processor bits can be used to construct a parallel carry-free adder. The processor is reconfigurable according to user's requirements. In SD16, a liquid crystal board LCD with 24 × 24 grids (or pixels) is served as a processor, and the layout of the pixel bits in the liquid crystal is arranged in the form as in Figure 3, where three adjacent pixels in the same row form a processor bit. Here, the LCD board is divided into two parts: the left and right parts. The twelve grids at the bottom of the left part are divided into 4 sections from right to left, which are 49608 VOLUME 9, 2021

B. SINGLE ADDER RECONSTRUCTION MODE
The bits of optical processor can be numbered from 0 to MAX − 1 in some order, where MAX is the number of processor bits. Here MAX = 192. According to the calculation mode of n-bit MSD addition in Section III.A, the MSD adder is designed and configured as follows. Let the position of the adder be start. Then in the processor, the Y transformer is reconstructed from start to start +(n−1), and the transformer F is reconstructed from start + n to start + 2n − 1. Similarly, transformers Y , F and S are reconstructed from start +2n to start + 3n, start + 3n + 1 to start + 4n + 1 and start + 4n + 2 to start + 5n + 3 respectively. The configuration of MSD adder with n = 5 bits is shown in Figure 4, where start = 0. Generally, an n-bit MSD adder uses 5n + 4 bits.

C. MULTI-ADDER RECONSTRUCTION MODE
It is assumed that t adders need to be configured on the processor. Suppose that the starting position of the i-th adder is pos [i], and the number of adder bits is len i and pos [1] = start. If the centralized reconstruction mode shown in Figure 5 is adopted in the processor, then pos[i+1] = pos[i]+5×len i +4. The independent bit allocation mode of three MSD adders of k-bit, m-bit and n-bit is shown in Figure 5.

D. THE APPLICATION OF MSD ADDITION TRANSFORMATIONS TO THE DESIGN OF MSD ADDER
In the parallel carry-free MSD adder transformations given in Table 7-13, there are several groups of transformations that are relatively simple. Here,we take a group of transformations as an example to further clarify these transformation tables that meet the conditions of the carry-free parallel adder. The following optical path diagram is a schematic diagram of the five transformations in Table 13B.The light path diagrams of Y and F, Y and F , S transformations are shown in Figure 6, 7, 8 respectively.
In these optical path diagrams, the rectangles marked LC1∼ LC5 represent optically inactive liquid crystal. It is not in the photon spin state when there is no control signal acting on crystal, and it is photon spin state when there is a control signal acting on the crystal. At this time, if the light directed to the liquid crystal is vertical light, the light transmitted through the liquid crystal becomes horizontal light and vice versa; the diamonds represent vertical polarizers (only allow vertical light to pass through the polarizers) or horizontal polarizers(only allow horizontal light to pass through the polarizers); LD1 and LD2 are photoelectric converters, it can convert optical signals into electrical signals; ''Light'' represents uniform scattering white light source, it includes three optically states (null light,vertical light,horizontal light). The thin lines with an arrow are the control light paths and the grey lines with an arrow are the main light paths.
It generally assumes that value 0 is represented by a null light state, value 1 is represented by vertically polarized light, and value1 is represented by horizontally polarized light.

E. OPTICAL EXPERIMENTS OF MSD ADDITION TRANSFORMATIONS
Here we take a group of transformations as examples to illustrate that the conclusion is correct. We take three sets of carry-free MSD transformations in Table 8 Table 13B.
The theoretical results of MSD additions A + B with the transformations in Table 8, 10 and 13A are listed in Table 14.
Next, we first generate reconstruction instructions according to the data with Table 8, 10, 13A and the single adder reconstruction mode, and then send them to the ternary  Table 13B. optical processor through the slave computer, respectively, to construct three 30-bit adders. Therefore, every adder requires a total of 154 (30 × 5 + 4 = 154) processor bits, of which processor bits No.0 ∼ No. 29  The optical image of addition with Table 8 is shown in Figure 9, and its decoding result s is 01001110101101101 010001111101110 from the high processor bit to the low bit.
The optical image of addition with Table 10 is shown in Figure 10, its decoding result s is 01001110101101101010001111101110.
The optical image of addition with Table 13A is shown in Figure 11, its decoding result s is 01001110101101101010001111101110.
The three decoding results s are all (1166910046) 10 , which are completely consistent with the theoretical results in Table 14.
The three experiments of MSD addition A + B show that the transformations in Table 8, 10 and 13A for MSD additions are correct.  Table 8.  Table 10.  Table 13A.

V. CONCLUSION
Recently, great progress has been made in the research of ternary optical processor. The parallel ternary optical adder based on MSD representation has been equipped with the basic module of SD16 system and run in Shanghai University successfully. This progress marks the advent of new processors with a large number of data bits, data-on-demand allocation and processor configuration based computing functions on demand. In this paper, the parallel carry-free three-step MSD addition transformations are studied deeply, and seven groups of transformations for MSD additions with this characteristic are obtained. They are all alternatives which will be used in the design of carry-free adders of the ternary optical computer. Some of the transformations are rather simple, which is shown in Table 12 or 13. Experiments of MSD additions for MSD transformations in Table 8, 10 and 13A show that the results are correct.
In fact, the transformations Y and F in Table 12 or 13 can be merged into a transformation (Y /F ), in other word, this two group transformation only need 4 transformation tables respectively, therefore, the MSD adders of one bit using them that will only use 4 processor-bits, which greatly decrease the hard resource with 25% compared to TW-MSD adder with transformations T , W , T , W , T 2 . Furthermore, the work in this paper provides a theoretical basis for the design of the carry-free adder of the ternary optical computer.

A. PROOF OF THEOREM 2
Theorem 2: For any two MSD numbers A = a n a n−1 · · · a 2 a 1 and B = b n b n−1 · · · b 2 b 1 , the cases y i−1 = f i = 1 or y i−1 = f i =1 cannot appear after applying the transformations Y , F, Y , F in Table 8 Next we consider the case There are two places of value1 in transformation table Y which are corresponding to input data (y, f ), that is, (y, f ) = (1,1) or (0,1). Hence (y i−2 , f i−1 ) = (1,1) or (0,1), and f i−1 =1. Similarly, there is only one place of1 in transformation table F which is corresponding to the input data (y, f ), that is, (y i−1 , f i ) = (1, 0), and y i−1 =1. Hence (y i−1 , f i−1 ) = (1,1). But there is no such input data (a i−1 , b i−1 ) that It shows that the cases y i−1 = f i = 1 and y i−1 = f i = 1 cannot appear in the processes of transformations. The theorem is proved. VOLUME 9, 2021 B. PROOF OF THEOREM 3 Theorem 3: For any two MSD numbers a = a n a n−1 . . . a 2 a 1 and b = b n b n−1 . . . b 2 b 1 , the cases y i−1 = f i = 1 and1 cannot appear by applying any set transformations Y , F, Y , F of Table 9-13 to a and b successively.
Proof: Note that the transformations in Tables 8 and 9,  Tables 10 and 11 as well as Tables 12 and 13 are dual respectively. If the theorem is true for one group of transformations, the theorem is also true for dual group of transformations. By Theorem 2, it is true for Table 9. Here we only need to discuss Table 10 and Table 12.
Suppose that during the transformations Y , F, Y , F ,the intermediate results Firstly we discuss Table 10. Consider the case On the one hand, y i−1 = 1 is the result of applying transformation Y to y i−2 and f i−1 . In Y transformation table there is only one place of value 1 which is corresponding to the input (y, f ) = (1, 1) in Y transformation table, Hence (y i−2 , f i−1 ) = (1, 1), and f i−1 = 1. On the other hand, f i = 1 is the result of applying transformation F to y i−1 and f i . There are three places of value 1 which are corresponding to input data (y, f ). So (y i−1 , f i ) = (0,1), (0, 1) or (1, 0), and y i−1 = 0 or 1.
Next we consider the case y i−1 = f i =1.
It shows that the cases y i−1 = f i = 1 and y i−1 = f i = 1 cannot appear in the processes of transformations. The theorem is proved.
Secondly, we discuss Table 13. It shows that the cases y i−1 = f i = 1 and y i−1 = f i = 1 cannot appear in the processes of transformations. The theorem is proved for OUYANG SHAN was born in 1979. He received the Ph.D. degree in engineering from Shanghai University, Shanghai, in 2012. He is currently a Lecturer with Shanghai University. His research interests include optical computer and architecture. VOLUME 9, 2021