Predictive Nearest-Level Control Algorithm for Modular Multilevel Converters With Reduced Harmonic Distortion

Owing to the low number of submodules (SMs) in modular multilevel converters (MMCs), especially in medium-voltage applications, the output current and voltage generated by conventional nearest-level control (NLC) methods contain evident distortions. Previously, various hybrid and level-increased NLC methods have been proposed to improve the output voltage quality, but such measures wither increased the complexity or did not regulate all the control objectives simultaneously. To further enhance the output performances of MMCs containing low numbers of SMs, an improved predictive NLC (I-PNLC) method combining NLC and model predictive control (MPC) is proposed, where the output and circulating currents are regulated with the corresponding predicted references, and the output voltage is controlled by the added voltage correction. The proposed I-PNLC not only reduces the output current and voltage total harmonic distortion (THD) considerably but also avoids additional complexity in the control system design. The results of simulations and an experiment are presented to verify the proposed approach, in addition to a comparison of the evaluations of conventional NLC methods.

phase-shifted and level-shifted carriers (PSCs and LSCs) are the two main realizations for MMCs [22]- [25]. Owing to merits, such as low total harmonic distortion (THD) in the output voltage, PWM is primarily used in medium-voltage applications, where the MMCs contain a few SMs. However, these PWM methods have some limiting features, such as high switching frequencies, high switching losses, and complicated implementation processes, in addition to unsatisfactory transient performances [26]- [28]. Furthermore, when the numbers of SMs increase, the PWM methods require extensive hardware resources for implementation. This is the same problem in the model predictive control (MPC) despite the MPC method offers an excellent dynamic performance and straightforward implementation [29]- [31].
Meanwhile, the conventional nearest-level control (NLC) method offers simple implementation and low switching frequency characteristics regardless of the number of SMs [32], [33], which render the NLC the most practical modulation method for MMCs. Unfortunately, conventional NLC techniques generate lower output performances than the PSC PWM method with a low number of SMs, as applied in medium-voltage applications. Furthermore, a large voltage ripple of the corresponding SM capacitor and high root-mean-square (rms) value of the circulating current are other problems in the conventional NLC method. Therefore, to achieve adequate output quality, the conventional NLC method is primarily used in high-voltage applications when the MMC contains a lot of SMs.
In an effort to further enhance the output current and voltage harmonic characteristics, one upper SM and one lower SM were operated in the PWM condition in [34] to increase the resolution ratio of the staircase waveform. This hybrid modulation lowered the harmonics and improved the THDs in the output currents and voltages. However, the voltage levels still remain similar to those of the conventional NLC method, the modular characteristic is eliminated, and the assembly is impractical. The level-increased NLC method presented in [35] used the round 0.25 (x) function instead of the traditional round 0.5 (x) function, where the decimal fraction of x is rounded to the next higher integer when it exceeds 0.25 or rounded down to the nearest integer otherwise. This is equivalent to adding an offset to the arm voltage references. However, the average number of inserted SMs is not constant at N , resulting in changes to the average SM capacitor voltages. To address this problem, an improved level-increased NLC was introduced in [36] that changed the offset value twice within a fundamental period and allowed maintaining the average number of inserted SMs at N ; hence, the average voltage of the SM capacitors did not deviate. The levelincreased NLC improved the output voltage performance by increasing the output voltage level; however, the circulating current was not suppressed, and the improved level-increased NLC was based on changing the offset phase to regulate the circulating current. The NLC approach in [37] included an additional second-order harmonic control term with the references of the upper and lower arm voltages. The low-frequency circulating current components are eliminated, but the efficiency of this scheme was affected by the sampling time and magnitude of the harmonic control term.
In [38], a limit controller was used to regulate the circulating current, and the limit controller modified the number of inserted SMs from the conventional NLC method to decrease the circulating current ripple. However, this adjustment to the number of SMs might degrade the output voltage performance. Another NLC approach [39] used deadbeat control to reduce the circulating current peak-to-peak value. A recent NLC method proposed in [40] defined the number of inserted SMs according to the output voltage level selection condition and circulating current regulation, thereby significantly improving the output performance and circulating current controllability. Unlike the previous NLC methods, the predictive NLC (PNLC) method, presented in [41], achieved the current-control objectives using the corresponding predicted references. The PNLC method is independent of the number of SMs and inherits the combined benefits of the predictive control and NLC methods. However, the inserted SM number in the conventional PNLC was according to the difference between the predicted reference and measured values, resulting in a non-nearest level or undesirable level transitions. Additionally, the staircase approximation error due to the voltage references in real applications is a discrete-time quantized signal that might produce undesirable level transitions. These undesirable level transitions increase the dv/dt of the output voltage, causing undesirable transitions between neighboring output voltage levels, which could cause voltage and current distortions and increase the corresponding THDs.
To resolve this problem and enhance the output performance of the MMC, the effective improved PNLC (I-PNLC) approach is proposed in this paper. Based on the analysis of the conventional PNLC and MPC, the principle and implementation of the proposed I-PNLC are described. First, the conventional PNLC method is implemented to define the temporary numbers of inserted SMs in the upper and lower arms. To avoid delays due to even one sampling instant in any digital control system, which might deteriorate the performance of the control system, a delay compensation technique is applied. Second, a predefined condition for output voltage correction is generated; this corresponding condition leads to possible combinations of the inserted SM numbers in the upper and lower arms. To select the optimal number of inserted SMs in the upper and lower arms from all possible combinations, the MPC technique is employed using a simple cost function. The proposed I-PNLC method enhances the output performance with low corresponding THDs compared with the conventional NLC and PNLC methods and regulates the other control objectives well under both low and fundamental modulation index operations. The efficacy of the proposed I-PNLC approach is carefully validated by simulations and experiments; moreover, the conventional NLC and PNLC methods, and various control schemes are also realized for comparison purposes. The remainder of this manuscript is organized as follows. The mathematical models of the single-phase MMC and conventional NLC methods are discussed in Section II. Section III introduces and analyzes the proposed I-PNLC method. The simulations and experimental validations are presented in Section IV, and the conclusions are presented in Section V.

A. MATHEMATICAL MODEL OF MMC
The configuration of the one-phase leg of the MMC is illustrated in Fig. 1(a). The two arms are called the upper and lower arms, as shown. One arm comprises an arm inductor L a and N series-connected half-bridge SMs, and each SM is formed using two series insulated gate bipolar transistors and a capacitor, as shown in Fig. 1(b); here, v u and v l are the output voltages of the upper and lower arms, respectively, and i u and i l represent the upper and lower arm currents, respectively, with i o being the output current and V dc the dclink voltage.
The mathematical equations governing the dynamic behavior of the MMC are obtained using Kirchhoff's voltage law as follows: The upper and lower arm currents can be expressed from Fig. 1(a) as where i circ is the circulating current that is calculated as Adding (1) and (2), and subtracting (1) from (2), the dynamic behavior of the MMC can be expressed as

B. CONVENTIONAL NLC AND PNLC METHODS
The control structure of the conventional NLC approach is illustrated in Fig. 2(a). The upper arm voltage reference v * u and lower arm voltage reference v * l are divided with the nominal value of the SM capacitor voltage V * C ; the inserted SM numbers associated with the nearest voltage levels are generated using the round 0.5 (x) function. A voltage sorting algorithm is then employed to balance the capacitor voltage and produce the switching signals from the generated SM number. The inserted SM numbers in the upper and lower arms can be expressed as where To facilitate understanding, an example of the arm voltage reference and its corresponding output voltage for an SM number of seven (N = 7) is depicted in Fig. 3 It should be noted that the conventional NLC has the most straightforward implementation, along with a reduction in the switching losses, compared with other carrier-based modulation techniques. However, the conventional NLC exhibits the poorest output performance, with high THD in output current and voltage. Furthermore, the conventional NLC method causes high amplitudes of the circulating current and capacitor voltage ripples. Therefore, the conventional NLC method is recommended for use in an MMC containing a relatively high number of SMs to obtain adequate output performance.    The conventional PNLC method inherits the benefits of predictive control as well as the NLC approach, as presented in Fig. 2(b). Instead of using the conventional upper and lower arm references, the optimal upper and lower arm voltages are generated by applying the predicted output and circulating current references. The model of the output and circulating currents in the discrete-time domain are respectively deduced from (6) and (7), based on Euler approximation [42], as +i circ (k) .
The optimal voltages corresponding to the upper and lower arms are deduced from (12) and (13) by replacing i o (t + T s ) and i circ (t + T s ) with their corresponding reference values i * o (t + T s ) and i * circ (t + T s ), respectively. Thus, the optimal upper and lower arm voltages can be expressed as where The final numbers of SMs in the upper and lower arms are generated in a manner similar to the conventional NLC using the round 0.5 (x) function. However, unlike the conventional NLC, the total SM numbers in the upper and lower arms are not always equal to N but vary among N , N − 1, and N + 1. As shown in Fig. 3(b), the vertical symmetry of the resulting steps v round u and v round l are disrupted, thereby causing a misalignment of the level transitions. This results in 2N + 1 output voltage levels with reduced step heights of 0.5V * C via 2N + 1 PWM. Therefore, in addition to the regulation of the output and circulating currents, the output voltage levels are increased to 2N + 1, resulting in improved output performance compared with that of the conventional NLC approach.
Nevertheless, the number of inserted SMs in the conventional PNLC is selected based on the difference between the predicted references and values of the output and circulating currents, which result in non-nearest or undesirable level transitions and staircase approximation errors. These undesirable level transitions increase the dv/dt in the output voltage, causing undesirable transitions among the adjacent output voltage levels, which could lead to voltage and current distortions and increase the corresponding THDs.

III. PROPOSED I-PNLC METHOD
To enhance appropriate output performance of the MMC, the I-PNLC is proposed herein as a modification of the conventional PNLC method. The entire I-PNLC scheme is outlined in Fig. 4. A substantial time delay exists unavoidably in any digital control system, which might deteriorate the operation of the system. Thus, for effective practical implementation of the I-PNLC, delay compensation techniques such as in [43], [44] should be applied by shifting the model in (12) and (13) forward by one-step as follows: The optimal upper and lower arm voltages at the k + 1 sampling instant can be obtained from (18) and (19) by replacing i o (k + 2) and i circ (k + 2) with their respective reference values i * o (k + 2) and i * circ (k + 2). Accordingly, the optimal upper and lower arm voltages are derived as where The temporarily inserted SM numbers in the upper and lower arms are defined as These temporarily inserted SMs in the upper and lower arms N * u(l)_temp are generated using (24) and (25), similar to the conventional PNLC. However, these N * u(l)_temp are not the final values, but are modified to enhance the output current and voltage qualities without affecting the circulating current controllability. To solve the undesirable-level problem, the temporarily inserted SMs in the upper and lower arms N * u(l)_temp are adjusted according to the differences between the previous output voltage levels level_old and temporary output voltage levels at the current sampling instant level_temp.
where N * u_final_1 and N * l_final_1 are the final numbers of inserted SMs at the previous sampling instant.
To guarantee smooth transitions among the neighboring output voltage levels, the absolute value of the difference between the previous and current output voltage level should be less than or equal to one. Therefore, three conditions regarding level are generated, as shown in Fig. 5. For instance, if level > 1, instead of using the temporary SM numbers directly in the upper and lower arms, as acquired using (24) and (25), respectively, N * u_temp and N * l_temp are modified by adding one to N * u_temp or subtracting one from N * l_temp . Two possible combinations of inserted SMs in the upper and lower arms (M u1 = N * u_temp +1, M l1 = N * l_temp and M u1 = N * u_temp , M l1 = N * l_temp − 1) are thus generated. These two combinations can result in changes to the output voltage levels, which decrease the differences between the previous and generated output voltage levels.  To guarantee circulating current controllability, the changes in N * u_temp and N * l_temp are followed by an analysis, as in [42]. The optimal inserted SM number needs to be selected from among possible combinations M u(l)1 or M u(l)2 . The MPC technique is employed using a simple cost function J , which contains the output and circulating current terms.
where λ is a weighting factor of the cost function that is obtained using the method in [44], [46], resulting in λ = 0.05. The flow chart of the MPC part is depicted in Fig. 6(a). The final acquired number of inserted SMs in the upper and lower arms N * u_final and N * l_final are applied to the voltage sorting algorithm [20] to balance the capacitor voltages, as shown in Fig. 6(b). The output signals are generated using the arms' current directions and the sorted capacitor voltages. When the arm current is negative (i.e., the capacitor is discharged), the SMs with the highest voltages are inserted; conversely, the SMs with the lowest voltages are inserted for positive arm currents.
Compared with the conventional control schemes, the proposed I-PNLC achieves better output performance by limiting the output voltage level transitions to one to eliminate the undesirable levels. The control of the circulating current is guaranteed via the MPC technique to select the optimal SM numbers in the upper and lower arms from among the two possible combinations. Compared with the conventional PNLC, although the MPC part is added to the control, the additional number of cost function evaluations is only two for each sampling instant. Hence, the computational load is not heavy.

A. SIMULATION RESULTS
Simulations were realized using the PSIM software to assess the suitability and efficacy of the proposed I-PNLC method. The single-phase MMC in the simulation contains seven SMs  per arm (N = 7), along with the parameter configuration given in Table 1. For a full assessment, comparisons between the proposed control scheme as well as the conventional NLC and PNLC methods, the level-increased NLC with circulating harmonic current suppression based on deadbeat control approach in [39], and the reduced computational burden MPC approach in [45] were obtained via simulations. The sampling frequency exerts a significant impact on the control performance of predictive control. A high sampling frequency enables obtaining high performance of the system but requires a fast control processor to ensure large numbers of needed calculations. This leads to increased system cost, which poses a challenge for practical implementation in industrial applications. Alternatively, the performance of the system deteriorates with a small sampling frequency. Therefore, the sampling frequency was set to 10 kHz in both the simulations and experiments, which is suitable for the output performance of the system and the clock frequency of a digital signal processor (DSP). Figs. 7(a)-(e) illustrate the simulated results of the output current and voltage under steady-state operation using the conventional NLC, conventional PNLC, the level-increased NLC with circulating harmonic current suppression based on deadbeat control [39], the reduced computational burden MPC [45], and proposed I-PNLC methods, respectively. With reference to Fig. 7(a), the output current obtained by the conventional NLC method contains evident distortion, which results in a non-smooth sinusoidal waveform. Meanwhile, it can be seen that there are eight levels (N + 1) in the output voltage. The corresponding THDs of the output current and voltage are 3.58% and 9.15%, respectively. Compared with the conventional NLC scheme, the THDs of the output current and voltage yielded by the conventional PNLC are reduced to 1.21% and 8.7%, respectively. The output current is thus well regulated with the conventional PNLC. Although the number of levels of output voltage from the conventional PNLC increases to fifteen (2N + 1), the corresponding THD is still relatively high because of the generation of undesirable output level transitions, resulting in high dv/dt and high harmonic component magnitudes. Meanwhile, the level-increased with circulating harmonic current suppression based on deadbeat control produced the lowest THD of the output voltage at 6.0% since the magnitude of high-frequency components in output voltage is low. The corresponding output current has a sinusoidal form with corresponding THD at 1.98%. The reduced computational burden MPC method has the quite same output performance as the conventional PNLC scheme with a slight difference between THDs of output current and output voltage. However, the output current and voltage acquired by the proposed I-PNLC are significantly improved compared with the two conventional schemes and approaches in [39] and [45]. The corresponding THDs of the output current and voltage are considerably low at 1.04% and 6.47%, respectively. It can be seen apparently that the output current is well controlled with a sinusoidal wave, whereas the output voltage contains fifteen (2N + 1) levels without any undesirable level transitions. The comparison of the normalized output voltage levels between the conventional PNLC and the proposed I-PNLC is shown in Fig. 8. It is observed that the undesirable level transitions from the conventional PLNC, represented by the red lines, are eliminated completely.
Figs. 9(a)-(e) present the waveforms of the SM capacitor voltages and circulating currents obtained by the conventional NLC, conventional PNLC, the level-increased NLC with circulating harmonic current suppression based on deadbeat control, the reduced computational burden MPC, and proposed I-PNLC approach, respectively. The SM capacitor voltage deviation obtained via the conventional NLC, as shown in Fig. 9(a), is notably large owing to unregulated circulating currents, resulting in low-frequency circulating current components, especially the second harmonic component. This also causes high rms values of the circulating currents (approximately 66.24 A). Meanwhile, the SM capacitor voltages obtained by the remaining approaches are maintained close to the nominal values of 1 kV for both cases, with ignorable deviations. Furthermore, the lowfrequency components in the circulating current from both PNLC schemes, the level-increased NLC with circulating harmonic current suppression based on deadbeat controller, and the reduced computational burden MPC are entirely removed, whereas the magnitudes of the remaining highfrequency components are low, as described in Figs. 9(b) -(e). The rms values of circulating current from the four control schemes are almost the same at approximately 38 A with a slight difference in peak-to-peak values. This means that the proposed I-PNLC does not deteriorate the circulating current controllability compared with the conventional PNLC and other methods, whereas the output current and voltage are significantly improved.
The dynamic performances of the five control schemes are shown in Figs. 10(a)-(e). The MMC was first controlled to generate 110 A of output current, equivalent to a modulation index of 0.6 (M = 0.6). At t = 0.3s, the modulation index increased to 1 (M = 1). First, it can be seen that under lowmodulation-index operation, the output currents obtained by the conventional PNLC, the level-increased NLC with circulating harmonic current suppression based on deadbeat controller, the reduced computational burden MPC, and proposed I-PNLC have higher qualities than that of the conventional NLC method, as depicted in Figs. 10(a)-(e). The voltage levels obtained by the five control schemes are increased, equivalent to the rise of the modulation index. Meanwhile, the SM capacitor voltages are maintained at nominal values, with lower deviations, and the magnitudes of the circulating currents are reduced as well. It can be apparently observed that the conventional NLC method exhibits the poorest dynamic performance for the circulating current, as seen in Fig. 10(a). The circulating currents obtained by the conventional NLC method presents a considerably high peak-to-peak value after the change to the modulation index, compared with the result under steady-state operation in Fig. 9(a). Nevertheless, the conventional PNLC, the level-increased NLC with circulating harmonic current suppression based on deadbeat controller, the reduced computational burden MPC, and proposed I-PNLC show better dynamic performances, where the circulating currents are tracked rapidly with the changes to the reference circulating current without any overshoots.

B. EXPERIMENTAL RESULTS
A downscaled single-phase MMC prototype with parameters as given in Table 2 was setup under laboratory conditions, as presented in Fig. 11(a), to confirm the proposed analysis and control method. Fig. 11(b) shows a photograph of the VOLUME 9, 2021 MMC circuit and control board hardware. In the following experiment, the conventional NLC, conventional PNLC, and proposed I-PNLC methods are assessed and compared. A DSP TMS320F28335 was employed to implement the control algorithms and generate the output signals. The arm currents and SMs capacitor voltages were sensed using current and voltage sensors respectively and sampled every T sp seconds (100 µs).
Figs. 12(a)-(e) show the steady-state performances of the output currents and voltages of the conventional NLC, conventional PNLC, and proposed I-PNLC methods, respectively. The experimental waveforms appear to match the simulated outcomes. In Fig. 13(a), the output currents and voltages THDs are presented. It is observed that owing to the lower SMs compared to the simulations, the THDs of the output currents and voltages from the conventional NLC are high, reaching 8.22% and 18.2%, respectively. The output current in Fig. 12(a) contains considerable distortion, whereas the output voltage comprises four levels (N + 1) with a step size of V * C = 50V, as explained in Fig. 4(a). It can be observed that the harmonic contents of the output voltage from the corresponding frequency spectrum are relatively high, indicating low voltage quality.
The output currents obtained by the conventional PNLC, the reduced computational burden MPC, and proposed I-PNLC are regulated adequately compared with the conventional NLC and the level-increased NLC with circulating harmonic current suppression based on deadbeat control. The corresponding THDs reach 4.08%, 3.05%, and 2.90%, respectively, as illustrated in Fig. 13(b), (d), and (e). Meanwhile, the THD of output current obtained by the levelincreased NLC with circulating harmonic current control based on deadbeat control is relatively high at 6.13%, as shown in Fig. 13(c). Apparently, the output currents obtained from the conventional PNLC, the reduced computational burden MPC and the proposed I-PNLC approach the trend of a sinusoidal waveform better than the conventional NLC and the level-increased NLC with circulating harmonic current control based on deadbeat control. It is observed that the output voltage levels obtained by the conventional PNLC, the level-increased NLC with circulating harmonic current suppression based on deadbeat controller, the reduced computational burden MPC, and proposed I-PNLC increase from four to seven, matching the number 2N + 1. However, it is noted that the output voltage obtained from the conventional PNLC contains large distortions and undesirable level transitions and that the corresponding THD reaches 17.0%. Although this output voltage THD is lower than that of the conventional NLC, it is relatively high, indicating poor voltage quality.
Conversely, the output voltage obtained by the proposed I-PNLC approach presents lower THD at 10.3% (reduced from 43.4% and 39.4% compared with the conventional NLC and conventional PNLC, respectively, and equivalent to the reduced computational burden MPC), as shown in Fig. 13(e). The elimination of undesirable level transitions of the proposed I-PNLC method results in reduced ripple in the waveforms and reduced filtering requirements under the same operating conditions. Furthermore, the application of the proposed I-PNLC results in significantly improved operating characteristics of the MMC compared with the conventional PNLC and especially the conventional NLC method. Equivalent to the simulation results, the THD value of output voltage obtained by the level-increased NLC with circulating harmonic current suppression based on deadbeat control approach is the lowest with 9.43%. However, in comparison with the proposed I-PNLC method, this difference is trivial.
Regarding the behaviors of the SM capacitor voltages, Fig. 14(a)-(e) present the capacitor voltage waveforms of the corresponding upper SM1 and lower SM3 obtained from the conventional NLC, conventional PNLC, the level-increased NLC with circulating harmonic current suppression based on deadbeat controller, the reduced computational burden MPC, and proposed I-PNLC methods, respectively. The capacitor voltage waveforms from the five control schemes are close to the nominal value of V * C = 50V. However, the presence of considerably large ripples in the SM capacitor voltage obtained from the conventional NLC is noticeable owing to the circulating current not being regulated, as shown in Fig.  14(a). Meanwhile, the capacitor voltages obtained from the remaining control schemes are balanced well, with negligible deviations. Similar to the simulation results, the circulating current obtained from the conventional NLC contains lowfrequency components, resulting in high peak-to-peak values, as shown in Fig. 14(a). The conventional PNLC, the levelincreased NLC with circulating harmonic current suppression based on deadbeat controller, the reduced computational burden MPC, and proposed I-PNLC present better circulating current suppression performances. The low-frequency components in the circulating currents from both PNLC schemes are entirely removed, whereas the magnitudes of the remaining high-frequency components are negligible, as depicted in Fig. 14(b) -(e). However, due to the low number of SMs in the experimental MMC prototype, the number of redundant inserted SMs is limited. The level-increased NLC with circulating harmonic current suppression based on deadbeat control uses a deadbeat controller to modify the number of inserted SMs acquired by the method in [39]. When the number of SMs is very low, the modified number of inserted SMs might not be sufficient to regulate the circulating current, resulting in higher peak-to-peak value compared with the PNCL, the reduced computational burden MPC and the proposed I-PNLC approaches, as shown in Fig. 14(c).
Figs. 15(a) -(e) present the dynamic performances obtained from the five control schemes, where the MMC was operated under the step change of the modulation index from 0.5 to 1. Owing to the lack of output and circulating current regulations, the conventional NLC exhibits low dynamic performance compared with both PNLC schemes. Meanwhile, the remaining approaches exhibit better dynamic performances of the output and circulating currents. Furthermore, under low modulation index operation, the output current quality from the conventional NLC and the levelincreased NLC with circulating harmonic current suppression VOLUME 9, 2021  based on deadbeat control are inadequate because the low output voltage level results in high dv/dt, as shown in Fig. 15(a) and (c). The output voltage obtained from the conventional PNLC contains several undesirable output voltage transitions, resulting in evident distortion, as shown in Fig. 15(b). On the other hand, the proposed I-PNLC presents a higher  quality of output voltage than the conventional schemes at both low-and high-modulation-index operations. The output voltage correction ensures that there are no approximation errors or undesirable level transitions.
The THDs obtained by the five control schemes, including simulation and experimental results, are summarized in Table 3. Apparently, the experimental results are very identical with those acquired in the simulations. The simulation and experimental results provide satisfactory performance in the sinusoidal output current, sufficient output voltage, the balance of SM capacitor voltages, and suppressed circulating currents for the proposed I-PNLC method under both steady-state and transient-state operations. From the com-parison between the proposed I-PNLC approach and various control schemes, it can be noticed that the proposed I-PNLC is effective and significantly enhances the output performance compared with the conventional NLC and PNLC methods. In terms of the conventional PNLC, the proposed I-PNLC eliminates unnecessary level transitions to get better THDs in output current and output voltage. This results in an ignorable rise in switching transition number and corresponding switching losses compared with the effectiveness of the proposed I-PNLC. Regarding the level-increased NLC with circulating harmonic current suppression based on deadbeat control, the proposed I-PNLC method significantly improve the output current performance, especially on the low number of SMs and low modulation index operation. Although the THD value of output voltage obtained by the level-increased NLC with circulating harmonic current suppression based on deadbeat control is lower than the proposed I-PNLC. This difference is trivial. In comparison with the reduced computational burden MPC, the proposed I-PNLC improves the output performance not too much. However, The computational burden of the proposed method is better than the reduced computational burden MPC, where the number of control actions of the proposed method is only two per sampling instant compared with five. Moreover, the number of control actions of the method in the reduced computational burden MPC increases when the number of SMs increases.

V. CONCLUSION
In MMC systems, the output current and voltage, in addition to the circulating current and capacitor voltage balancing control, should always be achieved simultaneously. This paper presents an I-PNLC method combining the PNLC and MPC approaches. The added output voltage correction by the MPC enhances the output voltage by altering the inserted SM numbers appropriately from the PNLC scheme. Owing to this output voltage correction, the approximation errors and undesirable voltage level transitions are eliminated, resulting in reduced THDs of the output current and voltage. The proposed I-PNLC method was verified through simulations and experiments, which confirm the excellent overall performance compared with the conventional NLC control schemes.