Design and Implementation of Multilevel Inverters for Electric Vehicles

The efficient and compact design of multilevel inverters (MLI) motivates in various applications such as solar PV and electric vehicles (EV). This paper proposes a 53-Level multilevel inverter topology based on a switched capacitor (SC) approach. The number of levels of MLI is designed based on the cascade connection of the number of SC cells. The SC cells are cascaded for implementing 17 and 33 levels of the output voltage. The proposed structure is straightforward and easy to implement for the higher levels. As the number of active switches is less, the driver circuits are reduced. This reduces the device count, cost, and size of the MLI. The solar panels, along with a perturb and observe (P&O) algorithm, provide a stable DC voltage and is boosted over the DC link voltage using a single input and multi-output converter (SIMO). The proposed inverters are tested experimentally under dynamic load variations with sudden load disturbances. This represents an electric vehicle moving on various road conditions. A detailed comparison is made in terms of switches count, gate driver boards, sources count, the number of diodes and capacitor count, and component count factor. For the 17-level, 33-level, and 53-level MLI, simulation results are verified with experimental results, and total harmonic distortion (THD) is observed to be the same and is lower than 5% which is under IEEE standards. A hardware prototype is implemented in the laboratory and verified experimentally under dynamic load variations, whereas the simulations are done in MATLAB/Simulink.


I. INTRODUCTION
With the demand for an increase in the requirements of highpower quality in industrial applications and solar PV systems, the conventional inverters in meeting the desired conditions like a pure sine-wave output and less harmonic distortions is a challenging task.The multilevel inverters receive more attention in reaching the desired requirements and acts as an alternative in delivering a quality of power.It provides several advantages such as reduced device count, operates in The associate editor coordinating the review of this manuscript and approving it for publication was Sudhakar Babu Thanikanti .low switching frequency, reduced dv/dt stress, less harmonic distortions, etc. [1].The recent multilevel inverter topologies comprise a smaller number of components used in the circuit compared with the conventional inverters such as flying capacitor type (FC) [2], cascaded H-bridge type (CHB) [3], and the neutral point clamped type (NPC) [4].The number of components in the circuit is directly proportional to the number of levels in MLI, which increases cost and complex structure [5].In both the FC MLI and NPC MLI, the capacitor voltage balancing is a challenging task with which these are limited to five-level and unable to cascade.This lowers the output voltage to half of the input voltage, providing a high switching frequency with more losses [6].A wide range of research is reducing the components of MLI, and several topologies are proposed based on the various levels which are having their challenges [7], [8].
In the recent past, various MLI topologies without association with the conventional three types of classification are reported in [9]- [13].Significantly, the sub multilevel converter configurations are proposed in [15].In [10], a basic level topology is reported, where multiple dc voltages are required.The coupled inductor-based topologies are documented in [9] and [11].These architectures are simple but extending to higher levels is a challenging task.A novel MLI topologies based on switched-capacitor (SC) with boost techniques are presented in [12] and [13] where the output voltage levels are limited to 5, 7, and 13, respectively.The MLI topology proposed in [14] can be extended to higher levels.The utilization of several switches and devices increases the cost and size of the system.
Concerning the switched capacitor (SC) technique, a new MLI topology with a multilevel converter and a full bridge is represented in [16].A five-level single phase inverter with a full bridge makes up two diodes, and a single switch is presented in [17] which provides five levels in its output, and its circuitry limits the extension of higher levels.The SC-based MLI topology reported in [18] makes up a frontend SC, and full-bridge backend, the control complexity, and more device count limit the application.As the carrier frequency provides the switching frequency, a high switching loss is irresistible for providing the high-frequency output [51].A boost MLI with a partial charging technique of SC theoretically can able to extend the number of output voltage levels.The control complexity is high in implementing partial charging [12].Hence, designing an SC-based MLI with highfrequency output, fewer harmonics, and high efficiency is a challenging task [19].The high-frequency output applies for implementing circuits in electric vehicle (EV) since the weight and size of the system is less [20].
The photovoltaic power generation comprises solar PV panels, where the output of a solar panel is fed to DC link through a DC-DC converter.The voltage from a DC link is fed to the DC-AC inverter and to load [21].The output of solar PV is not constant, and it changes according to the solar irradiation and temperature [22].Therefore, for an efficient operation of PV panels even under various climatic changes, it is essential to extract maximum power from the PV module, admitted to being Maximum power point tracking (MPPT) [23].Whenever the MPPT exists in a system, a DC-DC converter plays a significant role in handling maximum power as it works with the duty cycle change [24].
For a PV fed inverter, in producing a stable DC voltage, there is a need for a control technique.A standard PI controller realized in the standalone PV system to select a proper duty cycle of the DC-DC converter by comparing the converter output with reference [25].It is not desirable to have control over the DC-DC converter with the MPPT technique, and hence various topologies are proposed to solve this issue for the standalone solar system.In the recent past, several advanced techniques like artificial intelligence (AI), practical swarm optimization (PSO), fuzzy and genetic algorithm (GA) to have an auto-control regarding the training data to regulate voltage [26].The selection of the MPPT technique for a suitable application is an astonishing task where every method has its own merits and demerits.For example, hill climbing (HC), perturb, and observing (P&O) and are widely used MPPT methods because of their simple implementation.Under partial shading conditions, the conventional methods like fuzzy, P&O, INC algorithms cannot extract global MPP (GMPP) [27].Many works of literature have been implemented MLI with DC link with MPPT, where the control of outputs can be done by the load [28] or under steady solar irradiance [29].MPPT consistently changes the energy of the solar panel to operate at the maximum point of the power, which depends on temperature, load, and solar irradiance.Both solar irradiance and temperature change during day time for climatic conditions and depending on the season.So, it is vital to track all these parameters and get maximum powerpoint.
In this paper, a solar PV system is implemented using a 53level multilevel inverter integrated with a single input, and multiple output DC-DC boost converter is presented.P&O powered MPPT technique is implemented in the proposed system to extract peak energy from the solar panels.DC voltage from the between the solar panels fed to the single input and multiple output boost converter where the voltage gets boosted to the desired level and provided to the 53-level inverter.The SC units are cascaded to achieve 17, 33 levels of output voltages.Performance of these MLIs based on many such parameters like device count, power losses, efficiency, THD is compared with various MLI topologies and represented.The implemented system is tested in MAT-LAB/Simulink, whereas it is tested experimentally with a hardware setup.
The organization of the paper is: Modeling of PV and single input and multiple output DC-DC boost converter is represented in section-II, the proposed 53-level MLI modeling with the SC units cascade combinations to get 17 and 33level MLIs along with the power loss calculations are shown in section III.The simulation and experimental results are explained in section IV.Several comparisons with the same and distinct levels of MLI topologies are presented in section-V.Finally, conclusions are made in section VI.

II. MODELLING OF PV AND DC-DC BOOST CONVERTER A. MODELLING OF SOLAR PV
The modeling of a solar cell is an important segment of analyzing a solar PV system.The overall proposed circuit comprises solar panels, a three-level DC-DC boost converter fed to 53-level MLI shown in Figure 1.The solar PV can be modeled with three categories such as an equivalent circuit with current-voltage (I-V) and power-voltage (P-V) characteristics, the effect of solar irradiance and temperature, and  the partial shading condition is taken into consideration.PV resembles two words photo and voltaic: photo represents the photonic energy and voltaic represents the electrical energy, which implies that the energy conversion from photonic energy into electrical energy [30].The combination of a solar array is of various types of modules, where each module comprises solar cells.This comprises of p-n semiconductor diodes [31].The designed solar PV has a behavior of changing its output with the variation of temperature and climatic conditions [32].Therefore, the factors in modeling a solar PV are represented below:

1) SOLAR CELL: EQUIVALENT CIRCUIT AND I-V CHARACTERISTICS
The solar cell comprises internal resistance R SE and R SH connected to the diode in series and parallel combination, known to be an equivalent circuit shown in FIGURE 2.
V PV and I PV are the output voltage and current of a solar cell, respectively.These are got from the series and parallel connection of several PV modules shown in equation (1), where N SE and N SH are the number of PV cells in series and parallel connection.R SE is the series resistance, and R H is the parallel resistance.A is the ideality factor of a semiconductor device.K is Boltzmann's constant (1.3806503 × 10 −23 J/K), T is 'he temperature.I p is the current produced and is depends on the irradiation and temperature shown in equation ( 2) where I SK−STM is a short-circuited current at standard testing cases (STM), Ki is the SCC coefficient, G (W/m 2 ) is the irradiance on the surface of the cell, GSTM (1000W/m 2 ) is the irradiance at STM, and the cell temperature is T STM [33].
where V OK−STM is an open-circuited voltage at the standard testing case, K OV represents the open-circuit voltage coefficient, V Sth is solar cell thermal voltage.
I-V/P-V curves represent the characteristics of a solar cell is shown in FIGURE 3 [4].It is clear from the curve there is instability for the operating point of a PV; it varies continuously from null to open-circuit voltage.In this process, there is a single point that provides peak power for the design of solar PV at various irradiance.Here, the respective voltage and currents are V MPP , I MPP shown in Figure 3.
The values of current and voltage got from the solar PV depend on irradiance, temperature, number of series, and parallel connected strings.So, it is required to choose the solar panel wisely.In this paper, the 1Soltech 1STH-215-P panel is chosen from the list of given solar modules data in MATLAB with 2 series and parallel connected modules per string.The specifications of the selected solar panel are described in table 1 and the readings in the table are given for 1 parallel string and 1 series-connected module with a solar irradiance of 1000 W/m 2 and 250 o C temperature.

2) IRRADIANCE AND TEMPERATURE EFFECT
The solar PV output continuously varies with variation in climatic changes [34].As the solar irradiance confides on the incidence angle of sun rays, this effect forces the I-V/P-V characteristics to change.The output current I PV varies with the variation of sunray incidence, making V PV constant and V PV also shifts its magnitude, making I PV constant [34].Three factors are influencing the variation in temperature of a solar PV: The heat dissipated on its own during the functioning of PV, for the infrared wavelength started, which is a worn on the cell and the gradual increase in the sunbeam intensity [26].The V OC and I SC are measured based on the equations ( 5) and ( 6) at variable irradiance.
From the above equations, the temperature coefficients are a 1 and a 2 of the PV cell, respectively [35].V ′ OC and I ′ SC are the reference parameters at solar intensity G' and temperature T ′ .
As the variations of climatic conditions are specific, it affects the output voltage and currents.At any point during the operation of solar PV, the maximum extraction of power can be done.This can be possible with an efficient MPPT technique that tracks the irradiation and temperature and provides a constant voltage at the output.

3) PARTIAL SHADING EFFECT
Apart from the temperature and irradiance conditions, a partial shading case is also a challenging task for the MPPT technique in achieving maximum power.This partial shade occurs with mists, consecutive structures, trees, etc. [36].According to equation (2), the photocurrent I ph gets reduced with low insolation.With series-connected PV modules, the current is the same in all cells.But in this case, the shaded cell goes to a breakdown, and instead of providing the energy, this acts as a load because of the weakening of photocurrent.

B. MPPT CONTROLLER
The operating of solar PV is to extract the maximum power from the PV module is an MPPT controller.During all the disturbances mentioned above, if the controller can able to operate efficiently in tracking and to provide peak power from the solar panels, the efficiency and life span of the solar PV gets increased.This can be achieved by sinking the solar source to the load for various climate conditions to produce maximum power.There are two ways to extracting the maximum power from a solar panel.They are Mechanical and electrical tracking.With mechanical tracking, the solar panels change their direction depends on the climatic variation patterns.This includes seasonal climate changes for several months.With electrical tracking, the I-V curve is forced to locate the point of maximum power in the operation of the PV array [37].The MPPT controller is an internal part of the system which feeds the maximum power to load (batteries/motors).
For tracking maximum power during the operation of the PV module, a suitable algorithm is to be used.This can be seen in the P-V graph of a solar cell.There are many such methods to track the maximum power such as incremental conductance, perturb and observe, genetic algorithm, fractional open-circuit voltage, etc.In this paper, the perturb and observe algorithm it has many advantages.It is easy to implement using various controllers such as Arduino, microcontroller, etc.The maximum power point determination speed can be controlled by varying the perturbation value.The P&O algorithm is shown in the values got at kth instant.f) In the PV curve of a solar panel, on the right side, the slope is negative i.e., (dP/dV<0) whereas on the left side, the slope is positive (dP/dV>0).Therefore, the lesser duty cycle occurs on the right side of the curve and the high-duty occurs on the left side of the curve.g) Based on the polarity of the slope after subtraction, the algorithm decides the change in the duty cycle.The solar panel is designed with a power of 215W; the respective parameters and their specifications are shown in TABLE 1.

C. DC-DC BOOST CONVERTER
A single input multiple output DC-DC boost converter interfaced in between the solar panels and the proposed inverter is shown in Figure 1 [38].This converter provides three isolated dc sources in the ratio of 4:1:3:9.The converter feeds on a single solar PV to eliminate the unequal voltages along with the variations in the step size based on several climatic conditions.
The magnitude of the inductance can be calculated using the relation: where V dc is the input dc voltage, m is the modulation index, and fs is the switching frequency, Ir is the ripple current, a is the overloading factor which is usually 1.25.
The value of capacitance can be calculated using the relation: where I dc is the dc current, fs is the switching frequency, r is the ripple voltage, V dc is the input dc voltage, D is the duty cycle.
The duty cycle of the converter can be calculated using the following relation : The simulation and experimental results are shown in FIG-URE 5 and FIGURE 6, respectively.The specifications of the boost converter are represented in Table II.

III. PROPOSED ASYMMETRICAL 53-LEVEL MLI
The proposed 53-level MLI is designed and implemented with a switched capacitor approach.SC is incorporated at the front end along with the H-bridge.It acts as an individual energy storage system for the proposed MLI.Hence it is essential to select the specific value of the capacitance, and the value depends on the operating frequency, load current     in FIGURE 7(a) & FIGURE 8(a), under optimal conditions, during each half-cycle, the capacitor C is charged through S 2 switch during V 0 = ±Vc 1 .
The discharging of the capacitor C is started when the switch S 1 is in conduction at the front end of the proposed MLI topology.During the discharging period, the diode D and switch S 2 gets turned off.V 1 and V C1 supply energy to the load and the respective maximum load current is known where The discharging period can be used for obtaining the optimum value of SC for obtained ripple voltages.The simulation output waveform shown in FIGURE 8(b).
Let Q C be the charge released by C1 during the period, then where td1, td2 is the period of discharging, I 0 is maximum output current, fs is the fundamental frequency, and ϕ is the phase difference among the voltage and current.VC is the ripple voltage and can be calculated using the angles computed using where θ is the angle where the capacitor discharges and π θ is the angle where the capacitor is discharging stops.

A. 17-LEVEL MLI
A 17-level MLI is designed with the two SC units connected in cascade with a smaller number of components is shown in FIGURE 9.The proposed MLI topology comprises 10 controlled switches with two asymmetric DC sources with the  III.Few modes of operation, along with the switching pulses, is shown in FIGURE 10, and the expected output waveform is represented in FIGURE 11.
The developed 17-level MLI is operated in various modes of operation shown in TABLE III.In mode-1 operation of the circuit, the switches S A , S 5 , S D , S 3 , S 1 turn on forming a load current path, where V 1 , V C1 , V 2, and V C2 sources act in the circuit and produce a voltage of 50V, 150V, 50V, 150V respectively to get a maximum voltage of 400V.The respective switching pulses, switching states, and current paths are represented in Table III.In mode-2 operation, the switches D 1 , S 5 , S D , S 3 , S 1 turn on where V 1 , V 2, and V C2 sources act in the circuit and produce a voltage of 50V, 50V, and 150V respectively and get a voltage of 7V dc which is equal to 350V.In mode-3 operation, the switches S D , S 3 , S 6 , S 5 turn on forming a load current path where V 2 , V C2 sources act in the circuit and produce a voltage of 50V and 150V respectively and get a voltage of 6V dc equal to 300V.In mode-4 operation, the switches S A , S 5 , D 2 , S 3 , S 1 turn on with the voltages V 1 , V C1, and V 2 sources act in the circuit and produce a voltage of 50V, 150V, and 50V respectively and get a voltage of 5V dc which is equal to 250V.In mode-5 operation, the switches D 1 , S 5 , D 2 , S 3 , S 1 turn on with the voltages V 1 and V 2 sources act in the circuit and produces a voltage of 50V and 150V respectively and get a voltage of 4V dc equal to 200V.In mode-6 operation, the switches D 2 , S 3 , S 4 , S 5 , turn on with the voltage V 2 source act in the circuit and produce a voltage of 50V and get a voltage of 3V dc which is equal to 150V.In mode-7 operation, the switches S A , S 5 , S 6 , S 1 , turn on with the voltages V 1 andV C1 sources act in the circuit and produces a voltage of 50V and 150V respectively and get a voltage of 2V dc equal to 100V.In mode-8 operation, the switches D 1 , S 5 , S 6 , S 1 turn on with the voltages V 1 source act in the circuit and produces a voltage of 50V respectively and get a voltage of V dc which is equal to 50V.In mode-9 operation, the switches S 1 , S 2 , S 3 , turn on with no voltages acts in the circuit and produces a voltage of 0V.Hence the positive cycle is created.The negative cycle is implemented with the negative modes of operation, along with the switching states shown in Table III.Therefore, the 17-level MLI output waveform is achieved with a simulation THD of 4.12% shown in FIGURE 14.The experimental THD is shown in Figure 21 is 4.12%, which is like that of simulation THD.The output waveform for output voltage and currents are shown in FIGURE 12, FIGURE 13, FIGURE 14, and FIGURE 15.
The experimental output voltage and output current are represented in FIGURE 16.The MLI is tested with R-load, and the obtained voltage and currents are 400V and 4A, respectively, and the result obtained is shown in FIGURE 17.For L-load, the experimental result is shown in FIGURE 18, where the voltage and currents are of 400V and 6.8A, respectively.For RL-load, the result is shown in FIGURE 19.For LR-load, the experimental result is shown in FIGURE 20.The complete experimental setup is shown in FIGURE 44.The experimental specifications used in implementing 17level MLI are shown in Table VI.

B. 33-LEVEL MLI
A 33-level MLI is designed with the combination of two 17level MLI units connected with a smaller number of compo-     count level, voltage stress are minimized with this MLI topology.This topology achieves less TSV and is compared with various topologies.The path of the load current through the switches, along with the states of operation, are represented in   TABLE IV.Few modes of operation, along with the switching pulses, are shown in FIGURE 23.
The developed 33-level MLI is operated in various modes of operation shown in TABLE IV.In mode-1 operation of the circuit, the switches S A , S 5 , S D , S 3 , S 7, S E , S 11 , S H , S 9 , S 1 turn on forming a load current path, where V 1 , V C1 , V 2 , V C2 , V 3 , V C3 , V 4, and V C4 sources act in the circuit and produce the voltages of 25V, 25V, 75V, 75V, 25V, 25V and75V respectively to get a maximum voltage of 400V.The respective switching pulses, switching states, and current paths are represented in Table IV.In mode-2 operation,   the switches D 1 , S 5 , S D , S 3 , S 7, S E , S 11 , S H , S 9 , S 1 turn on where V 1 , V 2 , V C2 , V 3 , V C3 , V 4, and V C4 sources act in the circuit and produce the voltages of 25V, 75V, 75V, 25V, 25V and 75V respectively, and get a voltage of 15Vdc, which is equal to 375V.In mode-3 operation, the switches S D , S 3 , S 7 , S E , S 11 , S H , S 9 , S 1, S B , S A , D 1 , S 5 turn on forming a load current path where V 2 , V C2 , V 3 , V C3 , V 4, and V C4 sources act in the circuit and produce the voltages of 75V, 75V, 25V, 25V and 75V respectively and get a voltage of 14V dc equal to 350V.In mode-4 operation, the switches S D , S 3 , S 7 , D 3 , S 11, S H , S 9 , S 1 , S B , S A, D 1 , S 5 turn on with the voltages V 2 , V C2 , V 3 , V 4, and V C4 sources acts in the circuit and produces a voltage of 75V, 75V, 25V, 75V and 75V respectively and get a voltage of 13V dc which is equal to 325V.In mode-5 operation, the switches S D , S 3 , S 7 , S F , S E, D 3 , S 11 , S H , S 9 , S 1, S B , S A, D 1 , S 5 turn on with the voltages V 2 , V C2 , V 4, and V C4 sources acts in the circuit and produces a voltage of 75V, 75V, 75V and 75V respectively and get a voltage of 12V dc equal to 300V.In mode-6 operation, the switches S A , S 5 , S D , S 3, S 7 , S F , S E , D 3 , S 11, D 4, S 9, S 1 , turn on with the voltage V 1 , V C1 , V 2 , V C2, and V 4 sources acts in the circuit and produce a voltage of 25V, 25V, 75V, 75V and 75V respectively and get a voltage of 11V dc which is equal to 275V.In mode-7 operation, the switches D 1 , S 5 , S D , S 3, S 7 , S F , S E , D 3 , S 11, S 4 , S 9 , S 1 , turn on with the voltages V 1 , V 2 , V C2, and V 4 sources acts in the circuit and produces a voltage of 25V, 75V, 75V and 75V respectively and get a voltage of 10V dc which is equal to 250V.In mode-8 operation, the switches D 2 , S 3 , S 7 , S F, S E , D 3 , S 11 , D 4 , S 9, S 1 , S B , S A , D 1 , S 5 turn on with the voltages V 2 , V C2, and V 4 sources acts in the circuit and produces a voltage of 75V, 75V and 75V respectively and get a voltage of 9V dc which is equal to 225V.In mode-9 operation, the switches S A , S 5 , S D, S 3 , S 7 , S 8 , S 9 , S 1 , turn on with the voltages V 1 , V C1 , V 2, and V C2 acts in the circuit and produces a voltage of 25V, 25V, 75V, 75V respectively and get a voltage of 8V dc equal to 200V.In mode-10 operation, the switches D 1 , S 5 , S D , S 3, S 7 , S 8 , S 9 , S 1 , turn on with the voltages V 1 , V 2 , and V C2 acts in the circuit and produces a voltage of 25V, 75V and 75V respectively and get a voltage of 7V dc which is equal to 175V.In mode-11 operation, the switches S D , S 3 , S 7 , S 8, S 9 , S 1 , S B , S A , D 1, S 5 , turn on with the voltages V 2 and V C2 acts in the circuit and produces a voltage of 75V and 75V respectively and get a voltage of 6V dc equal to 150V.In mode-12 operation, the switches S A , S 5 , D 2 , S 3, S 7 , S 8 , S 9 , S 1 turn on with the voltages V 1 , V C1 and V 2 acts in the circuit and produces a voltage of 25V, 25V and 75V respectively and get a voltage of 5V dc which is equal to 125V.In mode-13 operation, the switches S A , S 5 , S 6 , S 7 , S E, S 11 , S 12 , S 1 turn on with the voltages V 1 , V C1 , V 3, and V C3 acts in the circuit and produces a voltage of 25V, 25V, 25V, and 25V respectively and get a voltage of 4V dc which is equal to 100V.In mode-14 operation, the switches D 2 , S 3 , S 7 , S 8 , S 9, S 1 , S B , S A , D 1 , S 5 turn on with the voltages V 2 acts in the circuit and produces a voltage 75V and get a voltage of 3V dc which is equal to 75V.In mode-15 operation, the switches S A , S 5 , S 6 , S 7, S 8 , S 9 , S 1 turn on with the voltages V 1 and V C1 acts in the circuit and produces a voltage 25V and 25V respectively and get a voltage of 2V dc equal to 50V.In mode-16 operation, the switches D 1 , S 5 , S 6, S 7 , S 8 , S 9 , S 1 turn on with the voltages V 1 acts in the circuit and produces a voltage 25V and gets a voltage of V dc which is equal to 25V.Hence the positive cycle is produced.The negative cycle is implemented with the negative modes of operation, along with the switching states shown in Table IV.Therefore, the 33-level MLI output waveform is achieved with a simulation THD of 2.54% shown in FIGURE 26.The experimental THD is shown in FIGURE 32 is 2.54%, which is like that of simulation THD.The output waveform for output voltage and currents are shown in FIGURE 24 and FIGURE 25.The MLI is tested with R-load, and the obtained voltage and currents are 400V and 4A, respectively, and the result obtained is shown in FIGURE 27 & FIGURE 28.For Lload, the experimental result is shown in FIGURE 29.Where  the voltage and currents are 400V and 6.8A, respectively.For RL-load, the result is shown in FIGURE 30.For LRload, the experimental result is shown in FIGURE 31.The complete experimental setup and specifications are shown in FIGURE 44 and Table V.

C. 53-LEVEL MLI
A 53-level MLI is designed with a combination of three SC units connected with a smaller number of components is shown in FIGURE 33.The proposed MLI topology comprises 14 controlled switches with three asymmetric DC sources with the absence of inductors.The three DC sources are of unequal voltage levels formed to be an asymmetrical configuration.Several power quality issues like total standing voltage (TSV), cost factor, and cost per unit with various values of the weight factor, THD, switch count, component count level, voltage stress is minimized with this MLI topology.This topology achieves less TSV and is compared with various topologies.The path of the load current through the switches along with the states of operation are represented in TABLE VI.Few modes of operation, along with the switching pulses are shown in FIGURE 34.The developed 53-level MLI is operated in various modes of operation shown in TABLE VI.In mode-1 operation of the circuit, the switches S E , S 2 , S A , S 7 , S D, S 4 , S 5 turns on forming a load current path, where V 1 , V C1 , V 2 , V C2 , V 3, and V C3 sources act in the circuit and produce the voltages of 15.4V, 15.4V, 46.2V, 46.2V, 138.6V, and 138.6V respectively to get a maximum voltage of 400.4V.The respective switching pulses, switching states and current paths are represented in Table V.In mode-2 operation of the circuit, the switches S E , S 2 , D 1 , S 7 , S D, S 4 , S 5 turn on forming a load current path, where V 1 , V 2 , V C2 , V 3, and V C3 sources act in the circuit and produce the voltages of 15.4V, 46.2V, 46.2V, 138.6V and 138.6V respectively to get a maximum voltage of 385V.In mode-3 operation of the circuit, the switches S E , S 2 , S B , S A , D 1 , S 7, S D , S 4, S 5 turn on forming a load current path, where V 2 , V C2 , V 3, and V C3 sources act in the circuit and produce the voltages of 46.2V, 46.2V, 138.6V and 138.6V respectively to get a maximum voltage of 369.6V.In mode-4 operation of the circuit, the switches S E , S 2 , S A , S 7, D 2 , S 4 , S 5 turn on forming a load current path, where V 1 , V C1 , V 2 , V 3, and V C3 sources act in the circuit and produce the voltages of 15.4V, 15.4V, 46.2V, 138.6V and 138.6V respectively to get a maximum voltage of 354.2V.In mode-5 operation of the circuit, the switches S E , S 2 , D 1 , S 7, D 2 , S 4 , S 5 turn on forming a load current path, where V 1 , V 2 , V 3, and V C3 sources act in the circuit and produce the voltages of 15.4V, 46.2V, 138.6V and 138.6V respectively to get a maximum voltage of 338.8V.In mode-18 operation, the switches D 3 , S 2 , S 3 , S 4 , S 5 turn on where the V 3 source acts in the circuit and produces the voltages of 138.6V and gets a voltage of 9V dc which is equal to 138.6V.In mode-28 operation, the switches D 1 , S 6 , S 5 , S 4 , S 3 turn on forming a load current path where the -V 1 source acts in the circuit and produces the voltage of -15.4V and gets a voltage of -V dc equal to -15.4V.In mode-53 operation, the switches S D , S 3 , S A , S 6 , S E , S 1 , S 8 turn on with the voltages V 1, V C1 , V 2 , V C2 , V 3, and V C3 sources act in the circuit and produce a voltage of 15.4V, 15.4V, 46.2V, 46.2V, 138.6V, and 138.6V respectively and get a voltage of 26V dc which is equal to 400.4V.Hence the positive cycle is produced.The negative cycle is implemented with the negative modes of operation, along with the switching states shown in Table VI.Therefore, the 53-level MLI output waveform is achieved with a simulation THD of 1.41% shown in FIGURE 37. The experimental THD is shown in FIGURE 43 is 1.41%, which is like that of simulation THD.The output waveform for output voltage and currents are shown in FIGURE 35 and FIGURE 36.The MLI is tested with R-load, and the obtained voltage and currents are 400V and 4A, respectively, and the result obtained is shown in FIGURE 38 & FIGURE 39.For Lload, the experimental result is shown in FIGURE 40.Where the voltage and currents are 400V, and 6.8A, respectively.For RL-load, the result is shown in FIGURE 41.For LRload, the experimental result is shown in FIGURE 42.The complete experimental setup and specifications are shown in FIGURE 44 and Table V.

D. TOTAL STANDING VOLTAGE (TSV)
The total standing voltage (TSV) plays a significant role in the selection of switches in the circuit.It is the sum of all blocking voltages for the total number of semiconductor devices in the topology.
The voltage stresses on the bi-directional and unidirectional switches are given as V Sbi = V i and V Suni = 2V i           proposed topology is V o, max = 400V.In the proposed MLI, the voltages are equal for complimentary switches, and all switches are unidirectional.Hence TSV is calculated using the following relation:   For the developed 17-level MLI, TSV can be calculated based on the equation ( 7) and found to be 16V dc.Similarly, for the 33-level MLI and the proposed 53-level MLI, TSV is found to be 50V dc and 30.8V dc, respectively.

E. COST FUNCTION
The cost factor for the proposed 53-level MLI can be calculated using the parameters like several switch counts, source count, total standing voltage, driver circuits count, and using the formula shown in equation ( 14) [37].
where CF is the cost factor, N S is the number of switches, N dk is the gate driver circuit count, N d is the diodes count, N c is the number of capacitors.TSV is the maximum standing voltage for the switches in conduction.TSV pu is the total standing voltage per unit, which is given by where n is the DC sources count in the circuit.α is the weight coefficient which is multiplied with TSVpu.The inverter topology with the absence of diodes and capacitors can be neglected, and the cost function is calculated using the relation.
CF = (S + N dk + αTSV pu ) × n (16)  The value of α is to be considered in such a way that one value is greater than one, and the other is less than one.In this paper, the value of α is realized as 0.5 (<1), and the other value is 1.5 (>1) for the evaluation of the cost function.
The cost-effectiveness of any MLI is calculated with level count (CF/L).This value is to be calculated for both values      used in a circuit.The lesser the value, the fewer components are used, which provides fewer losses and more efficiency.
The component count per level factor F ccl is calculated using the following relation: The component count level factor for the developed 17-level MLI, 33-level MLI, and the proposed 53-level MLI is found to be 1.53, 1.57, and 0.69, respectively.

F. POWER LOSS AND EFFICIENCY
The total losses are divided into conduction and switching losses related to switches.The conduction losses for the switches can be calculated using equation (18).
where V S is the voltage drop of the IGBT switch, and V d is the voltage drop of diodes.R S is the equivalent resistance of the switch, R d is the diodes equivalent-resistance.The generaliseded relation for finding conduction power losses (P cl ) considering the N IGBT switches and N d diodes at t instant of time is given in equation (12).
The switching losses can be calculated from the equation ( 13) where Eon and Eoff are the energy used by the switches.The total power losses (P total loss ) is calculated: P total loss = P cl + P sl (21) The efficiency (η) is calculated using the following relation: η = P out P in = P out P out + P loss (22) where P out and P in are the output and input powers.
The output power can be estimated:

IV. COMPARISON STUDIES
The comparison can be done for the developed 17-level, 33-level, and proposed 53-level MLIs based on the various parameters listed below.In the designed 17-level MLI topology, it is noticed that it is cost-effective as compared with the different recent topologies for both values of α.The proposed MLI is compared with various current topologies considering essential like the number of switches,    The proposed MLI is tested under multiple dynamic load variations.This topology is most suited for renewable energy applications.

FIGURE 1 .
FIGURE 1. Overall structure of the proposed system.

FIGURE 2 .
FIGURE 2. Equivalent circuit of solar cell.

FIGURE 3 .
FIGURE 3. I-V Characteristics of solar cell.

Figure 4 .
The algorithm for Perturb and Observe Technique is: a) Ipv and Vpv values are gathered from PV module.b) Ppv is calculated from Ipv and Vpv.c) Voltage and power values are stored.d) The values are recorded for the next consecutive (k + 1) th instant and repeat step 'a'.e) The values got at (k + 1) th instant are subtracted from

FIGURE 5 .
FIGURE 5.The solar PV and boost converter simulation waveforms.

FIGURE 6 .
FIGURE 6.The solar PV and boost converter experimental waveforms.

FIGURE 10 .
FIGURE 10.Modes of operation of the proposed 17-Level MLI topology.

FIGURE 14 .
FIGURE 14. Simulation output voltage and current waveforms of the 17-Level MLI.

FIGURE 23 .
FIGURE 23.Modes of operation of the proposed 33-Level MLI topology.

TABLE 4 .
Generation voltage levels according to Conduction of Switches of 33 MLI.VOLUME 9, 2021

FIGURE 25 .
FIGURE 25.Simulation output voltage and current waveforms of the 33-Level MLI.
respectively, where i = 1, 2. . . . . .n, and n are complimentary switches count.The maximum output voltage (V o ) for the

FIGURE 34 .
FIGURE 34.Modes of operation of the proposed 53-Level MLI topology.

Figure 46 (
i) Shows the comparison of the cost function for various topologies and found cost-effective.The proposed 53-level MLI is compared with multiple topologies are of different levels, and it is noticed that this topology is cost-effective as compared with the various recent topologies for both values of α.The proposed MLI is compared with multiple current topologies considering essential parameters like the number of switches,

FIGURE 46 .
FIGURE 46.Comparison of various 33-Level MLI topologies.Switches count (b) Gate driver circuits count (c) DC sources count (d) Diodes count (e) Capacitors count (f) TSV Components count per level (h) THD (i) Cost function/Level count.

FIGURE 47 .
FIGURE 47.Comparison of various topologies of MLI with different levels with proposed 53-Level MLI Switches count (b) Gate driver circuits count (c) Number of levels (d) TSV (e) DC sources count (f) Capacitors count (g) Components count per level (h) THD (i) Cost function/Level count.

TABLE 1 .
Specifications of the 215W PV system.

TABLE 2 .
Specifications of the boost converter.

TABLE 3 .
Generation voltage levels according to Conduction of Switches of 17 MLI.
FIGURE 35.Simulation output voltage waveform of the 53-Level MLI.FIGURE 36.Simulation output voltage and current waveforms of the 53-Level MLI.FIGURE 37. Simulation THD.

TABLE 6 .
Generation voltage levels according to Conduction of Switches of 53 MLI.

TABLE 7 .
Cost comparison of various multilevel inverters with proposed 17-Level MLI.

TABLE 9 .
Cost comparison of various multilevel inverters with proposed 53-Level MLI.