Low Frequency Harmonics Reduction Discontinuous PWM Strategy With Active Neutral Point Voltage Control for Neutral Point Clamped Three-Level Inverter

The traditional discontinuous pulse width modulation (DPWM) strategy is very suitable for reducing the switching losses of three-level inverter (TLI). However, large neutral point voltage (NPV) fluctuation is usually caused, which results in low frequency harmonics (LFHs) in the output line voltage. Therefore, a DPWM modulation strategy that can suppress LFHs is presented in this paper, and it is recorded as low frequency harmonic reduction DPWM (LFHRDPWM). The proposed LFHRDPWM can be seen as an improvement of traditional DPWM, which modifies the duty ratios according to voltages of the two DC-link capacitors. For LFHRDPWM, due to the suppressed LFHs, the self-balancing ability of NPV is thus lost, and gradually increased DC offset on NPV is caused. To overcome that, an active neutral point voltage control (ANPVC) method is also proposed. The proposed methods not only can achieve switching loss (SL) reduction almost as the same as traditional DPWM strategy, but also can realize NPV control and LFHs reduction. The effectiveness of the proposed method is verified by experiments.


I. INTRODUCTION
Multi-level inverters have been proposed to enhance the equipment power and efficiency and reduce production costs. Compared with the current-source inverter (CSI), the voltagesource inverter (VSI) have been received more attentions from researchers. Various voltage-source multi-level inverter topologies have been proposed [1], where neutral point clamped (NPC) is the most popular topology at this stage, and is mainly applied in various industrial fields such as electric motor driven systems, wind energy conversion and photovoltaic [2]- [4]. The performance of three-level inverter (TLI) can usually be evaluated by the voltage offset on neutral point (NP), The associate editor coordinating the review of this manuscript and approving it for publication was Md. Rabiul Islam . NP voltage (NPV) fluctuation, harmonic and switching loss (SL) [5]. Using different PWM strategies can get different performances. In order to get better performances, PWM should meet the following requirements at the same time as far as possible: i) Improve the NPV balance capability as much as possible. ii) The output waveform maintains good sinusoidal to reduce harmonics. iii) Reduce SL and achieve high efficiency. Discontinuous PWM (DPWM) can effectively reduce SL.
The NPV imbalance is one of the inherent characteristics of NPC TLI topology. If the voltage of two capacitors is not limited to half of the DC-side bus voltage, current will flow in or out from the NP [6]. The non-ideal component in the converter may cause a DC component of the NP current. If this DC component continues to appear, it will cause a continuous offset of the capacitor voltages [7]. Usually, this NPV problem is called DC offset. In addition, the NP current is not constant. The NP current of each switching cycle is changed but will repeat within 1/3 fundamental cycle. Thus, NPV will fluctuate with triple fundamental frequency. Generally, this NPV problem is called AC ripple.
Aiming at the NPV balance, many active neutral point voltage control (ANPVC) algorithms are proposed [8]- [13]. The ANPVC algorithms can be summarized into two types, which are common-mode duty ratio injection and differential-mode harmonic current injection. According to the previous researches, it can be seen that all space vector PWM (SVPWM) strategies and the most carrier-based PWM (CBPWM) strategies are belong to common-mode duty ratio injection. In [13], an algorithm that belongs to differentialmode harmonic current injection is proposed, which balances the NPV by modulating the input current amplitude. This algorithm can obtain good results under all working conditions. The NPV has a certain self-equilibrium ability that should be noticed in [14]. Without any ANPVC, sometimes NPV change is zero over a period of time. However, this NPV self-equilibrium ability is sometimes strong and sometimes weak and may only appear in a specific operating area. In addition, it can be known from existing researches that the NPV self-equilibrium ability is closely related to the modulation strategy. In some applications, TLI can operate even without ANPVC due to the strong NPV self-balancing ability. It can be concluded from the above analysis that due to the uncertainty of the NPV self-balancing ability, ANPVC is very necessary for NPC TLI to ensure reliability.
Efficiency is an important factor in evaluating the performance of NPC TLI, which has a great correlation with the total system loss. To increase efficiency, system losses must be reduced as much as possible. Switching losses are the main component of system losses on high power occasion. On the one hand, the NPC TLI works at lower switching frequency as much as possible to reduce SL. On the other hand, DPWM can effectively reduce SL. For three-phase systems, during each control cycle, one phase is not be modulated and has no switching action. The other two phases are normally modulated and have a switching action. In addition, the DPWM modulation strategy can be further subdivided according to the distribution of discontinuous intervals, such as the traditional DPWM I-IV [15], [16]. Compared with the use of continuous pulse width modulation (CPWM), the use of DPWM can reduce switching losses, and can obtain better harmonic characteristics at high modulation index [17]- [19].
Several ANPVC methods based on DPWM have been proposed [18]- [23]. In [19], ANPVC is achieved by selecting proper clamping modes. And it is modified in [20], in which an improved pulse sequence is presented to further reduce SL by avoiding unexpected switching action while clamping mode is switched. However, the SL reduction is a little weaker than that of traditional DPWMs. Furthermore, similar characteristics were obtained in [21] besides reduced common mode voltage, which was derived from space vector diagram.
Two extended DPWM modes are presented in [22], using the nine traditional DPWM modes and the two extended DPWM modes alternately, then the NPV balance goal can be achieved over the entire modulation index and power factor range. In [23], a novel DPWM method using two different offsets for NPV ripple reduction was proposed.
In a word, when applying DPWM in practice, LFHs caused by the NPV imbalance should be suppressed and ANPVC should be demanded when the NPV self-equilibrium ability is small or even lost. Aiming at that, low frequency harmonic reduction DPWM (LFHRDPWM) strategy with ANPVC is pro-posed in this paper. With that, LFHs are well controlled. Several aspects are mainly discussed in this paper: the first aspect is NPV analysis under different DPWM strategies; the second aspect is LFHs caused by NPV shift; the third aspect is the proposed LFHRDPWM; the last aspect is the proposed LFHRDPWM with ANPVC method.

II. NPC TLI TOPOLOGY AND PRINCIPLE OF DPWM STRATEGY
A. NPC TLI TOPOLOGY Fig.1 shows the NPC TLI topology and three levels can be outputted. For instance, the output is connected to the positive bus (PB) while S 11 and S 12 are gated on and denoted as P level; the output is connected to the NP while S 12 and S 13 are gated on and denoted as O level; the output is connected to the negative bus (NB) while S 13 and S 14 are gated on and denoted as N level. The significance of the various symbols marked in Fig. 1 is as follows: u A , u B , u C , i A , i B , i C are the three-phase output voltage and current, respectively; C 1 , C 2 are the two capacitors in series in the DC side; u dc denotes DC side voltage. The expressions of three-phase voltage and three-phase current are: 3 ) In equation (1), ω represents the output angular frequency; ϕ represents the power factor angle; m represents the modulation index. The active power outputted by TLI can be expressed as: The three-phase voltages can be rearranged as:

B. REVIEW OF DPWM FOR TLI
The SL can be reduced effectively by using DPWM strategy. The principle of DPWM is to clamp a certain phase to a specific level to avoid switching actions. Both SVPWM and CBPWM can be used to implement DPWM. Compared with the SVPWM, CBPWM is much simpler. Therefore, CBPWM is chosen to implement DPWM in this paper. There are two basic modes of DPWM, which are DPWM_PB and DPWM_NB. DPWM_PB mode means that u max is clamped to PB. The ZSV for DPWM_PB can be expressed as: DPWM_NB mode means that u min is clamped to NB. The ZSV for DPWM_NB can be expressed as: The traditional DPWM I-IV can be acquired by combining DPWM_NB and DPWM_PB properly, and the combination rules are given by Table 1.

A. THE NP CURRENT IN ONE CONTROL CYCLE
The modulation method for CBPWM in one control cycle is presented in Fig. 2. If the modulated wave is larger than the carrier wave, higher level is outputted; otherwise, lower level is outputted. In one control cycle, d X0 denotes the duty of O level of phase X (X=max, mid, min). If the modulated wave is larger is larger than zero, the switching sequence is composed of O and P level. Otherwise, it is composed of N and O level.
After ZSV is injected, the modulation signal of phase X is u X , and then according to Fig. 2, the expression of d X0 is: The average NP current in a control cycle can be defined as: For simplifying analysis, i 0N is normalized average NP current. i 0N,PB is normalized average NP current under DPWM_PB mode; i 0N,NB is normalized average NP current under DPWM_ NB mode.
The ZSV for different clamping mode are given as (4) and (5). u max , u mid , u min are the modulation waves after the ZSV injected. i max , i mid , i min are the corresponding phase current to u max , u mid , u min . In one control cycle, there are three cases for i 0N,PB under DPWM_PB mode: Case1 for DPWM_PB: u max = u dc /2, u mid > u min > 0, and i 0N,PB can be obtained as: Case2 for DPWM_PB: u max = u dc /2, u mid > 0 > u min , and i 0N,PB can be similarly expressed as: Case3 for DPWM_PB: u max = u dc /2, 0 > u mid > u min , and i 0N,PB can be expressed as: In one control cycle, there are also three cases for i 0N,NB under DPWM_NB mode: Case1 for DPWM_NB: 0 > u max > u mid , u min = −u dc /2, and i 0N,NB can be expressed as: Case2 for DPWM_ NB: u max > 0 > u mid , u min = −u dc /2, and i 0N,NB can be expressed as: Case3 for DPWM_NB: u max = u dc /2, 0 > u mid > u min , and i 0N,NB can be expressed as: The change on NPV u NP during [t1, t2] can be defined as: where u NPn is the normalized change on NPV. For simplifying analysis, u NPn will be discussed instead of u NP . The following content is discussed on the premise that the current are constant over a control cycle and the flowing from TLI is considered to be the positive direction of the current.
3) m > 0.577 As far as DPWM_PB and DPWM_NB are concerned, when m > 0.577 and ωt ∈ [0, 2π/3], there are Case 2 and Case 3, and Fig. 6 shows the three-phase modulation waveforms of the two clamping mode.
The intersection angles of Case 2 and Case 3 are θ 2 and 2π/3-θ 2 for DPWM_PB, respectively. θ 2 can be calculated by the line voltage's relationship: When m > 0.577, the u NPn under different clamping mode are given in Fig.7.
From above analysis, it can be obtained that the following equation is satisfied at any modulation index and power factor: VOLUME 8, 2020  The equation (17) can be also verified by mathematic method.
Considering the combining rules for DPWM I-IV between DPWM_NB and DPWM_PB, it is not difficult to find that u NP is zero in in terval [0, 2π/3] under DPWM I-IV. In theory, there is only ripple with triple fundamental frequency. In practice, due to the non-ideal circuit parameters and control algorithms of the system, the NPV may also have DC offset in addition to the theoretical AC ripple.

IV. LFHs ANALYSIS
It can be seen from Figs. 3-6 that there is at least one compliance mode in any condition of m and ωt, and even there are three compliance modes in some conditions of m and ωt. So an optimal compliance mode should be chosen. In this paper, the minimum switching loss is used as selection criterion. The switching loss evaluation function for different modes can be expressed as: Assuming that u is the offset of NPV, the upper and lower capacitor's voltages will change from u dc /2 to u dc /2u and u dc 2+ u, respectively. Thus, NP is not suitable to be selected as reference point. The voltage of phase A relative to NBũ AN can be written as: Similarly,ũ BN is: Then, the AB line voltage can be obtained by the following equation: Define k = 2 u/u dc as the offset coefficient of the NPV. When NPV is shifted, considering (1), (24) can be rewritten as:ũ From (25), it can be seen that there is an extra item inũ AB , which is the cause of low frequency harmonics. The value quotient of u AB and AB line voltage peak u AB,peak is: , n = 2, 4, 8, 10 · · · (27)

B. THE ODD ORDER LFHs FORMED BY AC RIPPLE
When TLI works in steady state, the fluctuation with triple fundamental frequency is the dominant component of AC ripple. Assuming that k = k m sin(3ωt), and k m is the amplitude of AC ripple. The value quotient of u AB and AB line voltage peak u AB,peak is: The existence of odd order LFHs has been revealed by the Fourier analysis of the output line voltage. The RMS quotient of harmonics and line voltage u 1 is: From above analysis, the AC ripple is the cause of odd order LFHs, and the higher the amplitude of the AC ripple, the higher amplitude of the LFHs is caused.

C. THE INFLUENCE OF LFHs ON TLI
As can be seen from the analysis in this section, for the output line voltage, DC offset is the cause of even order LFHs, while AC ripple is the cause of odd order LFHs. Harmonic voltage will result the corresponding order harmonic currents. However, even order harmonic currents are beneficial to the NPV self-equilibrium ability [14].
Although the even order current harmonics caused by the even order LFHs voltage are beneficial to the NPV selfequilibrium ability, it is usually required to eliminate the even and odd order LFHs voltage at the same time in modulation strategy. In other words, it is not desirable that there are DC offset and AC ripple on the NPV. Therefore, the following two questions must be paid attention.
(1) even and odd order LFHs must be eliminated in the proposed DPWM strategy.
(2) The ANPVC for the proposed DPWM must be studied to compensate the loss of the NPV self-equilibrium ability caused by even-order LFHs elimination.
In existing literatures, these two problems in NPC TLI with conventional DPWM strategies are not meanwhile resolved.

V. LFHRDPWM
The voltage of phase X is modified as follows with NB as the reference point: After the ZSV is injected given as (4) under DPWM_PB mode, and three-phase voltages arranged according to the law given in (3) can be rewritten as: The modulation principle under unbalanced NPV in one control cycle is given in Fig. 8, and the amplitudes of the carrier 1 and 2 are u C1 and u C2 , where u C1 and u C2 respectively denote the voltage of upper and lower capacitors. As shown in Fig. 8, when u C2 < u X < u C1 + u C2 , the switching sequence is consisting of P and O level. When 0 < u X < u C2 , the switching sequence is consisting of N and O level. When u X = u C1 + u C2 or 0, only P or N level is formed. Under DPWM_PB mode, the duty calculation expression of each phase and each level can be summarized into three situations: When u mid > u min > u C2 : When u mid > u C2 > u min : (34) VOLUME 8, 2020 When u C2 > u mid > u min : After the ZSV is injected given as (5) under DPWM_NB mode, and three-phase voltages arranged according to the law given in (3) can be rewritten as: Under DPWM_NB mode, the duty calculation expression of each phase and each level can be summarized into three situations: When u mid > u min > u C2 : When u mid > u C2 > u min : When u C2 > u mid > u min : Based on the obtained duty, the line voltage under LHFRD-PWM can be calculated as: From (40), the line voltage relationship under LHFRD-PWM remains unchanged.
And it can be concluded that when u max − u min ≤ u dc , the duty of each level is between 0 and 1. Therefore, the utilization of DC voltage for LFHRDPWM is equivalent to that for CSVPWM, and the modulation range is still [0, 1].
For LFHRDPWM, the three-phase modulation waves are the same with that of traditional DPWM, but the amplitudes of the two carrier waves are no longer equal, which are determined according to the voltages of the two DC-link capacitors. So, it can be seen as an improvement of traditional DPWM, which only modifies duty ratios. Therefore, the proposed LFHRDPWM can achieve SL reduction as the same as traditional DPWM.
However, due to the elimination of even-order LFHs, the self-equilibrium ability of NPV is lost, which results in gradually increased DC offset. So, LFHRDPWM can not be directly applied without any ANPVC control.

VI. ANPVC FOR LFHRDPWM
From the researches in section V, the LHFRDPWM is presented to eliminate odd and even order LFHs. Therefore, it is necessary to adopt ANPVC for LFHRDPWM, which can compensate the loss of the NPV self-equilibrium ability caused by even-order LFHs elimination.
According to Table 1, DPWM_PB or DPWM_NB is held on π/3 interval in implementation of different DPWM. It is conceivable that if the duration of DPWM_PB and DPWM_NB is extended and is held on 2π/3 interval, then ANPVC can be obtained.
Assuming that g NB denotes the integral of the NP current in the interval of 2π /3 under DPWM_NB and g PB denotes the integral of the NP current in the interval of 2π/3 under DPWM_PB. Omitting the tedious derivation process, g NB and g PB can be calculated as: h(m) is the segmentation function related to modulation index, and the expression of segmentation function is: The relationship diagram between h(m) and m is given in Fig. 9. No matter what value m takes, the value of h(m) is always positive. So in the DPWM_NB and DPWM_PB, the sign of g NB and g PB is only related to ϕ. When ϕ > 0, g PB > 0 and the NPV will decrease, while g NB < 0 and the NPV will increase during π/3 interval. Thus, when there is a large unbalance, DPWM_PB or DPWM_NB is held on 2π/3 interval to control the NPV. When the hybrid modulation strategy of LFHRDPWM and LFHRDPWM with ANPVC is used, it can ensure the controlled NPV and the reduced LFHs.
To realize the switch between LFHRDPWM and LFHRD-PWM with ANPVC, hysteresis controller for NPV is used. The upper and lower limits of the hysteresis threshold are determined by the maximum allowable positive shift and negative shift of the NPV, respectively. The operation principle of hysteresis controller is described in Fig. 10. The LHFRD-PWM with ANPVC will be started when the upper limit condition is triggered and it will be stopped when the lower limit condition is triggered. The PWM sequences are formed by the hysteresis controller switching between two modulation strategies. It can be imagined that with the decrease of hysteresis band, ANPVC will be frequently involved. In practice, u dc ±5% can be used as the hysteresis band.
Because the clamping duration becomes 2π/3 while the proposed ANPVC is involved, the SL is reduced compared to traditional DPWM. However, it is not frequently involved in practice, and then the SL is almost the same with traditional DPWM.
To well show the principle of the proposed ANPVC, corresponding simulation results are given in Fig. 11, where the figure on the right is an enlarged view of the marked area on the left. In Fig. 11, u C1 and u C2 stand for the upper and lower capacitor voltages, u A is the final modulation wave of phase A, and u ZSV denotes the injected ZSV.
From Fig. 11, it can be seen that while the proposed ANPVC is triggered, the clamping duration of DPWM_PB is changed from π/3 to 2π/3, and NPV increases towards equilibrium. In this case, DPWM_PB is held on 2π/3 interval because u C1 is larger u C2 . For the proposed ANPVC while u C1 is less than u C2 , DPWM_NB is held on 2π /3 interval, which is not given.    current, it can be seen that the NPV exhibits the characteristic of triple frequency and repeats three times in a fundamental cycle. The value of u NPn under different operating conditions is given in Fig. 13. In the region of low m (m < 0.5) and low ϕ (ϕ ≈ π/2or -π /2), the u NPn of DPWMs are almost zero. It is because there is no energy transition between AC and DC side. In the region of moderate m (m ≈0.5) and high ϕ (ϕ ≈0 or π), the u NPn of DPWMs get their maximum value. In this situation, the odd times harmonics in line-toline voltage will get their maximum values.

VIII. EXPERIMENTS
The feasibility of LFHRDPWM has been verified by building NPC TLI platform, and the prototype is shown in Fig. 14    controller, and DPWM I was chosen as an example for verification and comparison. To avoid the influence of control loop, open-loop control is adopted in the experiments. In order to well understand the implementation of the proposed methods, the corresponding flow diagram is shown in Fig. 15. Comparing to traditional DPWM, the amplitudes of the carriers are determined by u C1 and u C2 , and the clamping duration is extended from π/3 to 2π/3 while the proposed ANPVC is enable.
The key NPC TIL platform parameters are shown in Table 2. In order to facilitate the research, the experiment was carried out under six specific operating conditions,  A. EXPERIMENTAL RESULTS RELATED TO DPWM I Fig. 16 presents the experimental results of the start-up process under DPWM I. As for the NPV, when ϕ = 83.6 • , the DC offset gradually increases until it enters a steady state; when ϕ = 6.4 • , the DC offset is significantly smaller but with larger AC ripple. The reason is that under high load power factor, the intrinsic negative feedback of NPV caused by even harmonic currents is stronger than that under low load power factor [14]. Fig. 17 presents the experimental results of the steadystate under DPWM I. As for the NPV, the DC offset is more obvious than AC ripple under operating conditions 1 and 3, and the output line voltage contains higher second and fourth harmonics, which can be found in Fig. 17(a) and 17(c).
When ϕ = 6.4 • , the triple frequency ripple is the main form of unbalanced NPV. Under operating condition 2, NPV not only has DC offset but also AC ripple. Thus, in addition to the second and fourth harmonic components in the output line voltage, there are fifth and seventh harmonic components. Under operating condition 4, the fluctuation amplitude of AC ripple is larger than other cases, which verifies the previous simulation results.
It can be summarized that when DC offset is larger, even order LFHs are dominated; when AC ripple is larger, odd order LFHs are dominated.

B. EXPERIMENTAL RESULTS RELATED TO THE PROPOSED STRATEGY
The LHFRDPWM without ANPVC is discussed firstly, and the start process results are shown in Fig. 18. The DC offset was produced gradually during the start-up process. The shift rate of NPV under ϕ = 6.4 • is faster than that under ϕ = 83.6 • . When the offset of NPV reaches protection value, TLI stops. So LFHRDPWM without ANPVC for TLI cannot be used.
Then, the LHFRDPWM with ANPVC is discussed. In experiments, 30V hysteresis band is adopted. Although it is relatively large with respect to the DC-bus voltage, this is selected on purpose to make the experimental phenomenon obvious. Fig. 19 presents the experimental results of the start process under LHFRDPWM with ANPVC. Although the DC offset was produced gradually during the start process, ANPVC is quickly intervened to bring NPV back to balance as soon as the upper limit of hysteresis controller was reached. This process is repeated. The shift rate of NPV under ϕ = 6.4 • is faster than that under ϕ = 83.6 • . At the same m, the intervention of ANPVC under ϕ = 6.4 • is more frequent than that under ϕ = 83.6 • . Fig. 20 presents the experimental results of the steadystate under LHFRDPWM with ANPVC. Compared to that shown in Fig. 17, LFHs are effectively reduced that can be found in the output line voltage frequency spectrum. From Fig. 20, it can be seen that the two capacitor voltages are always undergoing a dynamic change in most cases. If the capacitance becomes small, the dynamic change frequency will be increased.     Summarizing the experimental results, the following conclusions can be drawn.
(1) When using LHFRDPWM alone, the even order LFHs in the output line voltage will be removed, which will cause NPV to lose its self-balancing ability and thus the TLI cannot work normally; (2) When using LHFRDPWM with ANPVC, TLI can work normally; (3) When using LHFRDPWM with ANPVC, the NPV is controllable; (4) The proposed modulation strategy almost has the same ability to reduce SL as DPWM I.

IX. CONCLUSION
DPWM is a commonly used modulation method to reduce switching losses, but DPWM makes NPV appear DC offset and AC ripple. In terms of the output line voltage, DC offset causes even order LFHs and AC ripple causes odd order LFHs. Therefore, LHFRDPWM is studied to suppress LFHs. But only LHFRDPWM cannot guarantee the balance of NPV and cannot make TLI work normally. Therefore, it is proposed to use ANPVC to balance the NPV. By switching LFHRDPWM and LFHRDPWM with ANPVC, the controlled NPV and the reduced LFHs, can be realized simultaneously, and it almost has the same SL reduction ability as DPWM I. The method is the improvement of traditional DPWM, and they have the same performance in terms of common mode voltage. Moreover, in over modulation region, although most regions may be clamped, the output line voltage is still distorted and LFHs are thus caused. Based on the proposed method in this paper, the reduction of common mode voltage and output line voltage distortion in over modulation region will be considered in our future work.