A 40nm CMOS Hysteretic Buck DC-DC Converter With Digital-Controlled Power-Driving-Tracked-Duration Current Pump

A fast-transient voltage-mode hysteretic buck converter with digital-controlled power-driving-tracked-duration (PDTD) auxiliary current pump is proposed. The pump injection current duration is digitally controlled by the driving signal of the power stage. It aims at enhancing the transient response time which is limited by the large inductor used in typical buck converters and reducing the multiple undershoot/overshoot effect encountered in conventional current pump injection technique. The converter has been fabricated using TSMC 40nm CMOS technology with the silicon area of $830\mu \text{m}\times 620\mu \text{m}$ . The proposed converter regulates properly in both Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). The measured output ripple is about 30mVpk and the switching frequency is about 1.45MHz. The peak efficiency is 93%. The measured load transient settling time for a 60-to-300mA/300-to-60mA load step change is 369ns/335ns, resulting in 350% faster than that of conventional counterpart without PDTD control scheme. The performance comparison with the representative state-of-art works has shown that the proposed converter shows good balance on performance metrics and the best figure-of-merit (FOM) in transient-response efficiency.


I. INTRODUCTION
In recent years, a rapid growth of portable devices, such as smartphones, tablets, laptops and digital cameras is resulted from the development of system-on-chip (SoC) [1]- [8] which have different energy requirements [6]- [9]. Concurrently, low power consumption is one of the primary design agenda for the battery-powered SoC [10]. Switching converters are widely used due to its high power-conversion efficiency [9]- [11]. Operating under different modes tends to be an effective method of reducing power consumption [12], [13]. As such, the embedded digital systems or microprocessors operating at high speed need to switch between different modes [14], [15]. During the dynamic loading change and the operation mode transfer, a massive load current change can induce a large The associate editor coordinating the review of this manuscript and approving it for publication was Zhe Zhang . undershoot/overshoot from the output voltage for a significantly long time owing to the transient regulation latency [12]. The undershoot voltage may cause missing of data and operation distortion under high speed scenario, whereas the overshoot voltage may contribute extra power loss and even damage the ambient devices and the overall chip. The long settling time limits the system mode switching frequency, and thus it may deteriorate the overall system performance and narrow its application scenarios [4]. In this prospective, fast-transient response becomes one of the key requirements for DC-DC converters in high performance applications [11], [16]- [19]. FIGURE 1 shows the block diagram of a DC-DC converter which comprises the power stage and the controller stage. The transient response is mainly constrained by the controller stage delay and the LC limitation of power stage [20]- [23]. Various techniques have been reported to achieve fast-transient response and reliable output voltage. Some of them focus on speeding up the controller stage at the expense of increased system complexity. Although the adaptive bandwidth compensation techniques [24], [25] and the capacitor multiplier techniques [26] aim to extend the compensated bandwidth, their transient responses are still limited by the OTA bandwidth through the frequency compensation in compromising overall closed-loop stability. In addition, V 2 converters are successful by introducing the feedforward path to bypass the slow error amplifier (EA) [12], [18], [27], but this approach may suffer from the subharmonic oscillation [8], [27]. Regarding the hysteretic converters, they offer faster response time and better-guaranteed stability using the compensation-free controller stage [28]- [33]. Moreover, these converters can operate at Pulse Frequency Modulation (PFM) mode automatically under the light load conditions to reduce the frequency-dependent switching loss, thus improving the light load efficiency [27], [34]. However, the transient speed of existing hysteretic converters is still constrained by the inductor. To overcome this limitation, an auxiliary current pump is applied to bypass the inductor, compensating the load current change for enhanced transient response [35]- [39]. The prior reported analog control topology in [4] is applied to achieve an instant current injection and a smooth turningoff, but it requires careful design of compensation network for stability whilst at expense of circuit complexity. Transient improvement of the auxiliary current is degraded by the compensated bandwidth of the error amplifier control loop. Besides, several voltage-triggering current pump sources inject auxiliary current by detecting the output voltage directly, supporting fast auxiliary current injection [36]- [38]. However, without output tracked turning-off control, multiple undershoot/overshoot may be induced when the current pump sources are turned off instantly, thus deteriorating the expected transient performance and the system stability. Although digital slope control scheme can avoid instantly turning-off control for current pump [20], [39], it requires complicated components and topology. In this work, a fasttransient hysteretic buck converter with a digital-controlled Power-Driving-Tracked-Duration (PDTD) scheme for the auxiliary current pump source is proposed. The auxiliary current is injected and hold for a long enough time to optimize the transient improvement of the auxiliary current. The current duration is well-defined to track the output variation through the effective digital control method. Due to hysteretic based design, it can eliminate the need of compensation network as encountered in analog approach whilst it yields low cost design by using simple digital components. It overcomes the above stated drawbacks whilst providing the optimal performance tradeoff arising from the transient enhancement technique. This paper is organized as follows. Section II presents the respective time-domain transient analysis for the conventional and proposed voltage-mode hysteretic DC-DC converters. Section III presents the system and circuit design of the proposed fast-transient DC-DC converter. Section IV shows the circuit and system implementation. Section V discusses the measurement results and the performance comparison with the representative reported works. Section VI gives the concluding remarks.

II. LOAD TRANSIENT RESPONSE ANALYSIS
In this Section, the undershoot transient response for the voltage-mode hysteretic converter is analyzed at the output node shown in Fig. 2(a) and Fig. 2(b). The current-voltage relationships in Fig. 2(a) are obtained as follows: The transient behavior of the inductor current I L (t) and the load current I R (t) are assumed as where m 1 and m 2 are the ramp-up slopes of I R (t) and I L (t), respectively and m 1 m 2 . -m 3 is the falling slope of I L (t). V OUT is the designed dc output voltage and I R = V OUT /R is the corresponding load current at V OUT .

A. WITHOUT I P (T)
The analysis is based on Fig. 2(a). and the case A timing waveforms are shown in Fig. 3. The key response waveforms are shown in Fig. 4.

1) REGION_A1:0 < t < t edge
In this region, assuming V C (0) = V out (0) = V OUT , we have where m = m 1 − m 2 .Since I C (t) > 0, the output capacitor C is discharged and a negative V ESR (t) is induced across R C . As a result, both V C (t) and V out (t) decrease within [0, t Edge ], causing large undershoot variation. If I R (t) ramps very rapidly where t Edge 2C R C can be easily fulfilled, then The output variation V out (t) = V OUT − V out (t) mainly consists of the negative V ESR (t) and hence V out (t) decreases linearly.
2) REGION_A2: t Edge <t < t Max Similarly, solving dV our (t)/dt = 0 to yield V out (t) min at the time The undershoot variation V UN is obtained as follows: Since V out (t) of the voltage-mode hysteretic converter is regulated by itself, when t>t min , V out (t) rises continuously until V out (t) reaches the high-side boundary of the window comparator V H . The settling time t Settle is assumed when V out (t) = V OUT . As such, the settling time expression is obtained as

3) REGION_A3: t Max <t < t Recover
In this region, the I L (t) ramps down and we have In this case, I C (t) < 0 and it continuously charges up C. When t = t Recover , I C (t) = 0 and V out (t Recover ) = V C (t Recover ). At this juncture, I C (t) finishes one complete discharging and charging cycle after the change of load current. Table 1 summarizes the time domain expressions for key parameters. Both V UN and t Settle are highly dependent on the load current magnitude I R . The transient performance can be improved by reducing I R . Of particular noted, the I R is the magnitude value over [t Edge , t Recover ]. This gives the proposed improvement by means of adding the current pump I P (t), as illustrated in Fig. 2(b), to bypass L so as to compensate the change of I L (t). In order to enhance the transient performance, the I P (t) in this work is designed to be hold until t End as indicated in Fig. 3.

B. WITH PDTD I P (T)
The analysis is based on Fig. 2(b) and the Case B timing waveforms in Fig. 3. The key response waveforms are shown in Fig. 5. In this case, the I P (t) in [0, t End ] is described as where m = m 1 − m 2 − m 4 and m < m.With the injected I P (t), a smaller I C (t) is required to compensate the change of I L (t) while V C (t) and V out (t) become larger. This is because I P (t) helps to compensate the change of I R (t), reducing the discharge current I C (t). Consequently, V C (t) decreases with a smaller rate and V ESR becomes smaller, leading to reduced V UN .
2) REGION_B2: t Edge <t < t P In this region, I R (t) = I R while I P (t) keeps on increasing. As a result, I Eq (t) = I R -m 4 t is reducing and the same goes for I C (t). The corresponding transient relationship for I C (t), V C (t) and V out (t) can be obtained as follows: where Solving Comparing with Case A, I C (t) decreases with a larger slope in this region. V C (t) min becomes larger. Equation (27) indicates V out (t) min varies with respect to m 2 , in which m 2 = m 2 + m 4 , and it gives δV out (t) min and becomes larger in Case B, and hence the V UN is reduced through I P (t).

3) REGION_B3: t P <t < t' Max
In this region, I P (t) = I P and the equivalent output current I Eq (t) = I Eq = I R − I P . The corresponding transient relationship for I C (t), V C (t) and V out (t) can be obtained as follows: In this region, I C (t) < 0, C is charged up. Both V C (t) and V out (t) rise with an increasing slope over [t P , t Max ]. As such, the transient settling time will be significantly reduced.

This gives
When V out (t) = V H , the time becomes where k is a constant and k = − m 4 2C t 2 P + m 1 t 2

Edge
2C + V OUT . Comparing with Case A, we have I Eq < I R , and it can be proved that t Settle <t Settle with I P <I R .

4) REGION_B4: T' Max <t<t End
In this region, I L (t) decreases. I C (t)<0 and it is given as The I C (t) continuously charges up C. When t = t' Recover , I C (t) = 0 and V out (t Recover ) = V C (t Recover ). At this juncture, I C (t) finishes one complete discharging and charging cycle after the change of load current. The transient parameters in Case A and Case B are summarized in Table 1. It proves that both V UN and t Settle can be reduced through holding on the I P (t). Fig. 6 illustrates the whole system architecture of the voltagemode hysteretic buck converter with the proposed PDTD control stage. The output capacitor is required to have a large ESR value to provide sufficient output voltage ripple V out (t). As suggested in [31], [40], the required minimum ESR value can be estimated by where V L is the low-side boundary of the window comparator and the other symbols have been defined before.

III. CIRCUIT AND SYSTEM IMPLEMENTATION
With the large ESR, V out (t) is dominant by the V ESR (t) and it is fed to the hysteretic comparator, generating the voltage signal V WIN as well as the adaptive control signals of undershoot/overshoot detection circuit, ON UN and ON OV . V WIN is used to regulate I L (t) through controlling the power transistors. The PFM control is added to improve the light load efficiency. Dual current pump sources are employed to compensate the large current difference between I R (t) and I L (t). They are triggered on by the undershoot/overshoot detection signal. The I P (t) turning-on duration is modulated by the power-driving-tracked-hold stage whereas the turningoff mechanism is controlled by the hold-period delayed ramping generator. The detailed circuit implementation of the proposed transient enhanced stage will be described in the following sub-sections.

A. UNDERSHOOT/OVERSHOOT DETECTION STAGE
In this work, the undershoot/overshoot is detected through a pair of adaptively-biased comparators [41]. As shown in Fig. 7, the adaptive biasing signals ON UN and ON OV are generated through the hysteretic comparator. They are added to reduce the standby power consumption of the undershoot and overshoot detection comparators. Once V FB is larger than the overshoot detection reference V HH , the OV goes to high. When V FB is smaller than the undershoot detection reference V LL , UN goes to high.

B. POWER-DRIVING-TRACKED-HOLD STAGE
In this work, the I P (t) hold-on duration is designed to track V out (t) variation such that a sufficient hold-on duration is guaranteed to enhance the transient response. In the meantime, once V out (t) settles down, I P (t) will be turned off to save power. This methodology is realized through the power-drivingtracked-hold stage in Fig. 8. It consists of two sub-stages: (1) wide pulse trigger stage with an exclude stage logic which is formed by the cross-coupled NAND gates and (2) pulse duration control stage. The wide pulse trigger stage is to extend the undershoot/overshoot detection signal UN/OV such that it provides a long enough turning-on duration for I P (t). The endpoint of wide pulse signal WP UN /WP OV is determined by the pulse duration control stage, which detects V out (t) by monitoring the power transistor driving voltage P and N . The exclude stage logic is to guarantee that UN and OV are exclusively extended. WP UN /WP OV is the inverting signal of WP UN /WP OV . EN UN and EN OV is the pulse duration control signal for undershoot and overshoot wide pulse trigger stage, respectively. HOND UN /HOND OV is the output signal of the dual pulse hold stage for undershoot/overshoot.

C. WIDE PULSE TRIGGER STAGE
In Fig. 7, the UN/OV state of output signal changes whenever V FB crosses V HH /V LL , giving fast detection speed. However, this narrow UN/OV pulse output causes insufficient turningon duration for the I P (t). To guarantee fast detection as well as sufficient turning-on duration, the turning-on and turning-off mechanism of I P (t) is separated in this work. This is realized through the wide pulse trigger stage as illustrated in Fig. 9.
When EN UN = 1, the equivalent wide pulse trigger stage is shown in Fig. 10(a). When V FB < V LL , the narrow detection pulse UN goes to high, setting WP UN to 0 and WP UN to high. When V FB >V HH , UN drops to 0. Due to the feedback logic, WP UN will be latched to 0 by itself and the WP UN is kept at high. In this case, a wide pulse WP UN can be triggered by the narrow UN pulse and the pulse duration of WP UN is independent of UN. When EN UN = 0, the equivalent circuit is shown in Fig. 10(b). In this case, EN UN will cut off the logic path and reset the wide pulse WP UN to 0 regardless of UN state. The narrow trigger pulse UN is extended to a wide pulse WP UN to provide sufficient hold-on duration for current pump I P (t). The rising edge of WP UN is only triggered by UN when EN UN = 1. On the other hand, the falling edge of WP UN is only controlled by the falling edge of EN UN . In this way, the turning-on and turning-off mechanism of I P (t) is then separated. The falling edge of EN UN is realized through the pulse duration control stage. The exclude stage logic circuit, which consists of the crosscoupled NAND gates, is added after the wide pulse trigger stage. It is to ensure the wide pulse WP UN /WP OV cannot be passed at the same time. As such, it avoids turning on the dual auxiliary current pump simultaneously. Hence, it helps to protect the overall system and reduce the power loss.

D. PULSE DURATION CONTROL STAGE
To improve the transient response of the voltage-mode hysteretic DC-DC converter, I P (t) is required to be hold for a long enough time. After V out (t) recovers back, I P (t) is required to be turned off to save power. In this work, the endpoint of I P (t) duration is designed to be at t End in Fig. 3. In the voltage-mode hysteretic buck converter, a large ESR value is required to keep V out (t) in phase with I L (t) and I L (t) is directly controlled by the power PMOS/NMOS transistor. Hence, the endpoint t End can be determined by monitoring the power PMOS/NMOS transistor driving voltage P/N . This is realized through the circuit as depicted in Fig. 11.  (1) and (3) are the positive edges and edges (2) and (4) are the negative edges. EN UN _P and EN UN _N are generated when WP UN goes through the flip flops DFF_P and DFF_N, respectively. EN UN is the pulse duration control signal. When EN UN is high, the wide pulse trigger stage is activated, and if UN is triggered, the wide pulse WP UN will be generated. On the other hand, when EN UN is low, the WP UN will reset to 0 regardless of the state of UN.

E. HOLD PERIOD DELAYED RAMPING GENERATOR
After the output voltage settles down, I P (t) is turned off at t End . However, if I P (t) is turned off instantly, a large current difference between I L (t) and I P (t) will be generated, which has the same effect as the change of I R (t). As observed, multiple undershoot/overshoot effect will be induced [36], [37], deteriorating the transient response and the system stability. This problem can be solved by turning off I P (t) slowly such that the change of I P (t) change can be compensated by I L (t). This is realized by generating a ramping period to slow down the ramping-up speed of I P (t) control voltage V GS (t), which is illustrated in Fig. 12. HOLD and V RAMP indicates the power-driving-tracked-hold signal and the I P (t) control voltage V GS (t), respectively. V RAMP is required to go down instantly to enhance the transient response. On the other hand, a relatively slow ramp-up slope is needed to avoid multiple undershoot/overshoot effect. M N has relatively larger aspect ratio than that of M P .
Once a large undershoot is detected, the HOLD will be triggered to logic 0, discharging the capacitor C RAMP rapidly through the large size M N . As a result, V RAMP is pulled down instantly whereas I P (t) is triggered on instantly to enhance the transient response. After V out (t) recovers back, HOLD is reset to high at t End instantly to cut off I P (t). Different from the HOLD, a ramping period is generated in V RAMP by a relatively small constant current I Charge to slow down the I P (t) changing rate. If I L (t) can compensate the change of I P (t), the multiple undershoots/overshoots will be significantly reduced or even eliminated. The ramp-up rate of V RAMP is given as follows: F. DUAL CURRENT PUMP SOURCE As shown in Fig. 13, either the current pump I P_UN or I P_OV is injected to the output node directly. Both I P_UN and I P_OV are designed to be supply independent through the constant biasing current I 1 to I 4 . S 1 to S 7 are controlled by the ramping voltage for undershoot or overshoot. Hence, I P_UN /I P_OV can be instantly turned on to enhance the transient response and slowly turned off to reduce the multiple undershoot/overshoot. During the steady state, S 1 to S 5 are turned on, pulling V P1 , V P2 and V P3 up to V DD while pulling V N 1 and V N 2 down to ground. In this way, I P_UN and I P_OV can be totally off to save power. I 1 and I 3 are always on to speed up the current pump start-up process. I 2 and I 4 are adaptively controlled by S 6 and S 7 to reduce the quiescent current.

G. DCM OPERATION
The DCM control algorithm is added to eliminate the reverse current, thus improving the light load efficiency [5].The reverse current detection is realized by the common gate comparator [42]. A large size free-wheel switch (FWS) transistor is added to reduce the ring effect when both NMOS and PMOS are turned off [43].

IV. RESULTS AND DISCUSSIONS
The proposed converter has been fabricated using TSMC 40nm CMOS process which is suitable for low-voltage SoC applications, the micrograph is shown in Fig. 14. The occupied silicon area is 830µm×620µm. Other support blocks  such as dead time control, over-current protection and soft start circuits are also realized in the DC-DC converter in order to protect the overall system and maintain the power efficiency. The fabricated fast-transient DC-DC buck converter has been tested with the input voltage of 2.5V and the nominal output voltage of 1.2V. The output capacitor is 4.7µF and the inductor is 4.7µH.

A. STEADY-STATE MEASUREMENT
The steady-state measurement results for CCM and DCM are illustrated in Fig. 15(a) and Fig. 15(b), respectively. Fig. 15(a) shows the steady-state waveforms of the output voltage V out (t) and the inductor current I L (t) at the load current of 60mA. It has validated that the proposed converter can regulate properly in CCM. The output ripple is about 30mV pk whereas the switching frequency is about 1.45MHz. It also shows that the V out (t) is in phase with the I L (t) because of the large ESR in the voltage-mode hysteretic converter as discussed in Section III. Fig. 15(b) shows the waveforms of the output voltage V out (t), the inductor current I L (t) and the switching node voltage V X (t) at the load current of 20mA. It has confirmed the design methodology of the DCM operation. During the light load condition, the reverse current can be detected and eliminated. The ringing at the output node can be significantly reduced by applying the FSW control. As a result, the light load efficiency is improved. The efficiency at different load currents is plotted in Fig. 16. The peak efficiency η peak is 93% at 60mA at V out = 1.2V. Finally, due to the PFM control of hysteretic converters under DCM, the light load efficiency at 20mA is close to 90%.

B. TRANSIENT RESPONSE MEASUREMENT
For the conventional hysteretic buck converter without the I P (t), the undershoot and overshoot transient response VOLUME 8, 2020  for the 60-to-300mA and 300-to-60mA load current change under the load current control signal V step (t) is illustrated in Fig. 17(a) and Fig. 17(b), respectively. The edge time of the current load step is about 5ns. The undershoot/overshoot variation V UN / V OV is 128mV/127mV whereas the undershoot/overshoot transient settling time For the hysteretic buck converter with PDTD I P (t), the undershoot/overshoot transient response for the 60to-300mA/300-to-60mA load current change is depicted in Fig. 18(a) and Fig. 18(b), respectively. In comparison to the conventional counterpart, the undershoot/overshoot variation V UN / V OV is reduced to 73mV/72mV whereas the transient settling time t Settle is improved to 369ns/335ns. This suggests that the proposed work offers 350% faster than that of the conventional counterpart, validating the effectiveness of the PDTD control scheme. Table 2 shows the performance comparison of the converter with the reported state-of-art works. In order to

V. CONCLUSION
The analysis, design and circuit implementation of the voltage-mode hysteretic DC-DC buck converter using the digital-based PDTD control scheme for generating well-defined digital-controlled auxiliary current pump are presented. The measurement results have shown that the converter regulates properly in both CCM and DCM. With freewheel switch control, the ringing at the output node can be significantly reduced. Through the PDTD control scheme, the transient response time of the voltage-mode hysteretic DC-DC buck converter can be significantly reduced with respect to most of representative prior-art topologies. Not only does it provide sufficient turning-on duration of the current pump to speed up the transient response, it also reduces the multiple undershoot/overshoot significantly whilst maintaining reasonable ripple voltage and efficiency at low output voltage to yield the balance performance metrics. Compared with conventional converter without PDTD control scheme, it improves the transient response time by 350%.
Hence, the proposed digital-based PDTD current pump technique is very useful for realizing fast-transient response in DC-DC buck converters.