Extended Multilevel Inverter Topology With Reduced Switch Count and Voltage Stress

For the applications related to the medium/high-power/voltage, Multilevel inverters (MLI) are widely accepted and commercially used. The performance of MLI compare to the conventional two-level inverters is significantly superior due to the insignificant amount of harmonic distortion, lower filter size, requirement of low voltage rating devices, lower electromagnetic interference, etc. However, there are a few disadvantages such as an increased number of components, a complex modulation and control strategy, and issues related to the voltage balancing of capacitors. The present paper proposes a new topology with a lower voltage rating component to improve the performance by remedying the mentioned disadvantages. Compared with existing inverter topologies, (especially higher levels), this topology requires fewer components, fewer dc sources, and gate drives. Further, voltage stress is also low. The overall costs and complexity are therefore greatly reduced, especially for higher voltage levels. The proposed topology has been compared with other similar topologies and the comparison proves the better structure of the proposed topology. To show the working of the proposed topology, a prototype has been developed and tested for a different operating condition with two different modulation techniques. All the results show the adequate performance of the inverter topology at the different real-time environment.


I. INTRODUCTION
Multi-level Voltage Source Inverters (MVSIs), known as the 'Rising Power Converter' has been used in a wide variety of high and medium voltage applications during the last decades. Compared with the conventional two-level topologies, this new type of DC-AC converter provides numerous advantages in terms of its high output voltage generation using lower voltage rating devices, lower dv / dt stress, low switching power losses, less input current distortions, and so on [1]- [4]. These attractive features together with the growth of power semiconductors have led to the interface between renewables photovoltaic systems and the utilities using MVSIs for various applications [5], [6].
The associate editor coordinating the review of this manuscript and approving it for publication was Francisco J. Garcia-Penalvo .
The first multi-level topology with separate DC sources was established as a cascaded H-bridge (CHB) in the mid of 1970s. In 1980s, the three-level and five-level Neutral Point Clamped (NPC) structure has been proposed using one DC source. In the 1990s, Flying Capacitor (FC) was introduced which is regarded as the third topology in the classical category of the multilevel inverter topologies. While previously MVSIs were notable to researchers and have been widely used in industrial applications for the past decades, it remained a challenge to develop new, hybrid symmetric or asymmetrical structures to generate more voltage levels that count less components [7]- [9].
The main concerns of NPC and FC include voltage balance, need for a large number of diodes/capacitors, module failure liability due to serial switch connections. Multiple DC source-based CHB gains a strong interest compared to these single DC MLIs due to their modularity and reliability. Furthermore, symmetric CHB have easier control, while asymmetric topologies can increase the number of levels considerably with a lower device count [10], [11]. However, the CHB required more number of isolated DC voltage sources. The requirement of more semiconductor switches and DC sources is the main constraint for the early proposed MLI. Continuous research has been done in recent years to improve the MLI configuration in all possible ways. Three different varieties of MLIs are investigated, for example, switched DC MLIs, switched-capacitor MLIs, and switched-diode MLIs [12]- [14]. In [15], a symmetric switched DC configuration was suggested with a decreased number of components compared to the traditional circuitry. The backend H-bridge is not used in this topology, hence the voltage stress is on the lower side, however, it still requires isolated sources similar to the CHB for higher voltage level generation. The structures proposed in [16], [17] are modest and cost-effective in the switched DC category. Inherently, these reduced device count topologies can produce both positive and negative polarity of the voltage. Further, a higher number of voltage levels can be achieved by cascading the multiple fundamental units. Optimal structures are revealed in [18], [19] using the integrated H-bridge in the basic units that can generate 15 levels using 16 switches and 7 isolated dc sources. An extension is also possible to generate voltage levels that use different dc sources and with lower voltage stress on switches. In [20]- [22], symmetrical and asymmetrical topologies with different techniques of pulse width modulation (PWM) were introduced and tested. In [23]- [30], compact module topologies based on switched DC were evaluated in order to replace conventional MLIs.
In this paper, a high level of inverter configuration has been proposed. The proposed inverter topology is based on the reduced switch count concept. The proposed topology has been validated using both low and high switching frequency modulation techniques. The paper is organized as: In Section II, the basic module of the proposed topology with its extension has been elaborated. Section III explains the different modulation techniques. Section IV provides the power loss analysis. A detailed comparison has been provided in Section V and experimental results are provided in Section VI. The important outcome of the paper has been summarized in Section VII.

II. PROPOSED HIGH-LEVEL INVERTER TOPOLOGY
A. BASIC MODULE OF THE PROPOSED TOPOLOGY Fig. 1 shows the basic module of the proposed topology. Three voltage sources with eight switches are the main components of the basic module. It consists of two modules with the left side being the high voltage (HV) module and the right side is the low voltage (LV) module. In the HV module, the magnitude of dc voltage sources is 2V dc with switches S 1 -S 3 . The LV side consists of four switches S 4 -S 7 with a dc voltage source of magnitude V dc . The basic module generates the 11 level output voltage with magnitudes of  zero, ±V dc , ±2V dc , ±3V dc , ±4V dc , and ±5V dc . The switch pair (S 4 , S 5 ) and (S 6 , S 7 ) of the LV module are operated in a complementary fashion and only one switch from each pair is operated. Table 1 provides the different switching combinations of the basic module. Further, the corresponding connection diagrams for different voltage level generation are given in Fig. 2. As all the switches facilities the bidirectional current flow, the basic module supports the inductive load with reverse current flow. Table 3 gives the information related to the voltage stress (VS) and current stress (CS) of different switches of the proposed topology for different voltage levels with I L denotes the load current.

B. STRUCTURE OF THE PROPOSED TOPOLOGY
The proposed topology with N-level output voltage levels is depicted in Fig. 3. The HV module of the proposed topology is the same as that of the basic module and in the LV module, the number of dc voltage sources is increasing in the additive polarity. The magnitude of each dc voltage source on the LV side is selected as V dc . Based on the number of dc voltage sources in the LV module, the magnitude of dc voltage 201836 VOLUME 8, 2020   source V 1 is selected as where m is the number of dc voltage sources in the LV module. The total standing voltage (TSV) of the proposed topology can be defined as Based on (1), the required blocking voltage of the switches of HV can be determined as The switched S 4 and S 5 are the connecting switches between the HV module and the LV module. Therefore these two switches have maximum voltage stress and are given as Similarly, the maximum blocking voltage of the switches of the LV module is given as Therefore, based on the above formulation, the TSV of HV and LV are given as: From (2) and (6), the TSV of the proposed topology is given as For the proposed topology, the equation for different parameters are given as where N sw , N gd , and N dc denote the total number of switches, gate driver circuits, and dc voltage sources respectively.

III. MODULATION TECHNIQUES
The PWM technique used for pulse generation was divided into two categories based on the switching frequency: High-frequency switching PWM and fundamental frequency switching PWM technology. Sinusoidal PWM, PWM space vector and PWM hybrid modulation are some examples of high-frequency switching techniques. The number of turns on and off in these PWM techniques are high, due to which the lower order harmonics are shifted to the carrier frequency thus reducing the effect of lower order harmonics. The fundamental switching frequency modulation includes selective harmonic elimination (SHE), nearest level modulation (NLM) or nearest level control (NLC) and optimal switching angle (OSA) modulation. For high power applications, the fundamental switching modulations are mostly preferred due to lower switching losses [31]- [38].

A. LEVEL SHIFTED PWM (LS-PWM)
For all switches of the basic module of the proposed topology, the PWM signal can be produced by comparing one modulation waveform with the five carriers waveforms. As shown in Fig. 4 (a), these five high-frequency carrier waves are shifted waveforms corresponding to different levels. The waveform's peak value is V sine,peak and the modulation index (MI) is defined as Depending on the location of the high-frequency carriers, the PWM signals are produced for the switches S 1 to S 7 . Fig. 4 (b) shows the switching pulses for switches S 1 to S 7 .

IV. B. NEAREST LEVEL CONTROL PWM (NLCPWM)
The working principle of NLC is illustrated in Fig. 5 (a), where the closest level is selected by comparing the output voltage and reference voltage. In case of float numbers (1.5 V dc or 2.5 V dc ), the round function is utilized to select the nearest even number (2 V dc ). The reference signal cuts the rising edge of the output signal into two parts, upper sub-level and lower sub-level, both of which are equal in magnitude as shown in Fig. 5 (a). The firing angle of this technique can be estimated by the expression below: where where, α i is the switching angle. The NLC can be stretched out to N level and the modulation index (MI ) of it can also be changed with the reference voltage by the expression below [36].
The generated gate pulse with NLCPWM is illustrated in Fig. 5 (b).

V. POWER LOSS ANALYSIS
Losses incurred in a converter can be estimated by the accumulation of losses in the different switches and diodes. Power losses of a switch or diode may usually be defined in three groups: i) OFF state ii). ON state iii) Switching state Because leakage currents during the blocking or OFF state losses are negligible. Therefore, only conduction and switching losses are measured for estimating losses related to the proposed inverter circuitry.
The proposed topology uses eight switches and all of them have their anti-parallel diodes. Therefore, the power loss of the respective anti-parallel diodes must be considered. The conduction losses for the switch (P con,s ) and diode (P con,d ) VOLUME 8, 2020  are expressed as follows: where, V ON,s and R s denote the voltage drop and the ON-state resistance of a switch, respectively. The similar parameters for the diode are denoted by V ON,d and R d . i(t) is the load current and α is the switch constant. Now, let N s and N d be the number of conducting switches and diodes at any time, then, by using (13) and (14), average conduction losses can be expressed as: (15) A typical switch is taken into account in the calculation of total switching loss, and individual switching losses are 201840 VOLUME 8, 2020 then added to achieve total inverter switching loss. During the switching period, a linear estimate of the voltage and the current is used to estimate the switching losses on an individual switch [27]. Energy losses during the turn ON and turn OFF are used for the calculation of the switching losses and is given by (16).
where T ON and T OFF are the turn-ON and turn-OFF time respectively, E ON and E OFF denote the turn-ON and turn-OFF energy losses, respectively and f represents the switching frequency. Fig. 6 show the different plots for the power loss analysis of the basic module with NLCPWM which has been estimated using PLECS software. The input voltage source magnitude has been selected as 60V and 120V which gives the peak output voltage as 300V. The parameters of switch IKW40N65ES5_IGBT has been considered for the efficiency calculation. As shown in Fig. 6 (a), the basic module gives higher efficiency as the efficiency is 97.5 % at an output power of 1kW. In addition, Fig. 6 (b) provides power loss distribution among different switches.

VI. COMPARISON OF THE PROPOSED TOPOLOGY
In this section, a comparative study between different topologies that have a similar structure to the proposed one has been provided. Table 3 gives the comparison table for different basic modules with 11 level output voltage. The number of switches for the proposed topology is less except the topology of [28], however, the topology of [28] uses three diodes. Further, the basic module of the proposed topology is such that only three dc voltage sources are required for 11 level output voltage which is lower among other topologies. The value of TSV is also less for the basic module of the proposed topology. Fig. 7 (a) shows the plot of the number of switches with respect to the number of levels for different topologies. As shown by Fig. 7 (a), the number of switches required for the proposed topology to generate a higher number of levels is low compare to the other topologies except [19]. In [19]. The bidirectional switch in [19] has been configured as a single switch with 4 diodes. The use of diodes reduces the number of switches, however, the overall component count of [19] is higher than the proposed topology. In the proposed topology a bidirectional switch is used with common emitter/source configuration, therefore, the number of driver circuitry required is less than the number of switches. The comparison between 201842 VOLUME 8, 2020 the number of driver circuitry and the number of levels is illustrated in Fig. 7 (b). Similar to the number of switches, the proposed topology required a lower number of gate driver circuits except for topologies of [16], [18] and [19]. Fig. 7 (c) and (d) show the comparison of the number of voltage source sand TSV of different topologies, respectively. As shown in Fig. 7 (c), the proposed topology requires a lower number of input voltage sources compare to other topologies. Also, the TSV of the proposed topology has a better plot compare to other topologies. Therefore, from Table 3 and Fig. 7, it can be summarized that the proposed topology gives a better alternative for the higher number of levels with a lower number of switches with lower voltage ratings and a lower number of dc voltage sources.

VII. RESULTS AND DISCUSSION
In this section, the experimental results of the basic module of the proposed topology have been discussed. The basic module generates 11 level output voltage waveform. The basic module has been tested for different operating conditions for both experimental results. For the control of the switches, both NLCPWM and LS-PWM techniques have been used. For the experimental results, an experimental prototype has been developed and shown in Fig. 8. dSPACE controller is used to generating the gate pulses. Table 4 gives the different parameters for the experimental results. Fig. 9 (a) demonstrate the output voltage and current waveform for an RL load. The magnitude of voltage sources in the HV module is elected as 120V and the voltage source magnitude of the LV module is fixed as 60V. This gives the resultant waveform having 11 levels of step voltage of 60V having a peak magnitude of 300V. The load has a parameter of 100 +100mH. Figs. 9 (b), (c) and (d) show the change of current with different loading c-condition with the fixed output voltage. In Fig. 9 (b), the change of load type from R to RL load, i.e., from 100 to 100 +100mH has been depicted. With purely R load, the power factor (pf) of the load is unity whereas, with RL load, the pf is 0.95 lagging. Fig. 9 (c) and (d) show the step change of load with R and RL load respectively. In Fig. 9 (c), the load is changed from no load to 100 to 50 . This also gives the doubling of the load current. In Fig. 9 (d), the step change is depicted for no-load to 100 +100mH to 50 +100mH. In this condition, the load pf changes from 0.95 lagging to 0.85 lagging.
In Figs. 9 (e) and (f), the magnitude of the output voltage is depicted with the corresponding waveforms of load current. The magnitude of the output voltage can be changed by varying the MI as discussed in Section III. In Fig. 9 (e), the MI is changed from 1.0 to 0.60 with RL load. At 0.60 MI, the number of levels is reduced to 7 with a peak magnitude of 180V. Similarly, with the change of MI from 0.20 to 1.0 with R load is illustrated in Fig. 9 (f). At MI of 0.20, the number of levels is reduced to 3 with a peak output voltage of 60V.
The proposed topology has also been validated with NLCPWM. The different waveforms of output voltage and current with different operating conditions are provided in Fig. 10. The different operating conditions include the change of load pf, step change of load, and change of MI. Based on the waveforms from Fig 9 and 10, it can be concluded that the proposed topology can be operated with a different real-time environment with good performance.
Furthermore, the harmonic spectrum of the 11 level output voltage at 50Hz has been illustrated in Fig. 11. The harmonic spectrum with PD-PWM and NLCPWM has been depicted in Fig. 11 (a) and (b) respectively. With the PD-PWM technique with 2.5kHz, the dominant harmonic order is around the 50 th harmonic order. With PD-PWM, THD is 7.5%. With NLCPWM, the THD amount is slightly lower than PD-PWM with a magnitude of 7.2%.
Due to higher voltage stress across the switches of the backend H-bridge, the application of the hybrid MLI topologies in which the backend H-bridge is used for the polarity reversal, in the high-voltage system is less favorable than the traditional CHBMLI topology. Nevertheless, hybrid MLI topologies have become increasingly important in low voltage systems with available commercial MOSFETs or IGBTs up to 1.7 kV blocking voltage. The proposed topology validating its superiority over the latest MLI topologies. Therefore the proposed topology represents a promising alternative for the conventional MLI in low voltage applications. The reason is that, with the same number of dc sources, significantly less switch and source count are required for the proposed topology. Further, the proposed topology can be applied to renewable generation utilizing low-power fuel cells and photovoltaic cells. In addition, the effective use of the battery storage system can be incorporated with the proposed topology for grid-tied or electric vehicle (EV) applications. With the reduced number of control switches in the proposed topology, efficiency improvements along with good quality output voltage waveform are the desirable features in these applications.

VIII. CONCLUSION
In this paper, a new inverter topology for higher voltage levels has been proposed and discussed in detail. The basic module of the proposed topology generates an 11 level voltage waveform with three voltage sources and 8 switches. The performance of the proposed topology has been shown through the efficiency curve and several experimental results considering various real-time operating conditions. The efficiency of the proposed topology is about 97.5% at an output power of 1kW. Further, the performance of the proposed topology with different operational environments is also satisfactory.  ISLAM SALAMOV was born in Shali, Chechen Republic, in January 1991. In 2008, he graduated from high school and entered the Faculty of Physics and Information and Communication Technologies, Chechen State University. From the first year, he took an active part in the scientific and social life of the faculty. He studied electronics, radio engineering, and computer systems. By the second year, he already had basic programming skills for operating systems and various microcontrollers used in automation. He was involved in educational and scientific projects in robotics and electronics. At the end of 2009, as part of a delegation from the Chechen Republic, he took part in the All-Russian Olympiad of Information and Computer Technologies "Science of the Oil and Gas Industry -Russian Youth", organized by the global energy company Gazprom. The Olympiad consisted of various types of competitions, such as: programming, graphics, algorithms, and so on. According to the results of the Olympiad, he took 3rd place in computer graphics. This was the first prize at such a high level. Since then, he has participated in many regional, federal and international events. Took prizes. In 2012, he won a grant from the Innovation Promotion Foundation for an electronics project. In 2013, he won an IT-Start grant. He graduated from the University in 2013. Immediately after receiving his specialist degree, he began his working career. He received the Ph.D. degree in electrical engineering. He worked with the Faculty of Physics and Information and Communication Technologies as a Software Engineer, the Deputy Dean for scientific work, and later as an Assistant to the Vice-Rector for academic affairs. In 2013, he founded the first small innovative enterprise based on the Tech-park of the Chechen State University. He worked on projects in the field of unmanned aircraft systems. He held the position of Deputy Director of the Quantorium Children's Techpark, the Head of Research, Grant and International Activities of the ChSPU, the Director of the Center for Prototyping, NTI Project Office, Chechen State University. At the moment, the main activity is energy. He is currently the Head of the Solar Energy Systems Laboratory, Green Energy Scientific and Technical Center, The Grozny State Oil Technical University. He is involved in science and commercial projects in the field of renewable energy. He is also the Head of the Solar Energy Laboratory, The Grozny State Oil Technical University. He is also the Head of Research, Grant, and International Activities, CSPU. His current research interests include renewable energy system and their control, and energy efficiency. He is also a Fellow of the President of the Russian Federation for young scientists and postgraduate students who carry out promising research and development in priority areas of modernization of the Russian economy for 2021-2023.