Reversible Palm Vein Authenticator Design With Quantum Dot Cellular Automata for Information Security in Nanocommunication Network

Palm vein pattern recognition is one of the most promising and rapidly developing fields of study in biometrics, which makes it an important solution for identity security in biometrics-based user identification systems. Quantum-dot Cellular Automata (QCA) is a developing field of nanotechnology which facilitates the creation of nano-scale logical circuits. Irreversible technology has faced some difficulties, such as higher heat energy dissipation. Reversible logic is therefore essential where heat dissipation is almost insignificant. This article proposes QCA design of a reversible circuit for palm vein authentication utilizing the Feynman gate. Fully reversible Feynman gate is designed. Using this newly designed Feynman gate the palm vein authenticator circuit is designed. The theoretical values and the results of the simulation correspond to the reliability of the planned circuit. Circuit complexity and circuit cost are explored. Validation of authenticated users by the proposed authenticator explores its design accuracy as per theoretical values. Energy dissipation of the proposed designs shows that it remains within Lauderer’s limit (0.06meV). This proves that the circuits designed are fully reversible in nature and dissipates very less amount of energy. Comparison with recent QCA state of the art architectures explores its characteristics.


I. INTRODUCTION
QCA [1]- [6] is a developing field among different developing nano-electronic innovations that give a progressive move towards the nano level. In the course of the most recent decades, the microelectronic manufacturers have been upgrading in terms of speed and size of electronic gadgets. These advancements are in relevance to Moore's Law for a protracted time, which predicts that the quantities of gadgets incorporated on a chip will increase by twofold at regular intervals of eighteen months [7], [8]. It is possible to accomplish it through consistent and fast upgrades in every part of the incorporated circuit manufacture. This allows manufacturers to reduce the size of chip whereas increment the chip measure, while keeping up adequate yields. This is designed The associate editor coordinating the review of this manuscript and approving it for publication was Chaitanya U Kshirsagar. by architects and circuit designers systematically to minimize the chips' magnitude and reduce the operative current.
The unremitting advancement in gadget creation on the milli-micron scale is not solely confined due to the process of its creation, in addition to this, elementary issues rise from scaling, like quantum-mechanical impacts and extreme power dissipation. The tunnelling current of the gates is increased with the degree of minimization to submicron level for MOS (metal-oxide-semiconductor) gadgets. It has been estimated from different investigations that reduction in the size of devices is drawing nearer to its physical cut-off points. The two unique conditions can be utilized to pass on a rationale variable in two legitimate rationale states, for example, electronic spin during any physical circumstance. In an alternative way, this logic can be represented by Quantum effects. QCA [9]- [14] is among the Quantum logic devices which follow this logic. VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ Circuit depends on QCA have the advantage of high density, fast switching and low power utilization. Further, it has benefits of highly parallel processing. In recent years QCA [15]- [21] is utilized to accomplish high density, fast exchanging rate, and its ability to operate at room temperature. Different combinational circuit [22], [23] and sequential circuit representation based on QCA has been suggested in recent years but few investigation endeavours with its application in the field of communication. This article endeavours with the application field.
The palm vein validation [24]- [26] has an elevated state of confirmation accuracy because of the uniqueness and unpredictability of the vein outlines of the palm. The pattern of palm vein lies within the human body, thus it is impossible to falsify.
Additionally, the framework is contactless and sterile for use in public. It is more dominant than other biometric confirmation, in comparison to face detection, iris detection, and retina detection. Palm vein verification employs infrared rays to infiltrate through the user's hand whenever the user holds his hand above the sensor. This extracts the veins information of the user's hand. Dark lines of veins are returned which helps in authentication.
Using QCA a reversible Palm Vein Authenticator (PVA) circuit has been designed which is smaller in size and also robust in performance.
The article's effectiveness is delineated as: • Reversible majority gate is used to achieve the fully reversible QCA circuit of the Feynman gate.
• A reversible Palm Vein authenticator using the Feynman gate is designed and implemented using QCA technology.
• The designed QCA Feynman gate is contrasted with previously built circuits.
• Authenticated user validation is also performed via the proposed authenticator.
• Verification of the design's accuracy is demonstrated by theoretical values.
• Circuit complexity and circuit cost is calculated for the proposed design.
• The proposed majority gates are compared with state of art majority gates.
• Energy dissipation is calculated using QCA Designer-E and it is lesser below Lauderer's limit.
• The proposed PVA architecture is contrasted with recent QCA architectures. The article is segregated into ten sections. Background of QCA is explored in section II. Related works are shown in section III. Then section IV explores the theoretical background of the palm vein authenticator. The proposed work is explained in Section V. The architecture designs of the proposed work have been explored in Section VI. Simulation result analysis of Feynman gate and Palm Vein Authenticator is provided in Section VII. In Section VIII discussion is done on the circuit's complexity, cost calculation, comparison with prevailing constructs, validation, the quantum cost, the proposed majority gate contrasted with existing majority gate and the proposed design is also contrasted with existing designs. Section IX presents the future work. Section X entails the conclusion part.

II. QCA BACKGROUND
QCA cell is the fundamental computing unit of QCA. It is of square form with tetrad quantum wells. Electrons are present inside these two tetrad wells. They occupy the diametric positions inside the cell due to Coulombic repulsion. Tunnelling activity takes place inside the cell due to polarization. Thus, two configuration states in QCA cells are present. They reflect binary ''0'' and ''1'' denotes −1 and +1 polarization and are denoted by the letter P, respectively. A QCA cell is displayed in Fig.1.
QCA wire is composed of several cells aligned adjacent to one another, shown in Fig. 2(a). NOT gate is constructed in QCA by placing the cells in oblique orientation as depicted in Fig. 2 Other logic gates designed from majority gates are OR gate and AND gate. A three input majority gate comprises five QCA cells. Majority gate expression is represented as M (a,b,c) = ab + bc + ac. OR gate is designed by setting one of the three inputs to polarization +1, whereas AND gate is designed by setting one of the three inputs to polarization −1. The designs are shown in Fig. 3. Both inverters and other two logic gates are used for implementation of other logic functions.

III. RELATED WORK
In the past few years, works are done in the field of nano communication, image processing, and data security, utilizing QCA. The works explored in [27]- [31] are related to the field of nano-communication. In [27] a nano-sensor processor has been produced. Different functionality can be performed by the processor. In this article, the procedure to process the data has been explained and how this preprocessed data is used to obtain a sigmoid function is explored. In [28] a serial nano-communication framework has been constructed which consists of serial-to-parallel and it's vice versa communication, parity checker, and Hamming code initiator. The reversible technique has been employed in the field of nano-communication in [29]. A QCA reversible router is publicized in this article. It employs less number of cells compared to other routers constructed beforehand. JK, SR, D, and T Flipflop's reversible architecture has been proposed in [30]. A reversible crossbar switch is exhibited in [31]. It shows the strategy of the activity of switches utilized throughout nanocommunication. In correlation with the current traditional circuit, it's more cost-productive.
Data security during nano-communication is conferred in [32]- [34]. Security is provided during nano-communication by producing Ciphertext, realized using QCA in [32]. A serpent block cipher is designed in QCA to build the basic building block to obtain a block cipher. In [33] LSB bit steganography is explored using QCA. A secured text has been hidden within the LSB bit of an image and delivered to the sender. Information theory is used to enhance security. Reversible logic is used to reconstruct the LSB bit circuit for steganography to obtain a more dynamic version before the aforementioned circuitry in [34]. The complexity of the circuit has been calculated.
The arena of image processing doesn't remain immaculate by QCA, they are reported in [35]- [38]. A multichannel filter is designed in [35] utilizing QCA. The image threshold utilizing QCA has been accounted for in [36]. Median filtering is achieved in [37], applying QCA technology. In [37] usage of median filtering and effect of numerical procedures are seen over images, understood utilizing QCA based designs. One of the basic functionality of image processing is identified by the procedure convolution and correlation is performed in [38].

IV. THEORETICAL BACKGROUND A. PALM VEIN AUTHENTICATION PROCESS
Palm vein authentication is the process of comparing the outlines of veins present in the palm of an individual with a sample present within the database. Vascular patterns on a palm vary from one person to another, as indicated by Fujitsu's research which is even indistinguishable between the twins. Since the vascular pattern exists inside the body, they can't be stolen by methods for photography, fingerprints or voice recording, consequently making this strategy for biometric confirmation more secure than others. Due to this threat, palm vein verification gives a progressively secure strategy for validation and thus presently creating enthusiasm as a biometric option in contrast to conventional current techniques for confirmation like PINs or passwords.
As indicated by BIOGUARD palm vein innovation works by recognizing the subcutaneous vein designs of hand. At the point when a client's hand is held over a scanner, infrared light maps the area of the veins. The red platelets present in the veins assimilate the beams and appear on the guide as dark lines, though the rest of the hand structure appears as white. This vein pattern is checked against a preregistered sample to verify the person. As veins lie within the body and have a lot of distinguishing features, it is not easier to detect which endeavors a higher level of security. Furthermore, the sensor of the palm vein gadget can perceive the vein pattern only if the hemoglobin is effectively streaming inside a person's veins.

B. DIFFERENT PRE-PROCESSING STEPS WITH A PARTICULAR PALM VEIN IMAGE
In Fig. 4 the different preprocessing steps are represented using a flowchart. Fig. 5 shows different steps performed on a sample palm vein image. The final image is a normalized binary image in which every pixel has a value of ''0'' or ''1''. These pixel values are either stored in the database and used later for testing, or fed into a palm vein authenticator system. The steps involved in conversion are:  • The RGB image is transformed to a Grayscale image. • Then the image is cropped to acquire the required portion.
• Thereafter applying Contrast Limited Adaptive Histogram Equalization (CLAHE), the variance of the image is enhanced.
• In the next step, the image is converted from a grayscale to a binary form.
• Image Normalization is then applied to normalize the image. VOLUME 8, 2020 • The image information is extracted in the form of a 2-D matrix which contains ''1'' and ''0'' only.

V. PROPOSED WORK A. OVERVIEW OF THE PROPOSED SYSTEM
Initially, some palm vein images undergo preprocessing and the output binary data is stored within the database. A palm vein image is taken as input from the user. This image undergoes the various preprocessing steps. The preprocessing part is processed in MATLAB as shown with dotted lines in Fig. 6. The second input of the PVA is accepted from the already preprocessed data stored in the database. The binary data that is obtained from the image is fed into the QCA Palm Vein Authenticator (PVA) circuit as one of the inputs and another input comes from the database. The authentication part is shown in Fig. 3 comprises two sets of preprocessed images and QCA Palm Vein Authenticator (PVA). The PVA validates whether the user is authenticated or not. The stepby-step diagram of the proposed system is displayed in Fig.6. PVA is used to identify a user is a valid user or not. The main functionality of the PVA circuit is to compare two palm vein images and if both the palm vein images resemble then the user is genuine one otherwise not. If both the input bits are identical then the output is ''1'' otherwise if the input bits are diverse the output is ''0''. From this information, the truth table is generated where X and Y represent the inputs, and PVA out represents the output. The truth table of PVA is exposed in Table 1. Karnaugh-map is drawn from Table 1 explored in Fig.7. When all of the output bits are ''1'' generated from the circuit then the user is a valid user otherwise invalid use.
The equation derived from the given K-map is  mapped along with two outputs OUT2 and OUT1. The relation between the inputs and the outputs are given by the expressions (2) and (3).
Formerly logically reversible QCA Feynman is designed in [39], [40] using standard majority gate as displayed in Fig. 3(a). A modified reversible majority gate is designed, in accordance with articles [41]- [43] is displayed in Fig. 9(a). Reversible OR and AND gates are designed from this majority gate and depicted in Fig. 9(b) and Fig.9(c) respectively. The majority gate has 3 inputs (A, B, C) and 3 outputs (GAR1, OUT, GAR2). GAR1 and GAR2 show the copy of inputs, A and B as output respectively. OUT shows the majority value of the input as output. The OR and AND gate consists of 3 inputs and 3 outputs. One input among these three inputs of the majority gate is set to P= +1 and P = −1 respectively. OUT of OR and AND gate functions as simple OR and AND gate respectively. These circuits function on Landauer's clocking as mentioned in [43]. To design a fully reversible Feynman gate, the OR gate and AND gate designed in Fig.9(b) and Fig.9(c) are used. Since reversible basic gates are used to design the Feynman gate the block diagram of a fully reversible Feynman gate is different compared to Fig. 8 as revealed in Fig.10. Three additional inputs are fixed inputs having fixed inputs, FINP1(with P = −1), FINP2(P = −1) and FINP3(P = +1) respectively. Three garbage outputs GAR2, GAR3, and GAR4 are three. It should be noted that the number of inputs and outputs remains the same which follows the rule of reversibility of the circuit. The expression for OUT2 and OUT1 is the same as eqn.
The circuit diagram, QCA representation, and truth table of Feynman gate are revealed in Fig. 11 (a), (b), and Table 2 respectively. Reversible AND and OR gates are shown with dotted lines in Fig. 11(b). The hypothetical outputs for corresponding inputs of Feynman gate are shown in the Truth Table represented in Table 2.  Fig.10. This adds the Feynman gate's unique features to realize the proposed reversible PVA is displayed in Fig. 12.
It is noted from Fig.12 and Fig.13 the PVA circuit design is created from the fully reversible Feynman gate as depicted in Fig.10 and Fig.11 respectively. To function the Feynman gate as fully reversible each of the modules are made reversible. The reversible majority gate included in this design is similar to the articles [41]- [43]. The majority gate consists of three inputs and three outputs. Copies of inputs are obtained as outputs on two of the outputs and the middle one gives the resultant output. It eliminates the fanout problem. The Feynman gate design has two main inputs INP1 and INP2 and three fixed inputs with polarization FINP1(with P = −1), FINP2(P = −1) and FINP3(P = +1) respectively. It consists of two main outputs OUT1 and OUT2 respectively and three garbage values GAR2, GAR3 and GAR4. All of these garbage values actually denote the copy of their input values. GAR2 denotes the value same as INP2. GAR3 denotes  output value obtained from the first AND gate, similarly GAR4 denotes the output obtained from the second AND gate.
Feynman gate is a reversible gate which functions as an XOR gate. The designed PVA acts as an XNOR gate. The comparison is done between two bits to check if either bit is similar, then the result is true otherwise false. When a NOT-gate is positioned after the Feynman gate's output, OUT1 the required output will be obtained at PVA out as represented in expression (7).
The other expressions for garbage are similar to expressions (3), (4), (5), and (6). Expression (7) shows that PVA out actually functions as an XNOR gate. The XNOR gate output remains true only when both of the inputs are similar. The fully reversible PVA receives the palm vein information from an user in the form of binary values obtained after preprocessing of the palm vein image in MATLAB and validate the information with the database of preprocessed images previously exists using the proposed QCA Palm Vein Authenticator. If the information matches, the input palm vein image is confirmed as a valid palm vein image, and the user is authenticated, otherwise it is treated as an invalid palm vein image and the user is not authenticated.
The block diagram of PVA is displayed in Fig. 9. Its circuit diagram, QCA layout, and corresponding truth table are explored in Fig. 13(a), 13(b), and Table 3 respectively. Landauer's clock is applied to the PVA circuit as referred to in [43] to reduce the power dissipation. The process of authentication of user palm vein image is carried forward using the proposed reversible PVA circuit as described in Algorithm 1.

A. SIMULATION RESULTS OF FEYNMAN GATE
The simulation result of the Feynman gate circuit using the QCADesigner-E tool [44], [45] is shown in Fig 14. From the third clock pulse, the output OUT1 is observed. The sequence of input in the first input signal INP1 is ''00110011'' and in the second input signal INP2 is ''01010101''. OUT1 is one

B. SIMULATION RESULTS OF PROPOSED PALM VEIN AUTHENTICATOR
The simulation result of the proposed Palm Vein Authenticator circuit is displayed in Fig 15. From the third clock pulse, the output PVA out is observed. The sequence of input in the first input signal INP1 is ''01010101'' and in the second input signal, INP2 is ''00110011''. OUT2, GAR2, GAR3, GAR4, and PVA out are the output signals. The outputs of OUT2, GAR2, GAR3, and GAR4 correspond to equation (2), (4), (5) and (6) and PVA out respectively corresponds to the equation (7) as portrayed in Fig. 15. The output PVA out is shown with dotted lines in Fig.15.

VIII. DISCUSSIONS A. PARAMETERS USED IN QCA DESIGNER
The parameters set used in QCA Designer-E [45] to obtain the proposed circuit's simulation results as well as energy dissipation, is depicted in Fig. 16. These are the basic parameters for the QCA Designer-E tool to simulate the circuit. Both the height and the thickness of one QCA cell are 18nm. The spaces between each QCA cell are 2nm. The area of the QCA design is calculated including the space between the cells.
Two sets of parameters are explained in [45] and observed in Fig.17, are in accordance with Fig.16 used during simulation. Fig.17(a) represents technology parameters and Fig. 17(b) represents the simulation parameters. Table 4 explores the complexity of the proposed circuits. The number of majority voter gates (MVs), number of QCA cells

C. COMPARISON WITH EXISTING FEYNMAN GATES
The proposed Feynman gate is compared with some existing designs reported in [46]- [50] Table 5, in terms of the number of cells, areas employed, delay, several layers, and reversible approach used.
It is noted from Table 5 that the proposed Feynman gate is higher in terms of the amount of cells, area employed, and delay than other existing designs [46]- [50]. It is observed from Table 5 that the proposed design is functioning as a fully reversible gate. Each of the modules of the design is VOLUME 8, 2020  obtained by using reversible majority gates. Landaeur's clock is employed to ensure it is fully reversible.  Fig. 17(a) all of the outputs obtained from the eight bits are ''1'' and similarly for the total image the output is ''1'' then the user is valid. In Fig. 17(b) all of the outputs for the first eight bits are not ''1'' and therefore correspondingly for the total image the outputs are a mixture of ''1'' and ''0'', then the user is not valid. These two cases are studied and represented in Case Study 1 and Case Study 2 respectively Case Study1:

D. USER VALIDATION WITH PROPOSED CIRCUIT
The first input signal, INP1 is ''00110011'' and the second input signal, INP2 is ''00110011'', which is stored in the database as depicted in Fig. 19. The output observed from the third clock pulse. From Table 3 it is observed that when the two inputs are the same, as in either both inputs are 'LOW' or both inputs are 'HIGH' the output PVA out is 'HIGH'. The output PVA out becomes 'LOW' when one input is 'HIGH' and the other is 'LOW'. From the simulation result obtained in Fig. 19 it is observed that from the output, PVA out is an entire sequence of 1's, which proves that both the images are matched and the user is valid.

Case Study2:
The first input signal, INP1 is ''01010101'' and the second input signal, INP2 is ''00110011''. From the third clock pulse, the output is observed. As aforementioned, the   Fig. 20 is in correspondence with Table 3. It is observed that from the output, PVA out entire output sequence is not 1's which proves that both the images are not matched and the user is invalid.

E. CIRCUIT COST ESTIMATION OF THE PROPOSED CIRCUITS
The circuit cost of a QCA circuit can be calculated using QCA cost function as shown in Eqn. (8) [51], [52].It is composed of four parameters. ''M'' represents the quantity of majority gates used, ''I'' specifies the quantity of inverters used, ''C'' denotes the quantity of crossovers, and ''T'' denotes delay or latency present in the QCA circuit generated. The ''C'' term has some more description. It is one of the fundamental features depending on the number of wire crossovers. Two types of the crossover are present in the QCA circuit; they are coplanar crossover and multilayer crossover respectively. In the coplanar crossover, as its name suggests all the cells remain in a similar plane, different layers are created using different clock zones. Multilayer crossovers are composed of several layers. The assembly of a multilayer circuit in contrast to the coplanar circuit is considerably complex. The term ''C'' thus consists of two terms, C cp and C ml , where C cp denotes the coplanar crossovers and C ml denotes the multilayer crossover respectively. A relation persists between these two terms i.e. C ml = m×C cp , m is considered to be equivalent to 3. ''C'' for equation (8) is calculated by equation (9). ''k'', ''l'', and ''p'' are powers of ''M'', ''C'' and ''T'' correspondingly. Each of the exponents mentioned is assigned with a value of 2 for calculation of circuit cost.  The reversible Feynman gate as presented in Fig. 8(b) Circuit cost calculated through equation (1) and (2) is depicted underneath. Quantity of M present here is 3, I is 3, and the crossovers, C cp is 1 and C ml is 0, and the latency is T = 1.75.

F. COMPARISON OF DESIGNED MAJORITY GATES WITH OTHER MAJORITY GATES
Four types of majority gates present in QCA technology till date [36], [53], [54]. In Table 7 these majority gates are compared in terms of quantity of cells, latency, area, number of inputs, number of garbage outputs and reversibility.
It is noted from Table 7 that the number of cells, and no. of outputs in case of the proposed 3-input reversible Majority Gate exceeded in quantity of cells and number of garbage outputs but it is reversible in nature.
It is observed from Table 8 that Image Steganography and User Password Authentication reported in [34] and [39] are logically reversible whereas the proposed PVA is fully reversible in nature.

H. POWER DISSIPATION CALCULATION OF THE PROPOSED DESIGNS
The research provided in [41] shows that QCA NOT gate, reversible majority gate, reversible AND gate and reversible OR gate are reversible in nature. It is explored in [41] the power dissipation of these fundamental reversible gates is below (kBTln2) energy limit. The energy dissipation values for different input combinations (000-111) of these gates are explored in Table 9 with respect to the parameters depicted in Fig. 17. The energy dissipation value for the proposed reversible PVA circuit is calculated using QCADesigner-E and explored in Table 9. The value of energy dissipation of the PVA circuit is observed, which is below Landauer's limit (0.06meV).

IX. FUTURE SCOPE
In future a new RAM architecture will be designed in QCA. It will store the data obtained from MATLAB. Then via RAM the image data can be sent to the Palm Vein Authenticator Circuit designed in this article. Same mechanism will be followed for the data stored in the database using another RAM.

X. CONCLUSION
A novel reversible QCA-based Palm Vein Authenticator (PVA) is reported in this article. The proposed PVA is advantageous in escalating the security of data accomplished by the validation of a legitimate client. QCA utilized less power and denser nano-circuit for the proposed design. The truth table affirms the results clarifying the suitability of the circuit. The utilization of QCA upgrades the PVA circuit in two different ways. Validation of authenticated users by the proposed authenticator shows its design accuracy as per theoretical values. Circuit complexity and circuit cost have been calculated to explore its implementation cost. Energy dissipation is calculated to prove that the proposed design dissipates energy within Lauderer's limit. Comparison with recent QCA state of the art architectures explores its characteristics.
BIKASH DEBNATH received the M.Tech. degree in software engineering from the West Bengal University of Technology, India, in 2012. He is currently an Assistant Professor with the Department of Computer Science and Engineering, Swami Vivekananda Institute of Science and Technology, West Bengal University of Technology, Kolkata, India. He has more than ten publications with more than six SCI journal publications. His research interests include image processing, steganography and quantum-dot cellular automata-based image processing, and nanocommunication. He received the IET Premium Award for the Best Journal Paper from IET Circuits Devices and Systems journal in 2018.
JADAV CHANDRA DAS received the M.Tech. degree in multimedia and software systems and the Ph.D. degree in computer science and engineering (nanotechnology) from the West Bengal University of Technology, Haringhata, India, in 2011 and 2019, respectively. He has ten years of teaching experiences and eight years of research experience. He is currently an Assistant Professor with the Department of Information Technology, Maulana Abul Kalam Azad University of Technology, West Bengal. He has published more than 50 research articles in peer-reviewed journal and conferences. He has more than 30 SCI journal publications. He has good scholarly records. He has more than 40 publications with more than 25 SCI journal publications. His research interests include cryptography, steganography, quantum-dot cellular automata-based image processing, reversible logic design with quantum-dot cellular automata, and nanocommunication network design. He received many prestigious honours for the best paper publication in SCI journal. He also received the J. ALI AHMADIAN (Member, IEEE) received the Ph.D. degree (Hons.) from Universiti Putra Malaysia (UPM), in 2014. He is currently a Fellow Researcher with the Institute of Industry Revolution 4.0, UKM. As a Young Researcher, he is dedicated to research in applied mathematics. He worked on projects related to drug delivery systems, acid hydrolysis in palm oil frond, carbon nanotubes dynamics, and Bloch equations and viscosity. He has successfully received 13 national and international research grants and selected as the 1% top reviewer in mathematics and computer sciences recognized by Publons, from 2017 to 2019. He is the author of more than 70 research articles published in reputed journals, including the IEEE TRANSACTIONS ON FUZZY SYSTEMS, Fuzzy Sets and Systems, Communications in Nonlinear Sciences and Numerical Simulation, the Journal of Computational Physics, and so on. He has presented his research works in 38 international conferences held in Canada, Serbia, China, Turkey, Malaysia, and UAE. His primary research interests include development of computational methods and models for problems arising in AI, biology, physics, and engineering under fuzzy and fractional calculus (FC). He was a member of programme committee in a number of international conferences in fuzzy field at Japan, China, Turkey, South Korea, and Malaysia. He is a member of editorial board in Progress in Fractional Differentiation and Applications (Natural Sciences Publishing). He serves as a Guest Editor for Advances in Mechanical Engineering (SAGE), Symmetry (MDPI), Frontier in Physics (Frontiers), and the International Journal of Hybrid Intelligence (Inderscience Publishers). He also serves as a Referee for more than 70 reputed international journals.
NORAZAK SENU is currently an Associate Professor with the Institute for Mathematical Research, Universiti Putra Malaysia. He has published over 100 articles in peer-reviewed international journals. His main research interests include different types of differential equations and modeling real-world systems using such equations. He received several prizes for his research works from the Ministry of Education, Malaysia, and a number of governmental grants to support his scientific works.