Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5 + 5 + 6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration, the lower 10 bits of the capacitor array can ensure 10-bit conversion accuracy. Every of the upper 6 bits of the capacitor array contains a linearity calibration unit. The linearity error of the upper 6 bits is calibrated by the linearity calibration unit. The 16-bit is manufactured by a <inline-formula> <tex-math notation="LaTeX">$0.6~\mu m$ </tex-math></inline-formula> standard COMS process, and the total chip area of 6-channel ADC including pads is 6.6mm <inline-formula> <tex-math notation="LaTeX">$\times6.6$ </tex-math></inline-formula>mm. As for single channel SAR ADC, the area is 0.9mm <inline-formula> <tex-math notation="LaTeX">$\times2.0$ </tex-math></inline-formula>mm. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel differential nonlinearity (DNL) and integral nonlinearity (INL) calibration methods. The power is 80mW, corresponding to a Figure of Merit (FOM) of 48 pJ/conv.-step.


I. INTRODUCTION
For the wearable electronic devices, low power consumption is its core indicator [1], [2]. Therefore, for its core chips, they all have lower power consumption requirements. As a typical representative of low-power Analog-to-Digital Converters (ADCs), SAR (successive approximation register) capacitor array units have been widely used in the core chips of many wearable electronic devices [3]- [5]. Due to the safety requirements of the wearable device, the analog signals mostly fluctuate within a small range, so the minimum The associate editor coordinating the review of this manuscript and approving it for publication was Jenny Mahoney. resolution voltage will be significantly lower than that of ordinary application environments. For the core ADC chip, a higher number of conversion bits is required to meet the specification requirements.
SAR ADC is the core of low-power products in wearable devices. Its accuracy is mainly determined by the internal SAR capacitor array. Because the capacitor array is composed of capacitors, its static power consumption is negligible. Because the main working principle of the SAR ADC is: first use charge to scale, and then use the comparator and digital logic unit to perform the bisection [6]. As a result, it can achieve a resolution of more than 16 bits under a medium conversion rate. Therefore, for the current field of wearable devices, the analog-to-digital converters in lowpower, high-precision applications are mostly designed using SAR-type capacitor array [7], [8].
The biggest challenge lies in the high resolution SAR ADC is the mismatch of capacitor array. Techniques to compensate for the mismatch in SAR converters appeared in the open literature. They mainly belong to the following three categories: foreground calibration, background calibration and averaging. Foreground methods measure the bit weights during calibration and fix bit weight errors in digital domain during normal operation [9]. Recently, the rapid advancement of digital technology motivates the use of digital techniques especially for background algorithms. Background calibration corrects the error during the normal operation, which exists the possibility of non-convergence [10]. Averaging deal with the mismatch errors by performing multiple conversions of the same sample [11]. A novel mismatch calibration method is proposed in this work. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits.

II. OVERALL FUNCTION
The typical block diagram of the SAR ADC is shown in Fig. 1. The conversion accuracy of the SAR ADC is mainly determined by the SAR capacitor array [12]. The classic capacitor array of an N-bit SAR ADC is shown in Fig. 2.  It can be seen from Fig. 2 that for the 16-bit ADC, the total number of unit capacitors is 2 16 = 65536, and the layout area is too large to achieve. Set the number of unit capacitors used in the N-th weight capacitor to Num(N). According to the basic principles of SAR ADC, for any M bits, when the minimum unit capacitor is used, the following formulas are used [13]: S (M − 1) = Num (1) + Num (2) Here, S(M − 1) represents the summation of all of the lower-bit capacitors before the M-th weight capacitor. For example, considering the 4-th weight capacitor (M = 4), Num(4) = 8, the summation of all of the previous capacitors before the 4-th weight capacitor is: S(3) = Num(1) + Num(2) + Num(3) = 1 + 2 + 4 = 7, finally, which satisfied the Equation (3). In general, in order to meet the N-bit conversion accuracy requirements, the number of unit capacitors applied to any N bits of the capacitor array must satisfy the above formula. Therefore, for a capacitor array with a precision of more than 16 bits, on the premise of satisfying the above formula, a 5 + 5 + 6 segmented capacitor array structure can be applied, as shown in Fig. 3. The number of unit capacitors is 2 7 = 128. As shown in Fig. 3, in order to meet the requirements of Equation (3), the bridge capacitances B1 and B2 must be 32/31 times the size of the unit capacitor, so set B1 and B2 to 32/31. For the SAR capacitor array shown in Fig. 3, to ensure that the capacitor array meets the 16-bit conversion accuracy, it is necessary to ensure that the relative error of all capacitors is less than 1/2 16 . By consulting the current major IC foundry, it can be known that the current natural matching accuracy of the capacitor is about 10 bits, that is, the relative error of the capacitor is larger than 1/2 10 , and all capacitors are required to be unit capacitors. If there is a non-unit capacitor in the capacitor array, the matching accuracy will be much lower.
In summary, although the SAR capacitor array shown in Fig. 3 can solve the problem of the excessive layout area, due to the limitation of the manufacture, its conversion accuracy will be far below 10 bits. Therefore, in order to meet the performance requirements of 16-bit ADC, it is necessary to optimize the design of the schematic shown in Fig. 3.
At present, the IC foundries can ensure capacitor units with a natural matching accuracy of about 10 bits. Therefore, if all the capacitors in BIT(1)∼BIT(10) are composed of unit capacitors, there is no need to introduce any calibrations for the lower 10-bit capacitor array. As can be seen from Fig. 3, in the lower 10-bit capacitor array, only the bridge capacitor B1 is not a unit capacitor. Therefore, in this work, the capacitor B1 is firstly normalized to a unit capacitor, so that the lower 10-bit capacitors are composed of unit capacitors, and the calibration range of the SAR capacitor array is minimized.
According to the basic working principle of SAR ADC and the requirements of Equation (3), for the weight capacitor of BIT(1)∼BIT(5), the weight value is 1/2 6−M (M = 1, 2, 3, 4, 5). Therefore, on the premise of satisfying the above weight relationship, by optimizing part of the circuit so that the bridge capacitor B1 in Fig. 3 also becomes a unit capacitor, then the BIT(1)∼BIT(10) bits of the weighted capacitor are all composed of unit capacitors. This meets the capacitor production conditions of IC foundry, making the natural conversion accuracy of the BIT(1)∼BIT(10) meet the 10-bit requirement. According to the above analysis, the optimization schematic diagram of the capacitor array in this work is shown in Fig. 4. In Fig. 4, it can be easily obtained that the BIT(1)∼BIT(5) bits meet the requirements of Equation (3). In the capacitor array shown in Fig. 4, the main transition point is the bridge capacitors B1 and B2. Therefore, the equivalent capacitance analysis is mainly performed on the above two points. The bridge capacitor B1 is a unit capacitor, so the equivalent total capacitance of BIT(1)∼BIT(5) and capacitor B1 is equal to 31/32. Therefore, BIT(1)∼BIT(6) meet the requirements of Equation (3). For BIT(1)∼BIT (10), it can also be easily obtained that BIT(1)∼BIT(10) meet the requirements of Equation (3).
As shown in Fig. 4, the total equivalent capacitance of the BIT(1)∼BIT(10) bits is 31 + 31/32, and the weight capacitance of the BIT(11) is 1. Therefore, in order to meet the requirements of Equation (3) In order to prove that these two capacitor arrays in Fig. 3 and Fig. 4 work similarly during the comparison period, law of conservation of electric charge is used to transform these two segmented capacitor arrays to normal binary capacitor arrays. A voltage excitation Vref is connected to the BIT (5) in the conventional 16-bit capacitor array shown in Fig. 5, the remaining capacitors are connected to the ground. According to the conservation of electric charge in the node A: Based on Equation (5), the value of voltage in the node A is The charge stored in the capacitor array LSB−2 is equivalent to the charge stored in the bridge capacitor B1. Therefore, the charge Q c1 stored in the bridge capacitor B1 is According to the conservation of electric charge in the node B: Based on Equation (8), the value of voltage in the node B is The charge stored in the capacitor array LSB−2 and LSB−1 is equivalent to the charge stored in the bridge capacitor B2. Therefore, the charge Q c2 stored in the bridge capacitor B2 is Therefore, the total charge Q ctot1 stored in the capacitor array in Fig. 5 is (11) Assume that C ilsb2 (i=1,2,3,4,5) represents the capacitor connected to Vref in the LSB−2 capacitor array, then Equation (11) can be rewritten as: (12) A voltage excitation Vref is connected to the BIT (10) in the conventional 16-bit capacitor array shown in Fig. 6, the remaining capacitors are connected to the ground. According to the conservation of electric charge in the node B: Based on Equation (13), the value of voltage in the node B is The charge stored in the capacitor array LSB−2 and LSB−1 is equivalent to the charge stored in the bridge capacitor B2. Therefore, the charge Q c3 stored in the bridge capacitor B2 is Therefore, the total charge Q ctot2 stored in the capacitor array in Fig. 6 is (16) Assume that C ilsb1 (i = 1,2,3,4,5) represents the capacitor connected to V ref in the LSB−1 capacitor array, then Equation (16) can be rewritten as Comparing Equation (12) and Equation (17), the equivalent binary capacitor array shown in Fig. 7 can be derived from the segmented capacitor array in Fig. 3.   Compared these two equivalent capacitor arrays ( Fig. 7 and Fig. 8), the capacitors all meet the binary relationship. Therefore, these two capacitor array work similarly during the conversion period.
It can be seen from the above that the BIT(1)∼BIT(16) bits can satisfy the Equation (3), and the bridge capacitor B1 has been normalized to a unit capacitor. Therefore, when all the capacitors used in the BIT(1)∼BIT(10) bits are composed of unit capacitors, the lower 10-bit capacitor array can meet the linear capacitor production conditions of the IC foundry. Therefore, for the BIT(1)∼BIT(10) bits, the schematic diagram shown in Fig. 4 can ensure that the natural conversion accuracy is not lower than 10 bits without introducing any calibrations.
In summary, for the BIT(1)∼BIT(10) bits, because they are all composed of unit capacitance, there is no need to introduce any calibrations. However, the bridge capacitor B2 is a non-unit capacitor, so after manufacturing, capacitor B2 usually has a large error, which is equivalent to introducing a mismatch of the BIT(11)∼BIT(16) capacitors. The mismatch introduced by the bridge capacitor B2 will directly reduce the DNL and INL of the ADC. In order to meet the 16-bit conversion accuracy requirements of the ADC, calibration units of BIT(11)∼BIT(16) capacitors are introduced, as shown in Fig. 9. As shown in Fig. 9, the IC foundry can only provide 10-bit matching accuracy, and the bridge capacitor B2 is a non-unit capacitor. The weight capacitors of BIT(11)∼BIT(16) will have an obvious mismatch, and the Cal(N) unit will compensate for the mismatch of the corresponding capacitor. VOLUME 8, 2020 It can be seen from Fig. 9 that the weight of BIT(11) is 1024LSB, so in order to meet the 16-bit accuracy requirement, the minimum trimming step of DNL should be set to 0.5LSB. According to the basic principle of the AD converter, the corresponding capacitance of 0.5LSB should be 0.5C/1024 = 1C/2048. Suppose Cal1's trim steps are 0.5LSB and 1LSB, and CalN's trim steps are 0.5LSB, 1LSB, · · · , 2 N LSB. Therefore, the corresponding trimming capacitance of CalN is 1C/2048, 2 1 C/2048, · · · , 2 N C/2048. The circuit diagram is shown in Fig. 10. In the actual design, the N value in the Cal1 unit is 4. Therefore, the minimum trimming step of the Cal1 unit is 0.5LSB, and the maximum trimming step is 16LSB. By analogy, N in the Cal6 unit is 9. The minimum calibration step of the CalN unit is 0.5LSB, and the maximum trimming step is 512LSB.
As can be seen from Fig. 9 and Fig. 10, even if the foundry can only provide 10-bit matching accuracy, the SAR capacitor array in this work can also ensure that the BIT(1)∼BIT(10) bits have 10-bit matching accuracy. For the BIT(11)∼BIT(16) bits, the mismatch caused by process and bridge capacitor B2 can be calibrated by the calibration unit.
The conversion performance of SAR ADC is usually characterized by two specifications. One is the DNL error, which is defined as the maximum difference between two adjacent codes. This parameter can characterize the linearity of the ADC in a small range; the other is the INL error, which is defined as the maximum deviation of the entire input range from the theoretical curve. INL can be simply expressed as the superposition of all DNL. This parameter can characterize the linearity of the ADC in the full-scale range.
For the current IC foundries, in order to meet the 10-bit capacitor matching accuracy requirements, the size of the single capacitor must be greater than a certain value, and the smaller the layout area of the capacitor array, the better the matching. Otherwise, the gradient effect of the process will cause a gradient mismatch of all capacitors, which usually affects the INL of the final circuit.
During calibration, when the weighted capacitors of the BIT(11)∼BIT(16) bits of the final circuit are calibrated, the theoretical deviation of DNL can be less than 1LSB, so the schematic shown in Fig. 9 can guarantee the DNL performance. However, even if the circuit structure shown in Fig. 9 is used, its overall capacitance still needs at least 64. In order to achieve the best matching accuracy of the process, the overall layout area of the capacitor array may exceed the minimum span area of the linear capacitance of the foundry, resulting in the INL error. Therefore, this paper will introduce an INL calibration method, which can achieve the INL calibration of the final circuit.
By testing multiple high-precision ADCs and statistically analyzing their INL curves, it can be concluded that when the DNL value is adjusted to the minimum, there are three main types of INL waveforms for 16-bit ADCs. The theoretical models are shown in Fig. 11. The three cases in Fig. 11 represent three typical INL measurement results, it is possible that there are other results other than these three cases in Fig. 11. As for Fig. 11(a), the error is evenly distributed among all of the codes, which will not lead large error in general. The curve in Fig. 11(c) is a second order curve, the central idea in this design is to produce an opposite second order curve to counteract the error. The curve in Fig. 11(b) can be regarded as two second order curves symmetrical about the midpoint. Its calibration can be similar as Fig. 11(c). We can generate two opposite second order curves to cancel the error. Finally, in this work, we focus on the case in Fig. 11(c).
In Fig. 11(a), the INL waveform indicates that INL is mainly caused by the overall DNL, and the peak value of INL is slightly larger than the maximum value of DNL; as shown in Fig. 11(b), the INL is caused by its own nonlinearity, and there will not be a large difference between the INL and the maximum value of DNL. The INL calibration method required for this model is more complicated and the required area is too large; the INL waveform shown in Fig. 11(c) indicates that the INL is caused by its own nonlinearity, and the INL value may significantly exceed the maximum value of DNL. The area required by the INL calibration method is small.
The 16-bit ADC in this work is limited by the area, so we only calibrate the INL shown in Fig. 11(c). If the remaining two INL models appear, the INL calibration will not be performed. After normalizing the INL curve shown in Fig. 7(c), its maximum INL offset point is at 1/2 range, and the INL value of its first and last points is 0. The overall INL curve can be equivalent to a second-order parabola. This paper proposes a new INL calibration scheme. The capacitor array shown in Fig. 9 is regarded as the main capacitor array, and an additional independent INL calibration sub-capacitor array is added. The final SAR type capacitor array is shown in Fig. 12. The COMP terminal is the input port of the comparator. The main function of INL-Cal-Array is to make the INL calibration circuit shown in Fig. 13(a) generate a nonlinear voltage through a certain digital algorithm. This nonlinear voltage is also a parabola, and its peak voltage is the same as that in Fig. 11(c), but the opening direction is opposite to it. The theoretical model of this voltage is shown in Fig. 13(b).
From the analysis in Fig. 9, we can see that the corresponding capacitance value of 1LSB should be 1C/1024. Therefore, in order to meet the requirement of 16-bit conversion accuracy, the minimum trimming step of INL is set to 1LSB in this work. The trimming steps of the INL-Cal-Array calibration array are 1LSB, 2LSB, 3LSB, and 4LSB respectively; so the corresponding capacitances are 1C/1024, 2C/1024, 3C/1024, and 4C/1024, respectively.
The working principle of the INL-Cal-Array unit is that when the calibration starts, the weight switches S1∼S4 of the unit are grounded. At this time, the voltage generated by the INL-Cal-Array at the COMP terminal is a DC voltage of 0V. Fig. 13(b) is the second-order parabola, and the abscissa X represents the input codeword (range 0∼65535). The ordinate Y indicates the value of INL, and the highest value is 5LSB. The parabolic formula shown in Fig. 13 , the values of X are: 32768±32768×0.8 0.5 (represented as 32768±X 1 ), 32768± 32768×0.6 0.5 (represented as 32768±X 2 ), 32768±32768× 0.4 0.5 (represented as 32768 ± X 3 ), 32768 ± 32768 × 0.2 0.5 (represented as 32768 ± X 4 ).
When 32768 − X 1 ≤ X ≤ 32768 − X 2 or 32768 + X 1 ≥ X ≥ 32768 + X 2 , the switch S1 is connected to REF, and the switches S2, S3, S4 are all connected to 0V, and the COMP terminal will generate a voltage of 1 LSB.
When 32768 − X 2 ≤ X ≤ 32768 − X 3 or 32768 + X 2 ≥ X ≥ 32768 + X 3 , the switch S2 is connected to REF, and the switches S1, S3, S4 are all connected to 0V, and the COMP terminal will generate a voltage of 2 LSB.
When 32768 − X 3 ≤ X ≤ 32768 − X 4 or 32768 + X 3 ≥ X ≥ 32768 + X 4 , the switch S3 is connected to REF, and the switches S1, S2, S4 are all connected to 0V, and the COMP terminal will generate a voltage of 3 LSB.
When 32768 − X 4 ≤ X ≤ 32768 or 32768 + X 4 ≥ X ≥ 32768, the switch S4 is connected to REF, and the switches S1, S2, S3 are all connected to 0V, and the COMP terminal will generate a voltage of 4 LSB.
Therefore, the actual waveform generated by the INL-Cal-Array at the COMP terminal is shown in Fig. 13(c). In summary, the SAR capacitor array shown in Fig. 12 is used in this work. By performing DNL and INL calibration on the final circuit, the conversion accuracy of the final circuit VOLUME 8, 2020 can meet the requirements of 16-bit applications. Ideally, the DNL for all of the codes are 0LSB. After INL calibration, codes 32768 ± X 1 , 32768 ± X 2 , 32768 ± X 3 and 32768 ± X 4 will have DNL error. Considering a certain code 32768 − X , its analog counterpart is V 32768−X , V LSB represents one LSB voltage. The DNL error for the code 32768 − X 1 is After the INL calibration, the analog voltage for the code 32768 − X 1 is still V 32768−X 1 , while the analog voltage for the code 32768−X 1 +1 becomes V 32768−X 1 +1 −V LSB , as a result, DNL for the code 32768−X 1 is: the same is true for codes 32768 − X 2 , 32768 − X 3 and 32768 − X 4 , whose DNL error become −1LSB after INL calibration. On the other hand, DNL error for codes 32768 + X 1 , 32768 + X 2 , 32768 + X 3 and 32768 + X 4 change to 1LSB after INL calibration. In a conclusion, the INL calibration range is limited within 5 LSB, which degrades the DNL for about 1 LSB.

III. CIRCUIT SIMULATION
In order to verify the performance of SAR capacitor arrays of IC foundries, it is necessary to perform mismatch simulation on the absolute size of all capacitors in the SAR capacitor array. In this work, the ADC is manufactured using the 0.6µm standard CMOS process, so the maximum size of the capacitor is set to 0.6µm. Although the mismatch is small, it is known through theoretical analysis that SNR will not show a large deviation. However, there will be significant differences of the DNL values of BIT(6), BIT(10), BIT (11), and BIT (16). Therefore, in the simulation, we will focus on comparing the DNL parameters.
Cadence software is used for the main performance simulation. The simulation conditions are set to VDD = 12V, VSS = −12V, VLL = 5V, VREF = 2.5V, VIN = −5V ∼ 5V, and the sampling frequency is 250kHz. The VDD is the analog power supply, while the VLL is the digital power supply. This SAR ADC proposed in this work is a commercial product, which is designed to satisfy many consumers. Some consumers demand ±5V input while other consumers need ±10V input, therefore we use ±12V supply to enhance the flexibility. The block diagram of the 16-bit SAR ADC is shown in Fig. 14(a). The comparator unit COMP in Fig. 14(a) uses a three-level output offset storage structure. The schematic diagram of each output offset storage unit is shown in Fig. 14(b). The simulation results of the comparator show that: offset error < 5µV, minimum resolution ≤ 5µV, propagation delay ≤ 100nS.
The circuit diagram of the sampling capacitor and capacitor array is shown in Fig. 14(c). VIN is the input port of the analog signal, and the sample/hold capacitance is 16C, while the conversion capacitors is 64C, corresponding to the 2.5V reference voltage and 10V analog range. The design document of the 0.6µm standard COMS process used in this work shows that the relationship between the matching accuracy of the linear capacitor and the capacitor area is In order to ensure that the matching accuracy of the capacitor array is higher than 10 bit, it is necessary to satisfy σ ( C/C) /100 ≤ 1/2 10 , so the minimum area of the unit capacitor is The maximum input range of the 16bit ADC in this work is VIN = −5V ∼ 5V, so the minimum resolution voltage is 10V/2 16 = 0.000152V. In order to meet the minimum resolution requirement, the thermal noise of the sampling capacitor must be less than the minimum resolution.
The square capacitance of the process used in the technology is 1fF/µm 2 . According to Equation (6) and Equation (8), when the minimum area of the unit capacitor is 171.8µm 2 , the thermal noise will be much smaller than the minimum resolution of the 16bit ADC. In order to further improve the matching performance of the capacitor array, the size of the unit capacitor is finally determined to be 20µm × 20µm.
During simulation verification, add a mismatch to the weight capacitor, and then perform DNL calibration through the calibration network to verify the linearity calibration function.
For BIT(11)∼BIT(16), the method for judging whether there is a deviation in the weight is (for the convenience of description, take BIT(11) as an example): When the output has no missing codes, the average input voltage of output code 1024 is V 1 , the average input voltage of output code 1023 is V 2 , and the voltage of 1LSB is V LSB . If the weight of BIT(11) is smaller than the ideal value, the weight error is (11) is larger than the ideal value, for example, the ideal weight of BIT (11) is 1024, while the real weight is 1030, the summation of all of the bits lower than BIT(11) is only 1023. As a result, the DNL is 6LSB.
If there is a missing code near the output code 1023, and the largest code less than 1023 is X. Assuming BIT (11) is smaller than the ideal value, and its weight error is (1023 − X) /1024. For example, the ideal weight of BIT (11) is 1024, while the real weight is 1013, which corresponds to 01111110101 (1 + 4 + 16 + 32 + 64 + 128 + 256 + 512 = 1013). As a result, the DNL is 2 + 8 = 10LSB.

A. SIMULATION OF THE CONVENTIONAL 5 + 5 + 6 BITS CAPACITOR ARRAY
The conventional 5 + 5 + 6 bits capacitor array is shown in Fig. 3. The size of the unit capacitor is 20µm × 20µm, and the size of the bridge capacitors B1 and B2 is 20µm × 20.65µm. The simulation results show that the SNR of the conventional 5 + 5 + 6 bits capacitor array is 88.02dB, and the SFDR is 94.16dB. The SFDR simulation result is shown in Fig. 15, and the DNL simulation results of BIT(6), BIT(10), BIT(11) and BIT(16) are shown in Table 1. One of the limiting factors for the dynamic performance possibly come from the nonlinearity of the switch. Because this is a high-voltage design. The switch is a high-voltage device, whose length is about 6µm, as a result, big parasitics and on-resistance of the switch introduce the nonlinearity. The   (6), BIT(10), BIT (11) and BIT (16) in the conventional 5 + 5 + 6 bits capacitor array. poly-to-poly capacitors have been used in this design. The absolute value of unit capacitor is 400 fF. The voltage coefficient of poly-to-poly capacitor is shown in Fig. 16. Therefore, the maximum voltage coefficient is about 100 ppm (1/10000), corresponding to 14 bits resolution, which does not reach 16 bits resolution (1/65536), as a result, the limitation of voltage coefficient of capacitors is one of the reasons for not good enough performance. Finally, the resolution of comparator and the bottom plate capacitor parasitics also deteriorate the dynamic performance.

B. SIMULATION OF THE CONVENTIONAL 5 + 5 + 6 BITS CAPACITOR ARRAY WITH MISMATCH
Then we set the size of all unit capacitors to 20µm × 19.4µm (the deviation is 0.6µm), and the sizes of the bridge capacitors B1 and B2 remain unchanged. The DNL values of BIT(6), BIT(10), BIT (11) and BIT (16) are shown in Table 2. The optimized 5 + 5 + 6 bits capacitor array is shown in Fig. 4, in which the size of all unit capacitors and the bridge capacitor B1 is 20µm × 20µm. The size of the bridge capacitor B2 is 20µm × 20.65µm. Simulation results show VOLUME 8, 2020 that the optimized 5 + 5 + 6 bits capacitor array has an SNR of 88.71dB and an SFDR of 94.55dB. The SFDR simulation result is shown in Fig. 17, and the DNL values of BIT(6), BIT(10), BIT (11) and BIT (16) are shown in Table 3.   Table 4. It can be seen from Table 4 that in the optimized 5 + 5 + 6 bits segmented capacitor array, if there is a deviation in the size of the unit capacitor, the DNL values of BIT(6)∼BIT(10) will not change significantly, only BIT(11)∼BIT(16) will have obvious errors.

E. SIMULATION OF LINEAR ERROR CALIBRATION
As shown in Fig. 9, in the SAR capacitor array, only the bridge capacitor B2 is a non-unit capacitor. The process will introduce a large size deviation to the capacitor B2. Therefore, the calibration function can be simulated by giving a deviation to capacitor B2 and performing linear error calibration.
The size of all unit capacitors and bridge capacitor B1 is set to 20µm × 20µm, and the size of the bridge capacitor B2 is 20µm × 20.85µm(the deviation is 0.2µm). When the bridge capacitor B2 has mismatch, the SNR is 74.76dB and the SFDR is 84.08dB. The SFDR simulation result is shown in Fig. 18, and the DNL values of BIT(6), BIT(10), BIT (11) and BIT (16) are shown in Table 5.
It can be seen from Fig. 18 and Table 5 that when there is a size offset ( + 0.2µm) of the bridge capacitor B2, the SNR, SFDR, and DNL will have obvious errors. The DNL error will only appear at BIT(11)∼ BIT(16), and will not affect BIT(1)∼BIT (10). Then, calibrate BIT(11)∼BIT (16). After calibration, the SNR is 86.78dB and the SFDR is 92.10dB. The SFDR simulation result is shown in Fig. 19. Table 6 shows the DNL value of BIT(6), BIT(10), BIT (11) and BIT (16). As mentioned above, the minimum trimming step of Cal1 unit is 0.5 LSB. Therefore, 0 LSB in Table 6 means the error is limited to 0.5 LSB actually.

F. ANALYSIS OF SIMULATION RESULTS
By comparing the simulation results of Subsection A and Subsection C, it can be concluded that the main performance of the optimized SAR capacitor array used in this work is basically the same as the conventional structure.
By comparing the simulation results of Subsection A and Subsection B, we can see that when there is a large deviation in the conventional capacitor array, the DNL values of BIT(6)∼BIT(16) have obvious errors, which results in a large area of DNL calibration unit.
By comparing the simulation results of Subsection C and Subsection D, which shows that when there is a large mismatch in the optimized capacitor array, the DNL values of BIT(6)∼BIT(10) are almost unchanged, only BIT(11)∼BIT(16) have large errors. It can be seen from Section E that this situation is basically the same as the DNL error caused by the mismatch of the bridge capacitor B2, so DNL calibration can be performed to calibrate this DNL error by the Cal-unit of BIT(11)∼BIT (16).
In summary, the mismatch of the overall capacitor array and the bridge capacitor B2 just affect the DNL of BIT(11)∼BIT(16) but not the DNL of the lower 10 bits. It can be seen from Subection E that the DNL error of BIT(11)∼BIT (16) can be calibrated by the Cal-unit of the corresponding bit.

IV. LAYOUT DESIGN
The 16-bit 6-channel SAR ADC is manufactured using the standard 0.6µm COMS process. The chip photo of the 16-bit 6-channel SAR ADC is shown in Fig. 20. The total 6-channel ADC area including pads is 6.6mm × 6.6mm. As for single channel SAR ADC, the area is 0.9mm × 2.0mm. The polyto-poly capacitors have been used in this design. The absolute value of unit capacitor is 400 fF. Two important measures have been adopted to deal with the parasitics of the floating bottom plate of the bridge capacitor. Firstly, the 400 fF unit capacitor is large enough to overcome the bottom parasitics of capacitor B1. Secondly, custom designed layout is an effective method to mitigate the bottom parasitics. The area of the top plate of the unit capacitor is 20µm × 20µm, while the area of the bottom plate is 26µm × 26µm, larger bottom plate can shield the parasitics between the top bottom and the ground. However, the parasitics between the bottom plate and the ground will become larger, sacrificing the sampling rate.

V. CHIP MEASUREMENT
Because the ADC is a low-speed product, its main application environment is measurement and control. In order to verify the conversion accuracy more easily, the main test specifications are DNL and INL. In order to ensure the testing accuracy, we use Teradyne J750 high-precision platform for parameter testing.
As well known, if the maximum value of DNL and INL is Y LSB (Y = 2 N ), then the effective accuracy is 16 − N bits.

A. CHIP MEASUREMENT WITHOUT DNL CALIBRATION
The measurement results of the 16-bit ADC without DNL calibration are shown in Fig. 21 and Fig. 22. Fig. 21 shows the DNL measurement results over the full range, and Fig. 22 shows the INL measurement results over the full range. Theoretically, the error in Fig. 21 starts from the second bridge capacitor B2, which means Bit (11) ∼ Bit (16) lead to big DNL error, the error begins from code 1024, and abrupt jumps of DNL occur every 1024 interval. In a conclusion, theoretically, high DNL error appear at codes 1024, 2048, 3072, 4096, . . . 64512.
The DNL and INL measurement results of the lower 10-bit without DNL calibration is shown in Fig. 23 and Fig. 24.   It can be seen from Fig. 21 to Fig. 24 that before the calibration, the lower 10-bit capacitor array of the ADC did not show a significant mismatch. The ADC has a DNL value of 4.09LSB and an INL value of -97.83LSB over the full range. Therefore, the effective conversion accuracy of the ADC before calibration is about 10 bits, which is consistent with the conclusions of theoretical analysis and simulation.

B. CHIP MEASUREMENT AFTER DNL CALIBRATION
According to the measurement data, the DNL error of the 16-bit ADC in this paper is mainly introduced by the   capacitors of BIT(11)∼BIT (16). After all calibrations are completed, the main measurement data is shown in Fig. 25,  Fig. 26, Fig. 27, and Fig. 28. Fig. 25 is the DNL measurement result after DNL calibration. Fig. 27 is the DNL measurement result of the lower 10-bit after DNL calibration. The DNL is larger than 1 LSB demonstrates that there are indeed missing codes. Since we think the lower 10 bits satisfy the matching demands, the linearity error perhaps due to the lack of comparator resolution because the DNL error is basically evenly distributed throughout the whole interval. Fig. 26 is the INL measurement result after INL calibration. Fig. 28 is the INL measurement result of the lower 10-bit after DNL calibration. It can be seen from Fig. 25 to Fig. 28 that the DNL calibration of the ADC will hardly affect the linearity of the lower 10 bits, but the DNL error of BIT(11)∼BIT(16) bits will be significantly improved. Within the full input range of the 16bit ADC, the DNL is 3.51LSB and the INL is 7.36LSB after calibration. Therefore, the effective conversion accuracy of the 16-bit ADC is greater than 13 bits after calibration, which is consistent with the theoretical analysis and simulation.

C. CHIP MEASUREMENT AFTER INL CALIBRATION
As shown in Fig. 26, the shape of the INL is consistent with the model in Fig. 11(a). As mentioned above, for the two INL models of Fig. 11(a) and Fig. 11(b), INL calibration will not be performed. However, in order to verify the INL calibration function proposed in this paper, INL calibration is still performed, and the measurement result after INL calibration is shown in Fig. 29. Comparing Fig. 26 with Fig. 29, we can see that the INL calibration method used in this paper can indeed change the overall shape of the INL, thus affecting the final INL value. However, since the INL in Fig. 26 is already the most optimized INL, the final circuit does not require INL calibration.

D. MEASUREMENT OF MAIN PERFORMANCE
In order to verify the batch-to-batch consistency, the main performances of 5 final chips have been measured, and the  measurement results of the final chips are shown in Table 7. It can be seen from Table 7 that the 16-bit SAR ADC proposed in this work has an effective conversion accuracy of about 13 bits after calibration, which is consistent with the theoretical analysis. Table 8 concludes the performance comparison with the state-of-the-art works. The chip in this work is a high-voltage commercial product, therefore, advanced technology may not be applicable. Table 8 also demonstrates that the on-chip calibration will not benefit FOM, but it is of great value for the practical application.

VI. CONCLUSION
The 16-bit SAR ADC proposed in this work is manufactured by a 0.6µm standard COMS process. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel DNL and INL calibration methods. Within the full input range of the 16bit ADC, the DNL is 3.51LSB and the INL is 7.36LSB after calibration. In recent five years, he has authored more than 500 articles, such as the IEEE TRANSACTIONS ON POWER ELECTRONICS, the IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION, the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, and the IEEE ANTENNAS AND WIRELESS PROPAGATION LETTERS, among which more than 300 were registered by SCI and EI. His current research interests include integrated circuits design, RFID technology, embedded systems, wireless communications, antennas and propagation, microwave and millimeter-wave technology, smart information processing, electromagnetic compatibility, and RF/microwave devices and materials. He has been honoured as the Excellent Expert and the Leader of Science and Technology of Sichuan Province owing to his outstanding contribution.
HADI HEIDARI (Senior Member, IEEE) is currently a Senior Lecturer (Associate Professor) and the Head of the Microelectronics Lab (meLAB), School of Engineering, University of Glasgow, U.K. He has authored over 90 publications in peer-reviewed journals (e.g., the IEEE JOURNAL OF SOLID-STATE CIRCUITS, the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, and the IEEE TRANSACTIONS ON ELECTRON DEVICES) and in international conferences. He is also a member of the IEEE Circuits and Systems Society Board of Governors (BoG) and the IEEE Sensors Council Administrative Committee (AdCom). He was a recipient of a number of awards, including the IEEE CASS Scholarship (NGCAS'17 conference), Silk Road Award from the Solid-State Circuits Conference (ISSCC'16), Best Paper Award from the IEEE ISCAS'14 Conference, Gold Leaf Award from the IEEE PRIME'14 Conference, and Rewards for Excellence prize from the University of Glasgow (2018). He involves in the organising committees of the IEEE PRIME'15, SEN-SORS'16, '17, IEEE NGCAS'17, BioCAS'18, ISCAS'20,'23 conferences, and chairing three special sessions at ISCAS'16,'17,'18. He is also the General Chair of the IEEE International Conference on Electronics Circuits and Systems (ICECS) 2020. He is also an Editor of the Elsevier Microelectronics Journal and a lead guest editor of four journal special issues. VOLUME 8, 2020