4th-Order Switched-Current Multistage-Noise-Shaping Delta-Sigma Modulator With a Simplified Digital Noise-Cancellation Circuit

This paper proposes a fourth-order (2-2) switched-current (SI) multistage-noise-shaping (MASH) delta–sigma modulator (DSM) with a simplified digital noise-cancellation circuit (DNCC) by using a Taiwan Semiconductor Manufacturing Company (TSMC) $0.18~\mu \text{m}$ 1P6M CMOS process. In view of area-efficiency, we propose a small-area current-mode sample-and-hold circuit (S/H) with a modified feedback memory cell (FMC) and cross-connected bias circuit. As a result of modifications to the feedback impedance, the input impedance of the current-mode differential FMC was decreased by $[2 + (\text {g}^\prime _{\mathrm {m3}}/\text {g}_{\mathrm {m1}} - 1) \times \text {A}]$ times relative to a traditional FMC. Any input current can be processed faster than usual given low input impedance. The MASH architecture inherited a superior signal-to-noise ratio (SNR) due to a simplified DNCC, consisting of six unit-delay circuits using a master–slave D flip-flop (DFF) and a logic circuit using a Karnaugh map. Post-layout simulations reveal that the simulated SNR was 87.1 dB and the effective number of bits (ENOB) was 14.18 bits. Measurements indicated that the SNR was 64.5 dB and the ENOB was 10.42 bits—at a sampling frequency of 10.24 MHz, an oversampling ratio of 256, a signal bandwidth of 20 kHz, and a supply voltage of 1.8 V. The designed chip was measured to have a power consumption of 18.19 mW, a chip area of 0.13 mm2, and a measured figure of merit (FoM) of 331.9 (pJ/conv-step). The advantages of our modulator are its small chip area and high processing speed at all input currents.


I. INTRODUCTION
The key motivation of this study is to develop a new highorder switched-current multistage-noise-shaping (SI MASH) delta-sigma modulator (DSM) with a digital noisecancellation circuit (DNCC) for applications in motor drive systems, whose bandwidths vary from dc to a few several kilohertz (kHz). For instance, a typical Hall sensor used for motor control operates within a bandwidth that ranges from The associate editor coordinating the review of this manuscript and approving it for publication was Artur Antonyan . dc to 25 kHz [1]. A second-order SI DSM was applied in a motor drive with a digital space vector pulse width modulator (SVPWM) [2]. However, quantization noise is a major concern in second-order modulators because quantization noise limits the resolution of analog-to-digital converters (ADCs). One study on a high-order DSM for high-resolution applications reported that high-order quantization error shaping can be achieved easily through either a single-loop or multi-loop architecture [3]. Unfortunately, those second-order or highorder modulators are liable to become unstable, especially for large-input signals [4]. As an alternative, the MASH VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ architecture prevents instability by connecting several stable low-order modulators in cascade. The MASH architecture cancels the low-order quantization noise from the previous stage of the DSM by using an effective DNCC [5]. The motivation of this study is to produce a small-area chip of the 2-2 SI MASH DSM with an on-chip DNCC for threephase induction motor (IM) drive system; its produced chip was fabricated in a Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 µm CMOS process.

FIGURE 1.
Proposed predictive direct torque control mixed-mode IC with fuzzy voltage vector control and neural network PID speed controller, which is composed of an analog IC of the delta-sigma ADC and a digital IC of the motor control ASIC. Figure 1 shows the proposed predictive direct torque control (DTC) mixed-mode IC with fuzzy voltage vector control and neural network PID speed controller, which is composed of an analog IC of the delta-sigma analog-to-digital converter (ADC) and an application-specific integrated circuit (ASIC) of the three-phase induction motor (IM) drive. The functional block diagram of the proposed ASIC includes the following block diagrams: voltage calculation, phase transformation, flux estimation, torque estimation, angle selection, predictive compensation circuit, speed feedback calculation, neural network PID controller, torque error fuzzification, three-level torque error comparator, flux error fuzzification, three-level flux error comparator, fuzzy vector selection table, and shortcircuit prevention. The proposed ASIC is a digital IC, which generally occupies much space in the entire mixed-mode IC. In view of the design of delta-sigma ADC, a 4 th -order SI MASH DSM is proposed with a simplified DNCC because of its small chip area. In switched-capacitor (SC), the sampling capacitor is the parasitical capacitor between the spread lines, whereas in SI, the parasitical capacitor is between gate and source of the MOSFET (C gs ). Therefore, the chip area in SI is smaller than that in SC [6]. The SI technique is effective for three-phase IM drive system with a small chip area and a suitable resolution (ENOB ≥ 10 bits), even though it suffers from non-linearity that is caused by the harmonics in the SI memory cell [7].
The fundamental problem in MASH architecture is the noise leakage, which is due to the mismatch between the analog coefficients and compensating DNCC. An effectively designed MASH architecture can deliver a high signalto-noise and distortion ratio (SNDR) if its designers correctly considered process variations, thermal noise types, and quantization errors [8]. To counteract this mismatch, the analog circuit must be carefully designed. Relative to a switchedcapacitor circuit, a switched-current (SI) circuit performs better owing to its high speed, small chip area, and low supply voltage [9]. Unfortunately, an SI circuit can suffer from transmission errors, clock feedthrough (CFT) errors, nonlinearity, and high power consumption [10]. The CFT errors can be minimized by means of a current minimum function in place of a sampling switch [11]. The transmission speed can be improved by reducing the input impedance by a factor of two. Furthermore, the transmission error can be minimized with the assistance of a current-mode feedback memory cell (FMC) and a common-mode feed-forward (CMFF) circuit. Those adopted circuits not only minimize the offset current but also improve the linearity [12].
Various digital calibration techniques have been published to extract noise and distortion from desired signals [13], [14]; these techniques can deliver high-SNDR ADCs. As reported in [15], a least mean squares (LMS) algorithm-based adaptive line enhancer can assess a desired signal from an input noise signal by informing DNCC coefficients, leading to an enhancement of SNR by >20 dB. The LMS-based arrangement delivers a superior matching coefficient between the analog modulator and DNCC. A study reported a DNCC that occupied a chip area of 0.59 mm 2 with respect to the total active area of 0.68 mm 2 ; that device consumed a power of 47 mW relative to a total power of 183 mW [16]. Any digital calibration technique, such as DNCC, is complex and occupies the majority of chip area, thus precluding high power consumption.
In this study, a fully differential 2-2 SI MASH DSM with a simplified DNCC was fabricated using TSMC's 0.18 µm 1P6M CMOS process. Simulated and measured results were completed with a bandwidth of 20 kHz, an oversampling ratio of 256, a sampling frequency of 10.24 MHz, and a supply voltage of 1.8 V. The features of this study's device are excellent SNR, a small chip area, and a high figure of merit (FoM)-from the current-mode S/H circuit with modified FMC, cross-connected bias circuit, and simplified DNCC. The rest of this paper is organized as follows. Section II elucidates the system design of the 2-2 SI MASH DSM and its circuit, implemented with a current-mode S/H circuit with two modified FMCs and a differential cross-connected bias circuit. Section III explains the circuit design of the simplified DNCC using a Karnaugh map and its logic circuit, implemented with master-slave DFFs and NAND-NAND circuits. Section IV presents the simulated and measured results. Section V presents the conclusions. Figure 2 displays a block diagram of the 2-2 SI MASH DSM with a 1-bit quantizer, which is composed of two cascade second-order modulators: one for the primary stage and the other for the secondary stage. The proposed topology performs with a completed stability in the perspective of lower-order modulation, whose order is ≤ 2 [4]. As illustrated in Fig. 2, the primary stage is a second-order modulator, which includes two discrete-time integrators, two digital-toanalog converters (DACs), and a 1-bit quantizer. Not only in the first integrator but also in the second integrator, each output swing relies on the input range of the previous integrator and the gain of a DAC. For instance, the first integrator receives the input function, which is equal to (X(z)−b 1 Y 1 (z)) with the input signal X(z); the gain of DAC b 1 ; and the output signal of the primary stage Y 1 (z). The first integrator then drives the second integrator by multiplication with an analog coefficient a 1 . Next, the second integrator is fed with a combined function-which contains the output of the first integrator, an analog scaling coefficient a 1 , DAC gain b 2 , and the output of the primary stage Y 1 (z). The output of the second integrator is connected to the following 1-bit quantizer with a quantization error Q 1 (z). In a manner similar to that of the secondary stage, the input signal X(z) is replaced with (Y 1 (z)−Q 1 (z)) and those DAC gains and analog coefficients are adjusted. The maximum levels of the in-band input signals, X(z) and (Y 1 (z)−Q 1 (z)), must remain within the maximum levels of the feedback signals, Y 1 (z) and Y 2 (z), respectively, to maintain the stability of the modulator.

A. 2-2 SI MASH DELTA-SIGMA MODULATOR
The primary stage of the 2-2 MASH DSM comprises two discrete-time integrators, two 1-bit DACs, and a 1-bit quantizer; this stage forms a second-order modulator. To obtain high performance, an integrator must be insensitive to the sampling frequency. This can be accomplished using a SI integrator, which provides an area reduction of approximately 72% compared with a switched-capacitor (SC) integrator [6]. Furthermore, the operating speed of the SI FMC is about 70% greater than that of the traditional FG SI MC [17]. If the quantization errors of the 1-bit quantizer are Q 1 (z) and Q 2 (z) in the primary stage and secondary stage, respectively, the signal transfer functions, STF 1 and STF 2 , and noise transfer functions, NTF 1 and NTF 2 , of the primary stage and secondary stage are expressed as follows: The signal transfer function (STF) and the quantization noise transfer function (NTF) of each modulator depend on the analog scaling coefficients and DAC gains. These coefficients and gains are selected for minimal quantization noise, superior signal levels in the transition, and physically realizable blocks, such as integrators and DACs [11], [17]. The analog scaling coefficients of the modulator and the DAC gains are listed in Table 1. and As illustrated in Fig. 3, the system requires a delay unit (z −1 ) to complete an integrator. The function of the integrator can be expressed as follows: Two current-mode sample-and-hold circuits, S/H-1 and S/H-2, are used to establish a delay unit (z −1 ). If one integrates the non-overlapping clocks, φ 1 and φ 1 , with the specifications of a sample-and-hold circuit (S/H), the desired sample-and-hold circuit can be implemented with a pair of FMCs. VOLUME 8, 2020

B. PROPOSED SWITCHED-CURRENT FEEDBACK MEMORY CELL
A traditional FMC, which was reported in [11], offered a system with low input impedance and small transmission error. The input impedance R in of the traditional FMC is given by where g m1 is the transistor transconductance of the first input MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). In general, a diode-connected NMOS transistor introduces an input impedance of 1/g m . The input impedance of the traditional FMC is half that of a diodeconnected NMOS transistor. The lower the input impedance is, the higher the transmission rate is. where Specifically, g mi is the transconductance of the i th MOSFET and A is the voltage gain (i.e., A = V 1 /V X ). As formalized in (12) and (13), the input impedance R in is given by To have identical transconductances between M1 and M6, and between M4 and M7, respectively (i.e., g m1 = g m6 and g m4 = g m7 ), the width-to-length ratio of each MOSFET must be modified carefully. Subsequently, the input impedance of the proposed FMC can be simplified into the following.
According to Kirchhoff's Current Law at node V 1 in Fig. 4(b), the relational function between V x and V 1 can be expressed as follows.
where R f is a feedback resistor between the drain and gate of M 2 , g m3 = g m3 + (1/r o2 ) + (1/r o3 ), and r oi is the drainsource resistor of the i th MOSFET. The voltage gain A can be obtained as follows.
As shown in (18), if (g m3 − g m1 ) > 0 and A > 0, then R in < 1/(g m1 + g m2 ). If we carefully modify both the transconductances, g m1 , g m2 , and g m3 , and the resistor R f , we can obtain an input impedance of the proposed FMC that is lower than that of the traditional FMC, as formalized in (11). The advantage of the proposed FMC is that one can modify the input impedance R in by changing R f , g m1 , g m2 , and g m3 , simultaneously.
C. PROPOSED CURRENT-MODE SAMPLE-AND-HOLD CIRCUIT Figure 5 depicts the proposed current-mode S/H circuit, which is composed of two switched-current (SI) FMC circuits with cross-connected bias circuits, one coupled differential replicate (CDR) with a CMFF circuit, and two filter capacitors, C 1 and C 2 . The proposed SI FMC circuit is utilized to lower an input impedance and to reduce a small transmission error by modifying the feedback resistor R f . The crossconnected bias circuit is added to stabilize the bias voltage and to enhance the common-mode voltage gain. Furthermore, the CDR with CMFF circuit is employed in compensating for the error of the current mirror, which is caused by either the difference of the drain voltage or the process variation [18]; the cross-connected CMFF circuit is also used to stabilize the bias voltage at the input terminal.
In the common-mode operation, both CMOS switches are open, and two nodes, A and B, are connected each other in the differential FMC with the bias circuit. This arrangement guarantees the stability of the bias voltage at the input terminal of the proposed current-mode S/H circuit. In the differential-mode operation, a positive small-signal current i d occurs at M 13 with an input current of I in+ and a negative small-signal current −i d occurs at M 23 with another input current of I in− . Subsequently, the collector current of M 13 is increased to I B +i d , and the collector current of M 23 is reduced to I B − i d . Meanwhile, the collector current of M 14 is I B + i d and the collector current of M 24 is changed to I B − i d with a constant bias current of I B . Consequently, the output currents of the positive terminal i o+ and the negative terminal i o− are appropriate at 2 × i d and −2 × i d , respectively. Figure 6 presents the simulated transmission errors, in %, of the traditional and proposed FMCs. The proposed FMC performs with an approximately ±0.10% transmission error for the differential input current ranging from −35 µA to +35 µA, whereas a traditional FMC operates with not only a large transmission error of ±0.25% with respect to the input current ranging from −20 µA to +20 µA but also an oscillation phenomenon. The proposed FMC delivers not only a small transmission error but also has superior stabilization relative to a traditional FMC.
Next, a MOSFET is utilized to complete the feedback resistor R f by setting it to operate in the triode region. In this study, a PMOS transistor was used as an electronically controllable resistor in the proposed FMC, which plays a crucial role in reducing the input impedance. Unfortunately, the PMOS is highly sensitive to the variation in temperature. To remedy this fault, a transmission gate is considered in series with PMOS to have a small temperature variation. Figure 7 presents the percentage transmission error for applied temperatures from −40 • C to 80 • C. In Fig. 7(a), the feedback resistor was only completed with a PMOS, whereas the feedback resistor was implemented with a PMOS in series with a transmission gate in Fig. 7(b). If the temperature range varies from −40 • C to +80 • C, the transmission error of Fig. 7(a) changes from 0.0% to 9.8%, and the transmission error of Fig. 7(b) varies from 0.0% to 0.34%. Clearly, the feedback resistor, which is completed with a PMOS in series with a transmission gate, is not highly susceptible to temperature variation. Figure 8 presents a 1-bit cascode current-mode DAC with two complementary switches, D 1 and D 1 , which are controlled with thermometer codes [18]. As the switch D 1 is on, the output current I out flows outside the DAC with a bias current I DA , whereas the output current I out flows inside the DAC, so that I out = −I DA , as the switch D 1 is on. Note that the bias current VOLUME 8, 2020  I DA is controlled with a bias voltage V bias . The advantages of this DAC circuit are the high current swing and the ability to equalize the output current using thermometer code. . If the Reset switch is turned on, both output voltages will be equal. Thus the differential output voltage is roughly zero [18].

III. CIRCUIT DESIGN OF SIMPLIFIED DNCC
A 2-2 SI MASH DSM provides two second-order NTFs, NTF 1 and NTF 2 , in the primary stage [Y 1 (z)] and second stage [Y 2 (z)], respectively. By designing a favorable DNCC, we can obtain a fourth-order NTF from the secondary stage and eliminate a second-order NTF from the primary stage of the 2-2 MASH DSM, as illustrated in Fig. 10. The DNCC converts two outputs, Y 1 (z) and Y 2 (z), of the 2-2 MASH DSM into a single output digital word Y(z), which is a fourthorder output with a fourth-order NTF. The output digital word includes many numbers and characteristics of the digital filter to assist in processing the received signal. The numbers and characteristics of the output digital word depend on the analog scaling coefficients of the 2-2 MASH DSM as well as the coefficients of the DNCC. The mathematical model of the adopted DNCC is given as follows. (21) where d 1 , d 2 , H 1 (z), and H 2 (z) can be substituted with 1.0, 4.0, z −2 , and (1 − z −1 ) 2 , respectively. Substituting (7) and (8) in (21) results in the following alternative expression for Y(z).
The aforementioned equation clearly indicates that the output digital word Y(z) of the DNCC performs with a four unit-delay (z −4 ) of the input signal X(z) and a fourth-order noise function of the quantization error Q 2 (z) in the secondary stage. The adopted DNCC thoroughly eliminates the quantization noise Q 1 (z) of the first stage. Subsequently, Eq. (21) can be rewritten as follows.
where A, B, C, D, and E are z −3 Y 1 (z), z −4 Y 1 (z), Y 2 (z), z −1 Y 2 (z), and z −2 Y 2 (z), respectively. The DNCC is composed of six delays (z −1 ): four delays for Y 1 (z) and two delays for Y 2 (z). Figure 11 presents the modified DNCC with six delays. Fundamentally, a master-slave flip-flop is utilized to construct the unit delay circuit. With respect to propagation delay and variability, a comparative assessment of the masterslave flip-flop is provided in [19]. Relative to the strongarm flip-flop (SAFF), data-mapping flip-flop (DMFF), conditional precharge sense-amplifier flip-flop (CPSAFF), conditional capture flip-flop (CCFF), and adaptive-coupling flip-flop (ACFF), the adopted master-slave flip-flop not only improves the propagation delay and timing skew but also minimizes the number of transistors, thereby minimizing the chip area. The advantage of the adopted master-slave flip-flop is that the maximal clock frequency of the entire system is up to a few GHz, and this flip-flop can perform at the system's maximal pace. Figure 12 presents the adopted master-slave flip-flop, which is used to implement the required unit delay circuit. The multiple nonoverlap delayed pulsed clock signals are used to resolve the timing problem between latches. As illustrated in Fig. 11, the output Y(z) is a digital word, which varies from −19 to +19. If five letters, A, B, C, D, and E, are set to −1, +1, −1, +1, and −1, respectively, the minimum value of Y(z) is calculated as −19. The maximum value of +19 is obtained by flipping the letters' signs to +1, −1, +1, −1, +1, respectively. Therefore, a 6-bit digital word, S 6 to S 1 , is utilized to represent those output values from −19 to +19. The term S 6 is the most significant bit (MSB), and S 1 is the least significant bit. Table 2 presents the output digital word of DNCC in six bits, S 6 to S 1 , in two's complement form. That is, the negative category values appear as a complementary positive number.
From Eqs. (30) to (34), the NAND-NAND logic circuit of the DNCC can be implemented with a Karnaugh map, as depicted in Fig. 13. Figure 14 presents the simulated waveforms of the designed DNCC, which was implemented with a unit delay circuit using a master-slave flip-flop and a NAND-NAND logic circuit using a Karnaugh map. As formalized in Eq. (23), the input of the primary stage Y 1 (z) must be delayed 3 clocks (3T) and 4 clocks (4T) to generate A and B, respectively; the input of the secondary stage Y 2 (z) must be copied to generate C (0T) and then delayed 1 clock (1T) and 2 clocks (2T) to generate D and E, respectively. In item 9 (A-E) of Table 2, five inputs, A = −1, B = +1, C = −1, D = −1, and E = +1, are entered to generate a digital output word Y(z) of 5, which is calculated with the formula Y = (2A − B) + (4C − 8D + 4E) and is displayed as ''000101'' in six bits, S 6 to S 1 , in two's complement form. A comparison of the simulated results in Fig. 14 with Table 2 proved that the designed DNCC with the unit delay circuit and the NAND-NAND logic circuit works correctly. Next, Laker  According to the post-layout simulation, the SNDR, the effective number of bits (ENOB), and the power dissipation were 87.1 dB, 14.18 bits, and 18.19 mW, respectivelyat a clock frequency of 10.24 MHz and an oversampling ratio (OSR) of 256. Figure 15 presents the simulated power spectrum density (PSD) of the designed 2-2 SI MASH DSM  with DNCC. After the post-layout simulation had been verified, the designed DSM with DNCC was implemented using TSMC's 0.18µm 1P6M CMOS process. Figure 16 depicts the chip microphotograph of the proposed 2-2 SI MASH DSM with DNCC. Figure 17 presents the measured platform, including information on the device under test (DUT) printed circuit board (PCB), ultralow distortion function generator (SRS DS360), synthesized signal generator (Anritsu MG3642A), precision measurement dc supply (2280S-60-3), digital signal analyzer-oscilloscope (Keysight DSAV134A), logic analyzer (Agilent 16902B), and MATLAB software. The signal generator provided a sampling frequency of 10.24 MHz, the ultralow distortion function generator generated a differential input sine wave, and the oscilloscope was used not only to display the output waveform in the time domain, but also to  process the fast Fourier transform analysis in the frequency domain. Finally, the digital output code was captured by the logic analyzer and imported into the MATLAB environment for calculation of the SNDR and ENOB. The power regulators of a bias circuit (bias power), a digital circuit (digital power), and an analog circuit (analog power) were separated to prevent power interference in the DUT PCB. The precision measurement dc supply was considered to have a stable power supply.

IV. SIMULATION AND MEASUREMENT RESULTS
In view of the negative effect of power noise, guard rings were utilized to separate the analog circuit from the digital circuit. Figure 18 presents the measured PCB of the proposed SI 2-2 MASH DSM with DNCC. The input sine wave was fed to the designed chip to measure the SNDR of the 2-2 MASH DSM and the 6-bit digital output word of DNCC. This study argues that the bias voltage at the input terminal was changed with DAC feedback. Thus, a cross-connected CMFF circuit was utilized to stabilize the common-mode bias voltage at the input terminal, as illustrated in Fig. 5. Figure 19 presents the measured 65535-point PSD of the proposed 2-2 SI MASH DSM with DNCC at an input current of 20 µA, a sampling frequency of 10.24 MHz, a signal bandwidth of 20 kHz, and an OSR of 256. When a signal frequency of 10.47 kHz was considered with coherent sampling calculation [21], the proposed SI MASH DSM with DNCC yielded an SNDR of 64.5 dB, which was approximately 10.42 bits; this was achieved by setting two control voltages, V crf1 and V crf2 , to 0.9 V, simultaneously, and three bias voltages, V b1 , V b2 , and V b3 , to 0.25 V, 1.05 V, and 1.4 V, respectively, as shown in Fig. 18. The post-layout-simulated SNDR of 87.1 dB can be compared with the measured SNDR of 64.5 dB; the difference was generated from the analog circuit. Furthermore, process variation, thermal noise, and time delay caused the discrepancy between the measured and simulated SNDRs, especially for the DSM circuit. To remedy those effects, we considered the modified FMC and the crossconnected bias circuit, and sought to enhance the resolution of the ADC. Those impairments still persisted, despite our implementation of numerous improvements. Table 3 summarizes the performance of the proposed SI MASH DSM developed herein and compares it with other SI DSMs. The performance comparison proved that the input current and measured SNR are better than those in [18]. Furthermore, the simulated SNR, measured SNR, simulated ENOB, measured ENOB, simulated FoM and measured FoM of the proposed 2-2 SI MASH DSM are superior to those of other SI MASH DSMs [11], [22]- [23]. The proposed 2-2 SI MASH DSM was significantly improved by the modified FMC and the cross-connected bias circuit. Besides, the proposed 2-2 SI MASH DSM has many advantages, such as its sampling frequency and chip area. The core area of 0.13 mm 2 is the smallest size of all that had been cited. Unfortunately, the power dissipation of 18.19 mW is inferior to that of its counterparts in SC DSM [24], [25]. The FoM is defined as follows [26]. In this paper, we proposed a novel current-mode S/H circuit with very low input impedance using a feedback resistor R f . By integrating a modified FMC with a cross-connected bias circuit, the post-layout simulation proved that the SNR was 87.1 dB and the ENOB was 14.18 bits at a sampling rate of 10.24 MHz, an OSR of 256, and a signal bandwidth of 20 kHz. Subsequently, a master-slave flip-flop was utilized to construct a unit delay circuit, which performed at a high clock frequency [19]. The main advantage of the proposed SI MASH DSM with DNCC is its small chip area, which is approximately 0.13 mm 2 . The performance of the proposed SI DSM was significantly improved by the modified currentmode S/H circuit with its modified FMC and cross-connected bias circuit. Measurements revealed that the SNR and ENOB were 64.5 dB and 10.42 bits, respectively. Both the simulated FoM of 24.5 pJ/conv-step and the measured FoM of 331.9 pJ/conv-step were better than those characteristics of a similar SI architecture. In future projects, we need to improve the resolution of SI MASH DSM by eliminating the impact of charge injection, clock feedthrough, offset of the second integrator, and quantization errors. If a small chip area and a fast sampling frequency (i.e., low input impedance) are required, the SI MASH DSM with DNCC is an excellent selection.