A Three-Phase Constant Common-Mode Voltage Inverter With Triple Voltage Boost for Transformerless Photovoltaic System

This paper introduces a new three-phase two-level inverter based on the switched-capacitor voltage multiplier. By adding a voltage multiplier network at the DC side of the traditional three-phase inverter topology, the DC-link voltage of the introduced inverter is stepped up to triple of the input voltage. Compared to the existing solutions, the common-mode voltage of the introduced topology is kept constant. Moreover, the voltage stress across additional semiconductor components is the same as one-third of DC-link voltage. Operating principles, mathematical analysis, circuit analysis, and pulse-width modulation (PWM) method based on the Boolean logic function for introduced inverter are presented. A comparison of the introduced inverter with other inverter topologies is also reported. The simulation results are shown to verify the introduced three-phase triple voltage boost inverter. Besides that, a laboratory-built prototype is developed based on a DSP F280049C microcontroller and the corresponding experimental tests are provided to prove the introduced inverter.


I. INTRODUCTION
In the recent period, transformerless grid-connected photovoltaic (PV) inverters have been receiving more and more attention from many researchers due to their inherent benefits of small size and volume, less complexity, high efficiency, low cost, and easy to install [1], [2]. Nevertheless, the removal of the transformer makes the PV array and the power grid has a direct electrical connection. This raises the leakage current in the PV system if the voltage across on the parasitic capacitance between the ground and PV array varies with high frequency. This leakage current flows between The associate editor coordinating the review of this manuscript and approving it for publication was Canbing Li. the ground and PV array through the parasitic capacitor, which causes a variety of unwanted problems such as serious electromagnetic interference (EMI) and insecurity, higher losses, higher current harmonics, and the low reliability of the transformerless grid-connected PV inverter systems [3]- [5]. Because of these, the leakage current flow in the gridconnected PV systems must be less than the VDE standard of 300 mA [6] to avoid the unfavorable effects. The leakage current can be limited by restricting amplitude and frequency of the common-mode voltage (CMV) or floating PV array from the grid on DC side of the inverter during certain time intervals. In order to eliminate leakage current, numerous interesting approaches have been reported in the prior works. In general, these approaches can be labeled into two types, namely the modulation-based approaches and the hardwarebased approaches. Recently, many CMV modulation-based methods have been discussed in the literature. To limit the amplitude of CMV, the near-state PWM (NSPWM) [7], [8], remote-state PWM (RSPWM) [9], [10] and active zero-state PWM (AZSPWM) methods [11]- [13] presented that only active vectors are considered to generate the desired voltage vector. In NSPWM and AZSPWM methods, the amplitude of CMV is restricted within 33% of the DC-link voltage. With the RSPWM method, CMV can be kept constant. Nevertheless, the RSPWM methods only perform linearly with low modulation index while NSPWM methods only perform linearly with high modulation index. Besides that, NSPWM methods, RSPWM methods, and AZSPWM methods produce bipolar output line to line voltage. Bipolar nature of the output line-to-line voltage rises the losses and voltage stress on filter inductor. In [14], the carrier phase-shift PWM based reverse injection scheme was presented to restrict the amplitude of CMV. In this scheme, low-frequency harmonics in the CMV was significantly reduced. However, the amplitude of CMV was only restricted within 33% of DC-link voltage with a low modulation index. The interleaved carrier technique was discussed in [15] to reduce the RMS value of the CMV by minimizing the appearance of the zero vectors. However, the amplitude of CMV was equal to DC-link voltage. In [16], a virtual space vector modulation method was introduced to limit the third-order harmonics in the CMV. This method only operated linearly with low modulation index. The model predictive control (MPC) based CMV reduction strategies were discussed in [17] and [18] to control the output currents with the fast transient response as well as limit the amplitude of CMV. The amplitude of CMV is restricted within 33% of DC-link voltage.
To overcome the drawbacks associated with the above modulation-based methods, the hardware-based methods have been discussed for the CMV reduction. A hybrid filter which includes an active common-mode filter and a passive filter has been introduced in [19] in order to reduce variations of the CMV. Although this filter technique is effective in restricting variations of the CMV, it has drawbacks of being bulky or complex. Instead of using conventional two-level voltage source inverter (VSI) topology, various inverter topologies and corresponding modulation strategies were introduced in [20]- [25]. A four-leg inverter topology, which adds two-switch paralleled to two-level three-phase voltage source inverter, has been presented in [20] to achieve the constant CMV. However, this topology requires additional weight and volume due to using an additional LC circuit. Besides, the output of this topology is bipolar as well as the modulation index is also limited. Another good solution was introduced in [21]. By combining a voltage-clamping network and two-level three-phase voltage source inverter, CMV of the voltage-clamping inverter topology is bounded in the range from one-third to two-thirds of DC-link voltage. In [22], the embedded-switch inverter (ESI) topology and corresponding modulation scheme were introduced to limit the high-frequency leakage current by adding six switches and two capacitors into two-level three-phase voltage source inverter. As a result, the CMV is kept as one half of DClink voltage all the time. An improved circuit topology with eight switches has been introduced in [23]. By controlling two extra switches to disconnect the input DC source from the inverter during zero states, the variation of CMV is restricted within one-third of DC-link voltage. In the improved H8 topology [24], CMV during zero states is clamped to twofifths of DC-link voltage by controlling two extra switches. As a result, the variation of CMV is also restricted within one-third of DC-link voltage. Xiaoqiang Guo et al. [25] presented zero-voltage-state rectifier (ZVR) topology to restrict the high-frequency leakage current. The CMV of the ZVR topology is maintained as half of the DC-link voltage all the time. Due to voltage-boosting capability, the switchedcapacitor topologies [26]- [28] have been gaining increasing attention these days. As presented in [26], a switchedcapacitor network that consists of seven semiconductors and three capacitors is inserted into between three-phase Neutral-Point-Clamped multilevel inverter and input voltage source. As a result, the DC-link voltage is triple of the input voltage. In [26], the input current of the inverter circulates through four semiconductors on each operating stage, which results in high conduction power loss in the switched-capacitor network. Sze Sing Lee et al. [27] presented a single-phase switched-capacitor-based multilevel inverter which combines a T-type inverter and a switched-capacitor network. In [27], the neutral of load (ac output side) and the midpoint of dc-link is connected directly, which results in low leakage current. Unlike [26], to produce a DC link voltage which is triple of input voltage, the switched-capacitor network in [27] requires twelve semiconductors and six capacitors. In [28], SCVD topology, which combines a two-level threephase voltage source inverter and a voltage-doubler network, has been proposed to reduce CMV. The variation of CMV can be limited within one-sixth of DC-link voltage. However, SCVD topology generates bipolar output line-to-line voltage and the modulation index is also limited.
In light of the above, a new three-phase constant commonmode voltage inverter (CCMVI) with a novel modulation strategy is presented in this paper. The introduced topology is a combination of a voltage multiplier network and a twolevel three-phase voltage source inverter. Compared to the topologies and modulations in existing works, CMV of proposed topology can be kept constant. The other remarkable feature of the proposed topology is voltage boost capability. In contrast to [21], the proposed topology uses a voltage multiplier network to restrict the CMV in lieu of a voltageclamping network. Compared to [28], the DC-link voltage of the proposed CCMVI is 1.5 times more than that of SCVD topology. When compared to the inverter in [26], the switched-capacitor network in the proposed inverter uses one more semiconductor. However, the input current of the proposed inverter only circulates through three semiconductors during even active states. And, this current only circulates VOLUME 8, 2020 through two semiconductors during zero state. Meanwhile, the input current of the inverter as presented in [26] circulates through four semiconductors on each operating stage. Furthermore, in the introduced topology, the voltage stress across additional semiconductor components is equal to onethird of DC-link voltage instead of half of DC-link voltage as SCVD topology. In contrast to [7]- [13], [20] and [28], the proposed CCMVI produces unipolar output line-to-line voltage. As a result, the stress and losses for filter inductor are significantly reduced. Also, a comparison between the proposed CCMVI and the existing solutions is illustrated. Common-mode leakage current model, operating principle, and the PWM control technique applied to the proposed topology are reported in section II. A comparison of the proposed inverter with the other inverters in terms of the component count, voltage linearity, and voltage gain, etc. is shown in section III. Section IV provides simulation results. Finally, the experimental results are given in section V.

II. PROPOSED THREE-PHASE CCMVI TOPOLOGY
The schematic diagram of the proposed CCMVI topology is depicted in Fig. 1. A switched-capacitor voltage multiplier (SCVM) network that consists of four switches, four diodes, and three capacitors is inserted into between two-level threephase voltage source inverter and input voltage source. The common-mode loop model of the introduced CCMVI topology is depicted in Fig. 2.

A. COMMON-MODE LEAKAGE CURRENT MODEL
Assuming that the grid is ideal, based on Fig. 1, the following mathematical equations are obtained: where, V AO , V BO , V CO , and V OO are phase A, B, C voltages, and voltage between grid neutral and the negative terminal of PV, respectively. V AO , V BO , and V CO are the voltages between the outputs of inverter and the negative terminal of PV. From (1), the CMV of the proposed CCMVI (V CMV ) is expressed as From Fig. 1, the following mathematical equations are obtained: Substituting V AO , V BO , and V CO in (3) into (2), the CMV of the proposed CCMVI can be rewritten as follows: From Fig. 2, the following mathematical equations are obtained: The leakage current can be expressed as: where C PE defines parasitic capacitance between the ground and PV array. From (4)-(6), the voltage across the parasitic capacitor (V PE ) is derived by From (6), we can see that the leakage current depends on both the parasitic capacitance C PE and dV PE (t)/dt. Therefore, the leakage current can be effectively limited if the voltage across the parasitic capacitor C PE is constant. According to (7), the voltage across the parasitic capacitor C PE is dependent on the CMV.  Table 1 highlights the corresponding CMV and eight switching states of the proposed CCMVI. The operating principle of the proposed CCMVI topology is explained as follows.

B. OPERATING PRINCIPLE OF PROPOSED CCMVI
During state 0 [see Fig. 3(a)]: S a , S b, and S c are switched off while S d is switched on. Therefore, diodes D a , D b, and D d are blocked while diode D c conducts. Capacitors C a and C b are discharged while capacitor C c is charged. The capacitor C c voltage is the same as V g . The CMV of the proposed CCMVI during state 0 is zero. Capacitors C a and C c are discharged while capacitor C b is charged. Capacitor C b voltage is the same as V g . The corresponding CMV of the proposed CCMVI during this state is zero. Capacitors C b and C c are discharged while capacitor C a is charged. Capacitor C a voltage is the same as V g . The corresponding CMV of the proposed CCMVI during this state is zero.
During state 7 [see Fig. 3 (h)]: like even active states, S b and S c are also switched on while S a and S d are switched off. So, diodes D a , D b , and D c are blocked while diode D d conducts. Capacitors C b and C c are discharged while the capacitor C a is charged. Capacitor C a voltage is the same as V g . The corresponding CMV of the proposed CCMVI during this state is V PN /3.
From (8)- (11), the voltage gain of the proposed CCMVI topology is defined: From operating principles of the introduced CCMVI topology, we can see that the CMV is maintained as constant at zero without using state 7. Besides, the DC-link voltage of the introduced CCMVI is triple of that of the VSI for the same input voltage. Based on the above circuit analysis, we can see that the input current of the proposed converter circulates through three semiconductors during even active states while it circulates through four semiconductors during odd active states. So, conduction loss in the switched-capacitor network is high. As a result, it affects the efficiency of the proposed topology.

C. PWM CONTROL TECHNIQUE FOR PROPOSED CCMVI
In this section, the implementation of the proposed PWM control technique for CCMVI is illustrated. Fig. 4 indicates a block diagram of the PWM generation scheme for all ten switches of the proposed CCMVI topology.
As shown in Fig. 4, we can see that the proposed PWM control technique for CCMVI can be utilized using the scalar approach as follows: where three sinusoidal signals v a , v b , and v c are the original reference signals, M i is the modulation index, and ω defines the angular frequency of reference signals. v os is the offset signal and is obtained as: Three sinusoidal signals with a phase shift of 120 • among them are used to produce three desired three-phase modulation signals (v * a , v * b , and v * c ) based on (13). And then, These desired three-phase modulation signals are compared to the high-frequency carrier wave to generate three signals X, Y, Z. Then, the gating signal can be obtained from three signals X, Y, Z based on the mathematical operations in Table 2. Logic functions in the proposed PWM generation scheme are highlighted in Table 2. This guarantees that the CMV of the introduced CCMVI is maintained as constant at zero. Similar to the conventional VSI under discontinuous PWM strategy, the proposed CCMVI topology under the proposed PWM control technique has also the major features such as low switching losses, full modulation range, and low DC-link current ripple. The proposed CCMVI under the proposed PWM control technique has an additional benefit of zero variation in CMV. Table 3 presents the comparison of the component count, CMV, voltage linearity, voltage gain, and voltage stress across filter inductors between the proposed CCMVI topology and the other three-phase topologies. Compared to the conventional VSI, the introduced CCMVI topology uses four more switches, four more diodes, and three more capacitors as depicted in Table 3. According to Table 3, the voltage gain of the introduced CCMVI topology is the highest. The voltage gain of the introduced CCMVI topology is triple of that of the conventional VSI. As a result, the required input of the introduced CCMVI is lowest and one-third of that in the other topologies in [8], [10], [11] and [20]- [25] for the same DC-link voltage. When compared with SCVD topology in [28], the proposed CCMVI topology uses two more switches, two more diodes, and one more capacitor as shown in Table 3. The voltage gain of the proposed CCMVI topology is 1.5 times more than voltage gain of SCVD topology. Therefore, for the same input voltage, the output voltage of the CCMVI topology can be higher than output voltage of the SCVD topology. Compared to four-leg inverter topology in [20], the CCMVI topology uses two more switches, four more diodes, and two more capacitors. However, four-leg inverter topology uses one more inductor in comparison to CCMVI topology. Compared to voltage-clamping topology in [21], the CCMVI topology uses two more switches and two more diodes. Also, the CCMVI topology uses three capacitors like voltage-clamping topology. Compared to the ESI topology in [22], the CCMVI topology uses two less switches and four more diodes as highlighted in Table 3. Compared to H8 topology in [23] and modified H8 topology in [24], the proposed inverter uses three more capacitors, two more switches and four more diodes as shown in Table 3. Compared to the ZVR topology, the proposed inverter uses eight less diodes, one more capacitor and one more switch as highlighted in Table 3.

III. COMPARISON WITH OTHER THREE-PHASE INVERTER TOPOLOGIES
As highlighted in Table 3, we can see that the CCMVI topology operates with the full range of modulation index while the conventional VSI using NSPWM in [8] and RSPWM in [10] have limitations on the modulation index. H8 topology in [23], modified H8 topology in [24], and the ZVR topology in [25], also operates with the full range of modulation index as emphasized in Table 3.
The CMV of the introduced CCMVI is zero while that of the conventional VSI under different PWM schemes in [8]- [11] is 33% of DC-link voltage. This variation of the ESI topology in [22] and the ZVR topology in [25] is also zero. Meanwhile, it varies within 33% of DC-link voltage with voltage-clamping topology in [21], H8 topology in [23], and modified H8 topology in [24]. The variation in CMV of SCVD topology in [28] is also 33% of DC-link voltage with DPWM and 16% of DC-link voltage with NSPWM.
In the introduced CCMVI topology, voltage stress across filter inductors is the same as DC-link voltage while that in four-leg inverter topology in [20] is double of DC-link voltage. Like four-leg inverter topology in [20], voltage stress across filter inductor in the conventional VSI under different PWM schemes in [8]- [11] and SCVD topology under NSPWM in [28] is double of DC-link voltage.

IV. SIMULATION RESULTS
To confirm the performance and operating principle of the proposed CCMVI topology, the simulation model is established in PLECS simulation platform, and simulation results are given. The simulation parameters of the proposed CCMVI are depicted in Table 4. Fig. 5 shows a control system for the proposed CCMVI topology in grid-connected mode. As indicated in Fig. 5, a three-phase inductor of 10 mH/phase is considered between the inverter output and the grid. As indicated in Fig. 5, a combination of a predictive current control as discussed in [29], and the proposed PWM control scheme is used to inject currents into the grid. According to [29], the required output voltage at instant k can be predicted as: where i d (k) and i q (k) are actual inverter output current in daxis and q-axis; ν * d (k) and ν * q (k) are desired output voltages in d-axis and q-axis; ν gd (k) and ν gq (k) are grid voltage in d-axis and q-axis; i dref (k) and i qref (k) are reference output current in d-axis and q-axis; ω, L m , and T are grid angular frequency, the modeled inductance of the output filter and the PWM period, respectively. Fig. 6 illustrates the simulation waveforms of the proposed topology with an injected current of 6 A. It can be observed from Fig. 6(a) that the DC-link voltage of the introduced topology is triple of the input voltage. The DC-link voltage  of the introduced topology is obtained as 300 V from the input voltage of 100 V as highlighted in Fig. 6(a). The proposed topology under the proposed PWM control technique generates unipolar output line-to-line voltage as indicated in Fig. 6(a). As a result, voltage stress across the inductor filter is the same as the DC-link voltage. The grid voltages, grid currents, CMV across the parasitic capacitor, and the leakage current are demonstrated in Fig. 6(b). It can be observed from the simulation waveform, the proposed inverter injects sinusoidal currents of 6 A to the grid. The THD value of the grid currents is around 1%. It can be observed from the simulation waveform that CMV across the parasitic capacitor is around 0 V. The RMS value of the leakage current is only 0.5 mA. Figs. 6(c) and 6(d) show waveforms of voltage across additional switches and their expanded view. As shown in Figs. 6(d), the voltage across three switches S a , S b , and S c is 100 V while the voltage across switch S d is 200 V. Fig. 7 illustrates dynamic performance waveforms of introduced topology. As indicated in Fig. 7(a), at t = 0.2 s, the proposed inverter injects sinusoidal currents of 6 A to the grid. From Fig. 7(a), we can see that the CMV across the parasitic capacitor is around 0 V. The RMS value of the leakage current is around 0.5 mA. The harmonic spectrum analysis of the grid current and leakage current, in this case, is presented in Fig. 8(a). The THD value of the grid current is around 1%. Fig. 7(b) demonstrates dynamic performance waveforms of introduced topology with injected current changed from 6 A to 3 A. From Fig. 7(b), at t = 0.4 s, the injected sinusoidal  currents are stepped down from 6 A to 3 A. The RMS value of the leakage current is around 0.5 mA. The harmonic spectrum analysis of the grid current and leakage current, in this case, is shown in Fig. 8(b). The THD value of the grid current is around 1.1%.

V. EXPERIMENTAL RESULTS
To prove the efficacy of the introduced CCMVI topology, the laboratory-built prototype based on a DSP F280049C microcontroller is exhibited in Fig. 9, and its components are listed in Table 4. The RHRG3060 diodes and IPW60R040C7 MOSFETs have been used for the experiments. The equivalent series resistance of capacitors is 240 m . Due to the  As shown in Fig. 10 (a), the DC-link voltage of the proposed CCMVI topology is obtained as 289 V from the input voltage of 100 V. As given in Fig. 10 (a), the output lineto-line voltage of the proposed CCMVI under the proposed PWM control technique is unipolar in nature. As shown in Fig. 10 (b), the amplitude value of output currents is 2.    The voltage across three capacitors (C a , C b , and C c ) is also 97 V as highlighted in Fig. 11(c). Fig. 11(d) shows CMV of the proposed CCMVI topology. It can be observed from the waveform that the variation of common-mode voltage is about 3 V due to the effect of voltage ripple on capacitors. Fig. 12 highlights the losses distribution chart of the proposed topology. The total power loss of proposed topology is 50.5 W at the power of 900 W. From Fig. 12, we can see that the most losses come from conduction loss of the switches. The proposed topology uses four more additional switches, four more additional diodes, and three more capac-  itors than those of the conventional VSI. So, its efficiency is lower than that of the conventional VSI. However, the voltage across on additional switches (S a , S b , and S c ) of the proposed topology is only one-third of DC-link voltage, and the voltage across on additional switch Sd is two-thirds of DC-link voltage. As a result, power loss on extra switches is reduced. Fig. 13 highlights the measured efficiency of proposed CCMVI with various output power when V g = 100 V and output phase voltage of 150 V. As highlighted in Fig. 13, we can see that the maximum efficiency of the laboratory prototype is around 95.2 % at 610 W . The CEC Efficiency (η CEC ) is calculated according to the following [30]: η CEC = 0.04η 10% + 0.05η 20% + 0.12η 30% + 0.21η 50% + 0.53η 75% + 0.05η 100% (16) where η 10% , η 20%, η 30%, η 50%, η 75%, η 100% is the efficiency of proposed topology at 10%, 20%, 30%, 50%, 75%, and 100% of the rated power, respectively. The prototype of the proposed topology reached a California Energy Commission (CEC) weighted power stage efficiency of 94.6%.

VI. CONCLUSION
In this paper, the three-phase constant common-mode voltage inverter with triple voltage boost is proposed. The introduced topology can provide a remarkable DC-link voltage that is triple of the input voltage. Therefore, the introduced topology can be operated in both buck and boost modes. Besides, the PWM control technique for the introduced topology is also presented, which is easy to follow and implement in practice. In addition, modeling, analysis of the leakage current paths in the PV system have been described. With introduced PWM control technique, the CMV of the introduced inverter is maintained as constant at zero. Thus, by limiting the variation in CMV, the leakage current that that flows through the parasitic capacitance existing between the load ground and PV array ground can be effectively reduced. The introduced inverter generates unipolar output. Therefore, voltage stress across filter inductors is the same as the DC-link voltage, resulting in limited size and loss in the filter inductors. It is worth noting that the inrush current of the capacitors and high power conduction loss in the switched-capacitor network are the drawbacks of the introduced inverter. Operating principles, mathematical analysis, circuit analysis, and comparison of the proposed inverter with the other existing inverters are presented. The simulation and experimental results associated with the efficiency measurement of the built inverter prototype have been illustrated to prove the effectiveness and feasibility of the proposed topology.
TAN-TAI TRAN received the B.S. degree in electrical and electronic engineering technology and the M.S. degree in electronic engineering from the Ho Chi Minh City University of Technology and Education, Ho Chi Minh City, Vietnam, in 2012 and 2016, respectively, and the Ph.D. degree in electrical engineering from Chonnam National University, Gwangju, South Korea, in 2020. He is currently with the Department of Electrical Engineering, Chonnam National University. His current research interests include renewable energy systems, automation systems, dc-dc converters, and dc-ac inverters.