Proposal and Analysis of a Novel Class of PUFs Based on Galois Ring Oscillators

In this article, the possibility of using Galois ring oscillators to construct physically unclonable functions (PUFs) has been studied. The idea is to use novel PUF architectures, similar as the ring oscillator PUFs that, instead of comparing frequencies, compare the statistical bias of pairs of oscillators implemented in different locations. To study the viability of these systems, three different Galois oscillators have been implemented in several locations in several FPGAs and we have studied the main properties of their bias: repeatability, variability with the location, variability with the FPGA and spatial autocorrelation. Based on this study, we have determined that the bias of these oscillators meet the requirements that are needed to be used to construct a PUF. Finally, a PUF based on comparing the bias of neighboring 7-LUT Galois ring oscillators have been implemented and analyzed. The experimental results show that this PUF generates uniform responses that are highly reproducible and unique, making this PUF suitable for being used in identification applications.


I. INTRODUCTION
In the last years, physically unclonable functions (PUFs) have gained a great interest in both the academic and in the industry communities and are now considered an essential building block in modern secure systems [1]- [3]. By profiting the physical variations that occur during the manufacturing process of silicon chips, PUFs can generate an embedded secret that is easy to verify but difficult to predict. This way, these primitives can be used in some important applications such as identification [4]- [6] and key generation/ storage [7], [8].
Depending on the method used for amplifying the manufacturing variations, PUFs can use several techniques such as memory metastability [9]- [11], matched delay line arbiter [12], differential-NAND [13] or ring oscillators (RO-PUFs) [7], [14]. However, in case of implementing a PUF in an FPGA, some complications can arise. While in an ASIC design, a designer can exploit the layout design techniques The associate editor coordinating the review of this manuscript and approving it for publication was Yong Chen . or work at a gate level, in an FPGA, a designer only has access to some bigger design blocks such as LUTs, flip-flops, multipliers or block RAM. Therefore, not all the proposed PUFs can be implemented on FPGAs.
Among the FPGA-based PUFs, RO-PUFs are often preferred [15], [16]. In these PUFs, typically the differences between the oscillator frequencies of identical ring oscillators are used to generate the PUF response. Unfortunately, the frequencies of the oscillators implemented in the FPGA present a clear systematic frequency variation when moved over the FPGA. To mitigate this effect, often, each oscillator is only compared with nearby oscillators [15].
In this article, we propose and study the possibility of using a class of digital nonlinear oscillators proposed by Golić in [17] to construct physically unclonable functions. We prove that, in a similar way as ring oscillators, Golić's oscillators exhibit a certain variation depending on its location that can be exploited for PUF applications. Furthermore, while the frequency variation of ring oscillators has a significant systematic component, we prove that the behavior of  these oscillators do not have a noticeable systematic component along the location in the FPGA.
The paper is organized as follows: Section II presents the basic structure of a RO-PUF, an overview of the Fibonacci and Galois ring oscillators and, finally, proposes a method to use the variability presented by these systems to construct a PUF; Section III studies experimentally the bias of three different Galois ring oscillators to prove the capability of these systems to be used to construct a PUF; in Section IV, a PUF consisting of an array of 7-LUT GAROs is implemented and analyzed. Finally, conclusions are drawn in Section V.

II. BASIC CONCEPTS A. ARCHITECTURE OF A RO-PUF
A ring oscillator consists of an odd number of inverters connected in a loop. Its output oscillates at a frequency that, in the ideal model, only depends on the number of inverters. In practice, however, due to random variations introduced during the manufacturing process, the oscillation frequency of each oscillator is not exactly the same. Typically, a RO-PUF compares the frequencies of pairs of identical oscillators to produce the output. A common scheme is the one shown in Fig 2, proposed in [7]. As it can be seen, the PUF contains an array of k identical ring oscillators, a couple of multiplexers used to select the oscillators and a couple of frequency counters to measure the frequencies of each oscillator. Typically, several pairs of oscillators are compared, producing several response bits. There are RO-PUFs with several challenges, where each challenge determines the pairs of oscillators to compare but, often, these PUFs have a single challenge, i.e., always the same pairs of oscillators are compared.
By considering all possible combinations, a total of pairs can be formed to generate an output bit. However, from all these possible comparisons, not all of them produce independent outputs. For example, if oscillator RO 1 is faster than oscillator RO 2 and oscillator RO 2 is faster than oscillator RO 3 , then it is clear that oscillator RO 1 is faster than oscillator RO 3 . The number of independent comparisons that can be made is theoretically limited by the number of possible ways of ordering the oscillators, which is k! Therefore, the maximum possible independent output bits is log 2 k! However, in practice, the exact list of independent comparisons to achieve this is difficult to obtain and is device-specific. A simple method of guaranteeing that all the output bits are independent consist of comparing fixed pairs of oscillators, using each oscillator only once, therefore, producing k 2 output bits. In order to further improve the reproducibility and uniqueness of the PUF, another approach consist of dividing the array of oscillators in groups of d oscillators and consider only the pair with the largest difference in frequency. This way, the quality of the PUF is enhanced at a cost of reducing the number of response bits by a factor of d [7]. Finally, a common approach consist of comparing neighboring oscillators, producing a response of k − 1 bits [14]. With this approach, although the output bits are not completely independent, the entropy per output bit is very high and the throughput is almost twice as much as with the k 2 strategy. As it is clear, there are many different RO-PUFs architectures that can be implemented and each architecture prioritizes some aspects such as: number of response bits, independence of the output bits, reproducibility and uniqueness of the PUF, big number of challenges-response pairs, etc. Unfortunately, when implemented in an FPGA, the frequency of the ring oscillators presents a clear systematic component (i.e., ring oscillators implemented in some locations are usually faster than ring oscillators implemented in other locations). As a consequence, some architectures that could theoretically be good for a certain application behave worse in a real implementation. Therefore, in practice, only a few architectures are usually used. Typically, in these architectures, only nearby oscillators are compared to reduce the systematic component.

B. FIBONACCI AND GALOIS RING OSCILLATORS
In 2006, J D. Golić proposed a new method for true random number generation using new structures called Fibonacci ring oscillators (FIRO) and Galois ring oscillators (GARO) [17]. These structures where based on the structure of ring oscillators but, instead of using a single circular feedback, they used a more complex feedback incorporating XOR gates in an analogous way to the Fibonacci and Galois configurations of an LFSR (Fig. 3). The idea behind this proposal was to  combine the pseudo-randomness properties of the LFSRs with the true randomness properties of ring oscillators due to oscillation jitter.
For both FIRO and GARO, the feedback connections are specified with coefficients f i and, therefore, the configuration can be unequivocally defined using a binary polynomial Fig. 3 is closed while, if f i = 0, the corresponding switch is open. Note that these switches are only shown for illustration purposes and are not actually implemented. In an actual implementation, if f i = 1, there is an XOR and a feedback connection implemented in the ith position while, if f i = 0, the ith feedback connection and XOR gate are not implemented. An advantage of using GAROs with respect to FIROs is that, given a feedback polynomial of order n, it is possible to easily implement it in an FPGA using exactly n LUTs. If f i = 1, the implemented function in the ith LUT is an XNOR operation while, if f i = 0, the implemented function in the ith LUT is a NOT operation. According to Xilinx specifications [18], the LUT propagation delay does not depend on the function implemented so the total timedelay will only depend on the total number of LUTs (which is determined by the order of the primitive polynomial), making the study of these systems easier. For this reason, in this work, only GARO topologies have been studied.

C. ISSUES OF FIRO AND GARO TRNGs
Both FIRO and GARO TRNGs have been widely studied and implemented in both FPGAs [19] and ASIC devices [20]. Unfortunately, these kind of structures have not yet proven to be robust since there is no theory that explains how to choose a feedback polynomial for GARO or FIRO that guarantees that the system behaves properly, generating a minimum amount of entropy [21], [22].
Furthermore, even using the same feedback polynomial, it has been recently proven that, depending on the location FIGURE 5. Autocorrelations of sequences obtained from the same GARO polynomial implemented in four different locations. Red sequence presents some statistical dependence and some autocorrelation, blue sequence presents no bias but a high statistical dependence, yellow sequence presents some bias and no statistical dependence and green sequence does not present bias or statistical dependence.
within the FPGA where the system is implemented, the behavior of the system can change drastically, sometimes resulting in poor random sequences [23], [24].
As an example, let's consider a TRNG consisting of a 7-LUT GARO with the feedback polynomial f (x) = 1+x 2 + x 6 + x 7 that obtains the random sequences by sampling the signal with a flip-flop (Fig. 4). By comparing the sequences obtained by the same system implemented at several locations within the FPGA, it can be seen that they clearly present different statistical properties. A possible measurement that can be used to illustrate this fact is the normalized autocorrelations, R j , defined as: a i a i+j where N is the total number of bits of the sequence and a i is the ith element of the sequence (note that the coefficient R 0 represents the bias of the sequence). Fig. 5 represents the normalized autocorrelations, R j , of four sequences, each of them generated by the same system sampled at 10 MHz but implemented at different locations in the same FPGA. As it can be seen, all of the graphs present clearly distinguishable patterns.

D. CONSTRUCTION OF A GARO-PUF
As we have shown, GAROs implemented in different locations present some clearly noticeable statistical differences. The main scope of this work is to study the possibility of using these statistical differences to construct a PUF. In particular, due to its simplicity, we will study the variation of the bias (R 0 ) depending on the location. As long as the bias distribution presents some properties such as being repeatable within the same location in the same FPGA but variable when changing the location or the FPGA, it could be possible to use an analogous structure as the one used in the RO-PUF ( Fig. 1) that compares the value of the bias of GAROs instead of the frequencies of ring oscillators.
In the following section, we will prove experimentally that the biases of several GAROs meet all the required properties and, therefore, it can be possible to construct PUFs based on these systems. Finally, as a proof of concept, a particular GARO-PUF that uses an analogous structure as the RO-PUF presented in [14] has been implemented and analyzed. All the systems have been implemented in a Pynq Z2 board that includes a Zynq-7000 series ARM/FPGA System on Chip.

III. PROPERTIES OF THE BIAS OF SEVERAL OSCILLATORS A. STUDY OF THE REPRODUCIBILITY OF A POSSIBLE GARO-PUF
In order to construct a PUF based on comparing the bias of pairs of oscillators (i.e., pairs of identical oscillators implemented on different locations), the biases of the oscillators must meet some properties, in a similar way as the frequencies of the ring oscillators in a RO-PUF. In particular, if we want this kind of PUFs to be reproducible, the bias of the oscillators must meet these two properties: -First, if the measurement of the bias of an oscillator in a given location and a given FPGA is repeated several times, the results should always be the same or very similar. In this article, this property will be called ''repeatability''. -Second, the measured bias should change when changing the location within the FPGA. In this article, we will call this property ''variability''. The changes in the bias that occur when changing the location (i.e., variability) should be clearly larger than the changes that might occur when repeating the measurement in the same location. This way, the results of the comparisons between pairs of oscillators will most of the time be the same and, therefore, an implemented PUF based on comparing pair of oscillators will be reproducible.
To study these properties, the same GARO has been implemented in 101 different locations in the same FPGA. Each GARO has been sampled with a flip-flop and, if the sampled bit is ''1'', a counter has been increased. This way, by observing the value of the counter, it is possible to know the behavior of the bias as long as the following conditions are met: first, the sampling frequency must be much lower than the frequency of the oscillations to avoid that the measurements occur during the same high or low state; second, a high number of samples must be taken so that the final value of the counter is a good estimation of the bias. The same process has been repeated 100 times to measure the repeatability.
In order to determine a proper sampling frequency, we first did a small test consisting of measuring the bias at different sampling frequencies (from 100 MHz to 10 kHz) for several systems. We observed that a sampling frequency of f s = 100 kHz was good enough for measuring the bias precisely (lower sampling frequencies did not improve the precision of the measurements while, in some systems, higher sampling frequencies affected the result of the bias). Regarding the number of samples, we determined that 100,000 samples was a good choice to have a good estimation of the bias. With 100,000 samples, assuming an ideal unbiased sequence the expected value of the sum would be 50, 000±158 (around ∼ 0.3% error). If, instead, we had used 10,000 samples, To evaluate the repeatability and the variability, the normalized standard deviations σ j rep , σ i var have been used, defined as: In this experiment, the number of repetitions is N = 100 and the number of different locations is N = 101. Fig. 6 shows the distribution of σ j rep and σ i var in an experiment using an array of 5-LUT GAROs at room temperature (∼ 25 • C). As it can be seen, the values of σ j rep are much smaller than the values of σ i var , which indicates that a PUF based on comparing the bias of pairs of oscillators would be reproducible. It must be noticed that all these measurements have been obtained in the same experiment (using the same synthesized code) so the fact that the values of σ j rep are not cero means that the system is sensitive to changes in the operation conditions that can occur between measurements such as slightly different temperatures or supply voltages. The spread of the histogram of σ j rep indicates that oscillators implemented in some locations are more sensitive to these changes than oscillators implemented in other locations.
The same experiment has been repeated for three different GAROs (a 5-LUT GARO, a 7-LUT GARO and a 17-LUT GARO) at different temperatures. According to [17], a GARO does not present a fixed point if an only if f (1) = 1 and n is odd. In this work, we have only used feedback polynomials that satisfy this condition to avoid any possible fixed points. Furthermore, for comparison purposes, an analogous structure that measures 100 times the frequencies of a 5-LUT ring oscillator implemented in the same 101 locations has been implemented. In order to have a figure of merit of the repeatability and variability, the average values var have been obtained for each temperature. Finally, we have defined the quality ratio Q =σ var /σ rep , which can be a good estimator of how reproducible a PUF would be. The experimental results are summarized in Table 1.
As it can be seen, although the temperature can affect the repeatability and the variability of the bias of a GARO, the changes are quite small in all three cases (5-LUT, 7-LUT and 17-LUT) and, from the collected data, it is not clear if increasing the temperature improves or deteriorates the reproducibility of the PUF. In a similar way, the 5-LUT ring oscillator does not present a high variability on the temperature, as long as the temperature is not very high. However, when operating at 80 • C, the repeatability is much higher and, therefore, the quality ratio Q is also very high.
By comparing the average values of the quality ratios, Q = 1 6 6 i=1 Q(T i ), of the different oscillators, we can see that both the 7-LUT GARO, the 17-LUT GARO and the 5-LUT RO present similar valuesQ ≈ 40 while the 5-LUT GARO presents a lower value (Q≈ 20). However, it must be noticed that, in the case of the ring oscillator, the high value of Q obtained at 80 • C affects greatly the value ofQ. By considering lower temperatures, the value ofQ would be around 5.0, which is clearly lower than the values obtained by the GAROs. Therefore, it can be concluded that, as long as the temperatures are not very high, a GARO-PUF would probably present a higher reproducibility than a RO-PUF.

B. STUDY OF THE UNIQUENESS OF A POSSIBLE GARO-PUF
In order to study the uniqueness of a GARO-PUF, the same experiment as before has been repeated on 20 different FPGAs at room temperature. First, for each FPGA and each jth location, the mean value of the bias, µ j k has been where A j i (k) is the ith measurement of the oscillator that is located in the jth location in the kth FPGA. Then, we have obtained the normalized standard deviations of the mean values measured on different FPGAs (σ j FPGA ) which indicate the variability of the bias in a certain location when changing the FPGA: In a similar manner as in the previous subsection, these deviations should be big compared to the deviations that occur when repeating the same measurement in the same location and same FPGA (σ    Table 2. For comparison, the values of a 5-LUT ring oscillator have also been included. From these values, it seems that the 5-LUT GARO-PUF would present the lowest uniqueness and the 7-LUT and 17-LUT GARO-PUFs would both present a slightly higher uniqueness. However, the ring oscillator presents the highest ratio (Q ≈ 40) which indicates that, probably, a RO-PUF would outperform a GARO-PUF in terms of uniqueness. Nevertheless, there could be other GAROs with other feedback polynomials that might exhibit a higher uniqueness. Future research works could focus on finding new feedback polynomials that have higher uniqueness while maintaining a high reproducibility.

C. STUDY OF THE SYSTEMATIC COMPONENTS IN THE BIAS
As explained before, one of the main issues of the ring oscillator PUF is that the frequencies of the ring oscillators present a high systematic component, i.e., ring oscillators implemented in some areas of the FPGA are usually faster than oscillators implemented in other regions. To visualize this fact, a color map of the average frequencies of a 5-LUT ring oscillator implemented on 101 different locations is shown in Fig. 8a. Each rectangle represents a ring oscillator and its coordinates correspond approximately to their physical coordinates within the FPGA (no oscillators were implemented in the top right corner of the FPGA). The color of each rectangle represents its frequency (darker color corresponds to higher frequency).
By looking at this map, there are some correlations that can be easily detected. For example, oscillators implemented in the right tend to have higher frequencies than oscillators implemented on left of the FPGA. On the other hand, the bottom row follows a dark-light-dark-light. . . pattern.
The same map has been obtained with the bias of 5-LUT GAROs implemented in the exact same locations (Fig. 8b). As seen in this Figure, no patterns can be easily appreciated indicating that the spatial autocorrelation of the bias of these oscillators is much lower than the spatial autocorrelation of the frequencies of ring oscillators. Similar figures have been obtained for the 7-LUT GARO and the 17-LUT GARO.  Therefore, GAROs seem to present a great advantage with respect to ring oscillators in that sense. While most of the RO-PUF constructions need to compare only nearby oscillators to mitigate the spatial correlations, GARO-PUFs would not have this restriction and, therefore, could offer a much bigger challenge-response set.

IV. IMPLEMENTATION OF A GARO-PUF
Finally, as proof of concept, a GARO-PUF has been implemented and tested. This PUF contains an array of 101 7-LUT GAROs and a 100-bit response is obtained by comparing the bias of neighboring oscillators in an analogous manner as the one presented in [14]. The measurement scheme adapted in this article is shown in Fig. 9. As in the previous section examples, to obtain the bias of each oscillator, 100,000 samples are collected with a sampling frequency of 100 kHz. This way, by measuring each oscillator in parallel a 100-bit response is obtained per second. This implementation, however, requires to implement a counter for each oscillator and, therefore, uses a lot of area. If, instead, the bias of each oscillator is measured sequentially, a single counter can be used for all the measurements. This way, the implementation area is greatly reduced at a cost of decreasing the throughput. Both implementations with parallel measurement and sequential measurement have been made. The implementation resources are shown in Table 3.
Since the architecture of this PUF is almost identical to the architecture of a RO-PUF, the implementation resources in both cases are very similar, as long as the same measurement strategy (sequential or parallel) is used. Regarding the throughput, in both GARO-PUFs and RO-PUFs it can be increased or decreased by changing the time spent to measure the bias/frequency. However, decreasing too much the time spent to measure the bias/frequency would worsen the quality of the PUF. In all comparisons shown in this article, a similar measuring time has been used for GAROs and ROs to have fair comparisons. We have chosen a quite high measuring time to measure the bias/frequencies quite precisely so that in both cases we are approaching to a best-case scenario. Lower measuring times would decrease the precision of the measurements, especially in the of the GAROs and, therefore, worsen their reproducibility.
Once implemented, this PUF has been analyzed in terms of reproducibility, uniqueness, uniformity and identifiability.

A. REPRODUCIBILITY
First, the reproducibility of the implemented PUF has been measured. For this purpose, the 100-bit response of the PUF has been measured 100 times and, for each possible pair of measurements, the Hamming Distance, HD, has been obtained. Given two m-bits output words, x = (x 1 , x 2 , . . .x m ) and y = (y 1 ,y 2 , . . .y m ), their hamming distance is defined as: where, in this case, m = 100. The distribution of the Intra-chip Hamming Distances (Intra-HDs) of the GARO-PUF measured at room temperature has been plotted in Fig. 10a. As it can be seen, all of the hamming distances are close to 0, indicating that the reproducibility is very high. The average value is 1.11% with a minimum value of 0 and a maximum value of 5%. For comparison, in the case of the ring oscillator we obtain an average value of 1.98% with also a minimum value of 0% and a maximum value of 5% (Fig. 10b). Furthermore, the histogram of the ring oscillator presents a larger dispersion.
Furthermore, the Intra-chip Hamming Distances have been measured at different temperatures. Its values are plotted in Fig. 11. As it can be seen, the average Intra-HD does  not change greatly with the temperature. If we compare the values with the ones obtained by the RO-PUF, we can see that for lower temperatures the GARO-PUF is more reproducible than the RO-PUF while, for very high temperatures, the RO-PUF is more reproducible. These results, however, could depend on many factors such the FPGA or the oscillators implemented so it is not possible to extrapolate these results to other cases. Another thing that must be pointed out is that, by repeating this experiment, the values obtained in Fig. 11 are not repeatable. This is likely caused by the fact that the internal temperatures and voltages are not exactly the same in each measurement. However, the tendency commented before (i.e., GARO-PUF presents lower Intra-HDs for  low temperatures and RO-PUF presents lower Intra-HDs for high temperatures) prevails.
Finally, we have measured Intra-chip Hamming Distances at different FPGA core voltages. The Pynq Z2 board has a TPS65400 Power Management Unit (PMU) that creates the required 3.3 V, 1.8 V, 1.5 V and 1.0 V supplies needed for the FPGA from the main power input [25]. In particular, the 1.0 V signal used for the FPGA core supply, V CCINT , depends on a reference voltage, V REF , that can be changed in 10 mV steps (which produces changes of around 13 mV in V CCINT ) through an I2C command [26]. This way by using a microcontroller we have managed to measure the interdistances at different voltages at a ±10% range. The results are shown in Fig. 12. We can see that, in both the RO-PUF and in the GARO-PUF, the average Intra-HD does not change greatly with the supply voltage. In fact, these changes could be caused by the fact that the internal temperature was not exactly the same in all measurements.

B. UNIQUENESS
To measure the uniqueness of the PUF, it has been implemented on 20 different FPGAs and we have obtained the most common response for each case. Then, the Inter-chip Hamming Distances have been obtained as shown in Fig. 13.
As it can be seen, although the Inter-HDs are quite larger than the Intra-HDs, their values are far from the ideal 50%. For comparison, the average Inter-HD is 39.1% while, for  the ring oscillator, the average value is 47.2%. It must be noticed that the measured value is not very precise since we do not have enough statistical data (only 20 FPGAs have been used). However, although the actual average value could be higher, it seems very unlikely that by increasing the number of FPGAs, the average value will approach too much to 50%.
The fact that the average Inter-HD deviates from the 50% value could be caused by two non-idealities. First, it could be caused by non-uniform distributions in the PUF responses (i.e., responses tend to have more 1's than 0's or vice versa). Second, it could be caused by bit-aliasing (i.e., most of the FPGAs produce the same bit in some positions).
To check if the output responses are uniform, Fig. 14 shows the Hamming Weights (percentage of ones), HW , of the most common response in each FPGA. As it can be seen, all Hamming Weights are close to 50%, which indicates that the responses are uniform so it cannot be the reason why the average Inter-chip HD is low.
Regarding the bit-aliasing, for each response bit position (from 1 to 100), the average value of the output bit across the 20 FPGAs has been obtained (Fig. 15).
We can see that, although the average value is 0.502, there are many spikes, i.e., some response bits are almost always 0 or almost always 1 in all FPGAs. Therefore, this explains why the Inter-chip HDs are smaller than the ideal value.
A possible reason for the bit-aliasing could be that some locations (the ones that almost always produce a 0 or a 1 output bit) could be physically placed near other FPGA elements (the input/output ports, the power supply, the implemented counters, . . . ) and some of those elements could affect the behavior of nearby oscillators in a similar way. Another possible reason could be that, during the manufacturing process, some areas of the FPGA could present lower variations than other areas. Finally, in some cases, the particular routing of a certain oscillator (which we not fully control) could determine its behavior. Since the exact same routing for each location is used when repeating the measurements in different FPGAs (the same.bit file is used to program each FPGA), the oscillators placed in some locations could have a particular routing that determines their behavior quite deterministically.

C. IDENTIFIABILITY
Since, the PUF presents a fuzzy behavior, in order to use it for identification applications, a threshold t must be set. Then, two responses x, y, will be considered to come from the same FPGA if HD (x, y) < t. Otherwise the two responses will be considered to come from a different FPGA [27]. With all the responses obtained experimentally, it can be noticed that all of the Intra-HDs (Fig. 10) are smaller than all the Inter-HDs (Fig. 13). Therefore, by choosing any threshold such as max {Intra-HD}< t < min{Inter-HD} all the responses are perfectly identifiable.
However, by increasing the number of measurements, new Hamming Distances will be obtained. To estimate the probability of obtaining different Hamming Distances, both the Intra-HDs and the Inter-HDs have been adjusted to binomial functions (Fig. 16). From this adjustment, we have calculated that the Equal Error Threshold t EER , i.e., the threshold for which the False Acceptance Rate (FAR) and False Rejection Rate (FRR) are closest is: t EER = 13. With this threshold, we obtain the values of FAR = 1.81 × 10 −9 and FRR = 1.61 × 10 −9 . As it can be seen, both errors are negligible and, therefore, this PUF is highly identifiable.

V. CONCLUSION
In this article, we have proven the suitability of using the GAROs proposed in [17] to construct a PUF. In particular, by analyzing three different oscillators, we have shown that their bias change depending on their location as well as the FPGA in a similar way as the frequencies of a ring oscillator.
As a demonstration, a 7-LUT GARO-PUF have been implemented and analyzed. Its reproducibility has been high and, although the uniqueness is not ideal, the identifiability is very high. Nevertheless, it must be noticed that, by measuring the bias with more precision (decreasing the sampling frequency and increasing the number of counts), both the reproducibility and uniqueness would improve.
From the experimental results obtained in this work, GARO-PUFs seem to be at least comparable to RO-PUFs. Their reproducibility seems to be higher and their uniqueness smaller. Furthermore, it seems that the distribution of the bias of these systems does not present as much spatial autocorrelation within the FPGA compared to the frequencies of the ring oscillator. This opens the possibility of constructing PUFs with a wider set of challenge-response sets since it is not required to compare only nearby oscillators as in the case of the RO-PUFs. This would be a great improvement since it would be possible to design PUFs with better performance and more robust to modeling attacks.
This work opens a very interesting line of research in the design of robust PUFs for FPGAs. Other structures such as other GAROs, FIROs or other Digital Nonlinear Oscillators such as the ones presented in [23] could be studied. It is likely that other oscillators would offer better results than the ones shown in this article. Furthermore, other strategies to distinguish between oscillators (e.g., measuring the other normalized autocorrelations, R j , or the Shannon entropy instead of measuring the bias) could be the used. However, this would require a more complex measuring system.