Extended Off-Time Control for CRM Boost Converter Based on Piecewise Equivalent Capacitance Model

Valley-switching (VS) and zero-voltage switching (ZVS) improves overall efficiency in critical conduction mode (CRM) boost converters. To achieve VS/ZVS, off-time of the main switch is often extended to match the resonance period by circuit inductor and parasitic capacitors of switching components. In this article, a piecewise equivalent model for parasitic capacitors is proposed to derive analytical solutions of the resonant process, by which the numerical solutions of VS/ZVS time is calculated. To precisely achieve VS/ZVS in a boost converter, corresponding extended off-time based on the numerical solutions is implemented with an extended off-time (EOT) controller. The EOT controller makes the inductor volt-second unbalance in continuous conduction mode (CCM) operation during one switching cycle, leading to the convergence to CRM operation. The analytical and experimental results correct the results derived by conventional equivalent model for parasitic capacitors, which leads to deviated VS/ZVS boundary and wrongly calculated off-time. The proposed model and controller are verified in a non-synchronous CRM boost converter based on GaN high electron mobility transistor (HEMT) and SiC diode. With the derived extended off-time, a peak efficiency of 99.15% is achieved at output power level of 200W.


I. INTRODUCTION
Converters under critical conduction mode (CRM) operation, which have potentials to degrade system order and achieve high efficiency, are widely used in low to medium power conditions, such as LED driver, power factor correction and on-board charger, [1]- [4]. To improve overall efficiency in non-synchronous boost converters operating in CRM, two sources of power loss are always considered: conduction loss and switching loss [5], [6]. With a certain power level and modulation strategy, conduction loss can be reduced by selecting devices with lower on-resistance or smaller voltage drop. Comparatively, reduction of The associate editor coordinating the review of this manuscript and approving it for publication was Jenny Mahoney. switching loss requires corresponding control strategy or auxiliary circuit to minimize the voltage across switch at switching-on moment [7], [8]. Therefore, in addition to selecting components with lower on-resistance, valley switching (VS) and zero-voltage switching (ZVS) are vital approaches to improve overall efficiency for CRM boost converters.
To achieve VS/ZVS in non-synchronous boost converters, an extended off-time is often regulated delicately, which starts from zero-crossing point of inductor current and ends at the rising edge of switching-on signal. In this situation, the extended off-time should match the resonant time by circuit inductor and parasitic capacitors of switching components, which usually consist of diode junction capacitor C j and output capacitor C oss of the main switch. As shown in Fig. 1, VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ FIGURE 1. Curves of (a) C oss and (b) C j with respect to junction voltage.
both the C j and C oss curves are strongly nonlinear with voltage levels [9], [10]. For silicon-based semiconductors, these voltage-varying curves are greatly affected by other circuit states, such as temperature, switching frequency, etc. By contrast, the third-generation semiconductors, such as GaN High Electron Mobility Transistor (HEMT) and SiC diode, are inherently environment-insensitive due to their wide bandgap characteristics. In [11], the characteristics of C oss of GaN HEMT is tested by double-pulse test (DPT) circuit. Firstly, it is proved that the E oss loss should be only relevant to the capacitor charging energy. In other words, the loss is a function of voltage v ds and C oss . Then, the DPT at different circuit state shows that E oss is independent on both the junction temperature and switching speed. In [12], the curve of C j with respect to voltage level is fully investigated. For SiC based diode, frequency variation has negligible influences on this curve while the curve by Si based diode is greatly deviated from the nominal one. In [13]- [15], experiments verify that energy curves of C j with respect to voltage level is irrelevant to temperature in the industrial application temperature range. From the literatures above, the voltage-varying curves of C j and C oss are insensitive to circuit states, such as temperature, switching frequency, etc. The environment-insensitive feature provides reasonable foundation to make use of parasitic capacitors in practice. However, the nonlinear relationship with junction voltage makes it complex to intuitively understand the resonance behaviour of these parasitic capacitors. To simplify the resonant process, parasitic capacitors are considered as a constant value in a boost circuit based on GaN HEMT [16]- [18]. In order to evaluate a proper VS/ZVS time, it is necessary to discuss the resonant process with nonlinear capacitors in detail. Therefore, authors in [19] divide the C oss into two integrals based on voltage level to refine the resonant process. In [20], although different intervals are considered to calculate the approximate resonant time, it does not give clear explanations of the resonance characteristics. In the mentioned literatures, a theoretical and practical model has not been well-designed to derive the analytical equations of the resonant process, which fails to acquire a proper VS/ZVS time.
In order to precisely achieve VS/ZVS for a CRM converter, an analog zero current detection (ZCD) circuit is often used to locate the zero-crossing point of inductor current, which is the starting point of the resonant process. However, the resonant process only lasts several hundred nanoseconds, which means that the delay introduced by the ZCD circuit should be carefully considered. For examples, sampling resistor is used in ZCD circuit, where high speed comparator is required [21]. To ensure a controllable VS/ZVS time, delay of each components is discussed in detail [22]. In [23], [24], the inductor current zero-crossing point is detected by secondary windings of the inductor. This method is easy to understand, but components in ZCD detection module may induce significant delay to the turn-on edge of main switch [25]. Furthermore, the detecting delay varies with input voltage, which make it complex to accurately locate the current zero-crossing point. From the aforementioned methods, analog ZCD module is indispensable for the implementation of CRM operation. However, an accurate ZCD module with matched speed could also increase the overall design complexity, cost and size, especially in high frequency applications.
In this article, a piecewise equivalent capacitance model for CRM boost converter is proposed to quantify the resonant process, based on which the optimal VS/ZVS time is derived. To simplify the non-linearity problem by C oss and C j , the capacitor value is first divided into several intervals with respect to suitable voltage levels, where the capacitor value in each interval varies within a small range. Then, the equivalent capacitor value for each interval is calculated by a charge-based equivalent method. With capacitor values in each interval and the interval boundaries, analytical solutions of the resonant process are derived, which is the foundation to calculate the optimal VS/ZVS time. Comparatively, analytical solutions by the conventional constant capacitance model fail to match the resonant process in practice. To achieve VS/ZVS in a boost converter, the optimal VS/ZVS time is implemented in the extended off-time by an extended off-time (EOT) controller. The EOT controller makes the inductor volt-second unbalance in continuous conduction mode (CCM) operation during one switching cycle, leading to the convergence to CRM operation. Since it does not require ZCD module or current sensing, it is a sensorless approach. The derived VS/ZVS time and the proposed controller are verified in a boost prototype based on GaN HEMT and SiC diode.
This article is organized as follows: Section II discusses the conventional constant capacitance model for parasitic capacitors in non-synchronous CRM boost converter, and introduce the estimation method of equivalent capacitance under different conditions. In Section III, optimal VS/ZVS time is calculated according to the piecewise equivalent capacitance model. Furthermore, the VS/ZVS time is applied in the extended off-time with the proposed EOT controller. In Section IV, the derived VS/ZVS time and the proposed controller are verified by experimental results. Finally, a brief conclusion is given in Section V.

II. VS/ZVS REALIZATION IN NON-SYCHRONOUS CRM BOOST CONVERTER WITH CONSTANT CAPACITANCE MODEL FOR PARASITIC CAPACITORS
VS/ZVS is often an indispensable approach to reduce the switching loss. For a non-synchronous CRM boost converter, to derive a proper VS/ZVS time, resonant process by circuit inductor and parasitic capacitors of switching components is often investigated. In the followings, the conventional constant capacitance model for the parasitic capacitors is introduced. This approach simplifies the analytical solutions of the resonant process, however, it ignores nonlinearity of the parasitic capacitors, where deviated VS/ZVS time is induced.

A. RESONANT PROCESS WITH CONSTANT CAPACITANCE MODEL
Basic topology of a non-synchronous boost circuit based on GaN HEMT and SiC diode is given in Fig. 2(a). Since the values of input and output capacitors in the circuit are much larger than that of the parasitic capacitors, the equivalent resonant circuit for boost circuit during VS/ZVS time is simplified to the topology in Fig. 2(b).
The current and voltage of the boost converter when VS and ZVS are achieved is given in Fig. 3(a) and Fig. 3

(b).
For an entire switching cycle, gate voltage v gs keeps high from t 0 to t 1 , where the inductor current rises from zero at t 0 and falls to zero at t 2 . Finally, the circuit inductor resonates with parasitic capacitors from t 2 to t 3 .
For VS situation shown in Fig. 3(a), v ds during resonance is always higher than zero. The gate voltage v gs turns high at the valley point of v ds , where the inductor current returns zero. For ZVS situation shown in Fig. 3(b), the resonant process ends at t 3 , which is the zero-crossing point of v ds .
To derive the optimal VS/ZVS time, the resonant process should be fully investigated. Although the behaviors of the current and voltage are different for these two situations, their equivalent resonant topology remains the same. According to the equivalent circuit shown in Fig. 2 equations for drain-source voltage v ds and inductor current i L during the resonance are described as: To simplify the analysis of resonant duration, the two voltage-varying parasitic capacitors are equivalent to constant values based on the conventional constant capacitance method. Since voltage v ds across the MOSFET satisfies v ds (t 2 ) = v o and dv ds (t 2 )/dt = 0, equations for v ds and the inductor current i L are derived as: where Z r = L/(C oss + C j ), ω r = 1/ L(C oss + C j ), and t 2 is the beginning of the resonant process, as shown in Fig. 3(a) and Fig. 3(b). Thus, the capacitors during resonant process can be combined as one capacitor, which is C eq = C oss + C j .

B. SOLUTIONS FOR VS/ZVS TIME
With the resonant process equations (3) and (4), solutions for VS/ZVS time can be calculated. For VS situation in Fig. 3(a), it is indicated by (4) that v ds is positive definite when 2v in > v o . Therefore, VS can be achieved in half the resonant period, which is t VS = π/ω r = π LC eq . VOLUME 8, 2020 For ZVS situation in Fig. 3(b), drain-source voltage v ds might reach a negative value when 2v in < v o according to (4). For a Si-based MOSFET, the negative value of v ds is clamped by the body diode. Comparatively, GaN HEMT is a kind of common power devices with a symmetric structure, without parasitic diodes and works upon two dimensional electron gas (2DEG) [26]. Similarly, the resonance voltage will be clamped to zero when v gd is higher than threshold voltage. Furthermore, no reverse recovery is induced owing to 2DEG conduction mechanism.
To investigate the optimal ZVS time t zvs , the zero-crossing point of v ds is located by setting v ds (t 3 ) = 0, which gives the minimum ZVS time as After t 3 , inductor current rises with a slope of v in /L, the negative to positive zero-crossing point of i L is given by: Therefore, ZVS can be achieved from t 3 to t 4 , where the GaN HEMT is reversely conducted.
Above analysis is based on the assumption that C eq is irrelevant to voltage level. However, both C oss and C j vary greatly with voltage. Since resonance period is directly related to capacitor value, this ignorance can lead to deviated results of the resonance behavior, such as VS/ZVS boundary and optimal VS/ZVS time. Furthermore, the beginning of the resonant process is often located by ZCD approach, whereas an accurate ZCD module with matched speed could increase overall design complexity, cost and size, especially in high frequency applications.

III. PIECEWISE EQUIVALENT CAPACITANCE MODEL AND EOT CONTROL
In order to address aforementioned issues, a piecewise equivalent capacitance model is proposed to correct the optimal VS/ZVS time, which provides a reasonable explanation to the resonant behavior with nonlinear capacitors. The derived VS/ZVS time is implemented by an extended off-time (EOT) controller. It is a simple and effective approach to achieve CRM operation without ZCD module. The EOT controller is described as

Scheme of boost converter under EOT control is given in
where the extended off-time t ext = t rise + t VS/ZVS , as shown in Fig. 5. The proposed approach can be applied to other Therefore, the inductor current is unbalanced during one switching cycle, which leads to a current decrease. Finally, owing to the unidirectional conduction characteristic of the diode, the converter converges to CRM operation in steady state.
In order to achieve VS/ZVS, t ext should be carefully considered, where t VS/ZVS is the VS/ZVS time, and t rise is the rising time of v ds at the falling edge of v gs , as shown in Fig. 5.
In the followings, a piecewise equivalent capacitance model is proposed to linearize the nonlinear capacitors in each interval. With the linearized capacitance, the optimal VS/ZVS time is derived by the analytical solutions of resonant process.

B. PIECEWISE EQUIVALENT CAPACITANCE MODEL
Considering the variations of equivalent capacitors, C eq (v ds ) is a function of v ds . Resolving equations (1) and (2), a differential equation for v ds during resonance is given by Obviously, (9) is a second-order nonlinear differential equation. Its analytical solution is hard to derived. Conventional method consumes that C eq (v ds ) is a fixed value, which makes (9) a linear equation. It simplifies the analysis for the resonance behavior. However, the results can lead to mistake solutions of the resonant process.
To refine the resonant process, a piecewise equivalent capacitance model is introduced in the following.
In order to derive the accurate analytical solutions of (9), the nonlinear item, which is the second order differential term, should be eliminated. Considering the complexity and accuracy of the derivation process, the piecewise equivalent capacitance model for C oss and C j is proposed.
A piecewise equivalent capacitance example when v o = 400V is given in Fig. 6(a). The C oss (v ds ) is divided into three intervals. The n th interval boundaries are chosen from v n to v n+1 , where the capacitance in the boundary satisfies C oss (v n+1 ) = 2C oss (v n ), (n = 3,4). Comparatively, C j (v ds ) drops rapidly to a small value after the resonance when voltage across the diode turns high. Since C j is much smaller than C oss in most situations, it is acceptable to divide C j (v ds ) into two intervals, where the first interval boundary satisfies C j (v 2 ) = 2C j (v 5 ), as shown in Fig. 6(a).
For the entire resonance circuit, C eq is acquired by combining C oss with C j , as shown in Fig. 6(b). Finally, four In order to derive analytical solutions of the resonant process, the equivalent capacitance of each interval is obtained by a charge-based equivalent method, which calculates the average capacitance for each interval. For voltage interval boundary with v a and v b , the charge Q c on capacitors satisfies: Therefore, the equivalent capacitance is derived by

C. NUMERICAL SOLUTIONS FOR t VS/ZVS AND t ch 1) NUMERICAL SOLUTIONS FOR T VS/ZVS
Based on the equivalent capacitance and initial conditions of each interval, the analytical solutions for v ds and i L during the resonant process are derived. Resonant curves of v ds and i L at VS and ZVS situation are given in Fig. 7. For VS situation in Fig. 7(a), VS point is located by the valley value of v ds or the zero-crossing point of i L . Comparatively, as shown in Fig. 7(b), there is a time range that ZVS can be achieved. Detail derivation process for t VS and t ZVS is given in the following. Although the capacitors are voltage-varying, the resonance structure remains the same during VS/ZVS time, as shown in Fig. 2(b). Therefore, resonance behavior of each interval can be also described by (1) and (2), where the common solution of v ds in each interval when v ds > 0 is v ds (t) = v in +a n cos (ω n (t −t n ))+b n sin (ω n (t − t n )) , (12) where ω n = 1 LC eq,n , n = 1,2,3,4. According to (2), i L (t) in each interval is solved as i L (t) = C eq,n dv ds (t) dt = −a n ω n C eq,n sin (ω n (t − t n )) + b n ω n C eq,n cos (ω n (t − t n )) .
Derivation of a n and b n is based on the boundary conditions. By setting t = t n in (12), a n is derived as Furthermore, b n is derived by the current boundary condition. By setting t = t n , differentiating (12) gives dv ds (t n )/dt = b n ω n . Therefore, b n is obtained by  Since inductor current keeps constant at the boundary of the n th and n-1 th interval, the boundary current value is given by i L (t n ) = −a n−1 ω n−1 C eq,n-1 sin (ω n−1 (t n − t n−1 )) +b n−1 ω n−1 C eq,n-1 cos (ω n−1 (t n − t n−1 )) . (16) With analytical solutions of the resonant process, the VS point and the first ZVS point can be derived. When the valley value is above zero, VS is achieved at the valley point.
When the valley value reaches below zero, ZVS is achieved starting from the first zero point of v ds , which locates at t ZVS1 shown in Fig. 7(b). After this point, the inductor current will rise up to zero with a slope rate of v in /L, where the GaN HEMT is reversely conducted. Therefore, the negativepositive inductor current zero-crossing point t ZVS2 is derived by where t ext1 is acquired by solving (13) = 0. From t ZVS1 to t ZVS2 , v ds can be regarded as zero, where ZVS is achieved.

2) NUMERICAL SOLUTIONS FOR T CH
According to Fig. 5(b), charge balance of the equivalent capacitance during the conversion time gives In general, a converter based on GaN HEMT and SiC diode provides a relatively high conversion speed of switching state, which makes t ch a much smaller value compared with t VS/ZVS . Therefore, inductor current during t ch can be regarded as a current source during the charging time to parasitic capacitors.
Since i pk = T on L/v in , t ch is derived by D. OVERALL DERIVATION PROCESS OF OPTIMAL EXTENDED OFF-TIME Fig. 8 gives the overall calculation process for the extend off-time to achieve VS/ZVS. Firstly, the C oss and C j are divided into intervals with different voltage levels. The equivalent capacitance is calculated by the charge-based equivalent method based on (11). Then, analytical solutions of the resonant process are derived as (12) and (13), with which the optimal t VS/ZVS is obtained. Furthermore, t ch is calculated by (19). Combining t VS/ZVS and t ch , the optimal t ext is derived to achieve VS/ZVS under EOT control.

E. SMALL SIGNAL MODELING
For stability analyses and compensator design, small signal model of boost converter with EOT control is given in the followings. In Fig. 9, {G vi (s), G vg (s), G vr (s)} are transfer functions from i ref , v in and R to the output voltage, respectively. Under EOT control, the inductor current peak value is regulated to i ref . Therefore, the output current average value of the boost converter is given by .
Since output capacitor is charged with i o,av , and discharged with v o /R, the output voltage is expressed as Differential functions of (20) and (22) are given by Finally, small signal model of the system is derived as The small signal model is first-order, and all transfer functions have the same pole with different gains.
In order to improve the system stability, a PI compensator is used to compensate the loop. Based on small-signal model of the converter, the PI compensator is optimized as P = 0.136 and I = 1936. Furthermore, the open-loop bode plot is given in Fig. 10.
According to Fig. 10, the cross-over frequency ω cross is 32.5k rad/s, while the phase margin is 96.5 degrees. This indicates great stability toward input/output voltage steps.

IV. SIMULAITONS AND EXPERIMENTS
Simulations are carried out in MATLAB/Simulink to derive the curves of optimal VS/ZVS time versus v in and v o . Specifications of the parasitic capacitors are obtained by datasheets of the experimental components. An experimental prototype, as shown in Fig. 11(b), is built to verify the proposed model and controller. Curves of the derived VS/ZVS time versus v in and v o based on piecewise equivalent capacitance model and constant capacitance model are given first. Then, comparisons of voltages and currents between analytical solution and experimental results are given to verify the effectiveness of proposed model and controller. Efficiency comparison is also given with respect to different voltage levels.
The curves of C oss and C j with respect to junction voltage is given in Fig. 1, where the main switching component is a GaN HEMT from GaNSystem (GS66508T) [9] and a SiC diode from ST (STPSC8H065) [10]. The SiC diode is used to match the switching frequency while eliminates the reverse recovery current.
Main specifications of the prototype are given in TABLE 3. Two ADC (LTC2314-14) modules are used to convert the analog values to digital signals. Digital value of input/output voltage are received and processed by a FPGA (Cyclone IV) board, as shown in Fig. 11(a). A 1µF capacitor (MPP105J6241120) and a 0.1µF bypass capacitor are adopted as the output capacitor. The core material of inductor is PQ20/16-3F36 from FERROXCUBE, which is suitable for operation frequency below 1MHz.
The input/output current and voltage and the efficiency are measured by power analyzer PA5000H. The measure range of input/output voltage is 300V/600V with absolute error of 0.01V. With a rated range of 5A current measurement board, the measure range of input/output current is set as 2.5A/1A with absolute error of 0.001A. The final efficiency measurement accuracy error provided by the power analyzer is 0.05%. VOLUME 8, 2020

A. t ch AND t VS/ZVS
Curves of optimal VS/ZVS time versus v in and v o based on piecewise equivalent capacitance model and constant capacitance model are given in Fig. 12(a) and Fig. 12 (b). Within all v in and v o range, t VS/ZVS based on constant capacitance model is from 150ns to 410ns. However, it varies from 210ns to 490ns based on piecewise equivalent capacitance model, which shows considerable differences compared with that based on constant capacitance model. Furthermore, the VS/ZVS boundary is no longer 2v in = v o , as shown in Fig. 12 (a).
As shown in Fig. 13, curves of t ch with v in and v o are plotted, where t ch varies within 25ns. Adding t ch to t VS/ZVS gives t ext . With the derived extended off-time, experimental comparisons are given with respect to different capacitance equivalent method.

B. EFFECTIVENESS OF THE ANALYTICAL SOLUTIONS
In order to compare the effectiveness of the mentioned capacitance equivalent methods, experiments are given with respect to two output voltage levels at output power of 200W.
Under the proposed EOT control, the experimental prototype works at different voltage situations, where the currents and voltages are given in Fig. 14 Fig. 14(a), the valley voltage is 20V, which means that the resonant process derivates from typical sinusoidal waveform. Furthermore, the achieved t VS/ZVS is measured for the comparison with the calculated t VS/ZVS , as shown in TABLE 4. The calculated t VS/ZVS based on piecewise equivalent capacitance model deviates from the experimental results within 5ns. In practice, errors within 5ns are accurate enough to achieve VS/ZVS. Comparatively, the calculated t VS/ZVS based on the conventional constant capacitance model deviates from the experimental results within 72ns. Obviously, the results by conventional model has unacceptable accuracy for VS/ZVS.

C. EFFICIENCY COMPARISON AND LOSS BREAKDOWN
The accuracy of extended off-time directly affects the overall efficiency of the system. In the followings, efficiency comparisons are given with respect to t ext by the proposed piecewise equivalent capacitance model and conventional constant capacitance model.
The efficiency comparisons at rated power of 200W is given in Fig. 16. The highest efficiency of 99.15% is achieved at a ZVS situation where v in = 150V and v o = 400V.    Similar efficiency trend is achieved with respect to input voltage when v o = 320V and v o = 400V, as shown in Fig. 16(a) and Fig. 16(b). When v in >160V, VS is achieved. Although the valley voltage increases as v in increases, the reduced efficiency with piecewise equivalent capacitance model (labeled as piecewise capacitance model) is always less than that with constant capacitance model. When v in < 160V, ZVS is achieved. However, the average input current increases as v in decreases, which lead to higher conduction loss.
To quantify the changes of each losses, loss breakdown is given in Fig 17. It shows that higher switching frequency leads to higher switching loss under constant capacitance model (labeled as constant model), where additional switching loss of 0.848W is induced compared with piecewise equivalent capacitance model (labeled as piecewise model).
When v in reduces, the input current rises up, which induces higher inductor loss. This result indicates that switching loss can be greatly reduced with piecewise equivalent equivalence model, where the VS/ZVS is achieved. As a result, obvious overall efficiency improvement under piecewise model is achieved compared with that under constant capacitance model. He is currently an Associate Professor with the School of Automation, Wuhan University of Technology. His research interests include the power electronics system design and control, such as dc-dc converter sensorless control strategies, electrical machine parameters estimation by control theory, system nonlinearity compensation for dc-dc converters, and voltage source inverters.

V. CONCLUSION
LINKAI LI received the B.Eng. and M.S. degree in automation from the College of Engineering, Nanjing Agriculture University, Nanjing, China, in 2014 and 2017, respectively. He is currently pursuing the Ph.D. degree in microelectronics with the School of Optical and Electronic Information, Huazhong University of Science and Technology. His current research interests include the optimal design and digital control of power converters.
GAOSHUAI SHEN received the B.Eng. degree in electrical engineering and automation from the School of Automation, Wuhan University of Technology, Wuhan, China, in 2019. He is currently pursuing the master's degree in microelectronics with the School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan, China. His current research interests include modeling, analysis, and control of dc-dc power electronics systems. VOLUME 8, 2020