Analysis of the Influence of Silicon-on-Insulator Lateral Double-Diffused MOS Device Substrate Deep Depletion on the Transient Breakdown Voltage

With two-dimensional device simulation software, the influence of the deep depletion (DD) of the silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) device substrate on the transient breakdown voltage (<italic>TrBV</italic>) was analyzed. Based on the changes in the characteristics of the charge distribution and the depletion layer in the device substrate with time and the related parameters in the off state, the mechanism of their action on the transverse and vertical breakdown voltages (<italic>BV</italic>s) was studied. <italic>TrBV</italic> demonstrates completely different characteristics from the static breakdown voltage (<italic>StBV</italic>) due to the DD effect of SOI LDMOSs. Low drift region concentration (<inline-formula> <tex-math notation="LaTeX">$N_{\mathrm {d}}$ </tex-math></inline-formula>) and substrate doping concentration (<inline-formula> <tex-math notation="LaTeX">$P_{\mathrm {sub}}$ </tex-math></inline-formula>) are conducive to obtaining a high maximum <italic>TrBV</italic>. With increasing drain voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {d}}$ </tex-math></inline-formula>), the turn-off nonbreakdown time (<inline-formula> <tex-math notation="LaTeX">$T_{\mathrm {nonbv}}$ </tex-math></inline-formula>) of the device with higher <inline-formula> <tex-math notation="LaTeX">$P_{\mathrm {sub}}$ </tex-math></inline-formula> decreases faster. However, the <inline-formula> <tex-math notation="LaTeX">$T_{\mathrm {nonbv}}$ </tex-math></inline-formula> with higher <inline-formula> <tex-math notation="LaTeX">$P_{\mathrm {sub}}$ </tex-math></inline-formula> is higher at low <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {d}}$ </tex-math></inline-formula>. Therefore, the maximum <inline-formula> <tex-math notation="LaTeX">$T_{\mathrm {nonbv}}$ </tex-math></inline-formula> can be obtained by optimizing <inline-formula> <tex-math notation="LaTeX">$N_{\mathrm {d}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$P_{\mathrm {sub}}$ </tex-math></inline-formula> under a given <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {d}}$ </tex-math></inline-formula>. In addition, <inline-formula> <tex-math notation="LaTeX">$T_{\mathrm {nonbv}}$ </tex-math></inline-formula> is greatly reduced with increasing temperature.


I. INTRODUCTION
Regarding the static breakdown voltage (StBV) of siliconon-insulator (SOI) lateral double-diffused metal-oxidesemiconductor (LDMOS), when the device is in the off state, there is an inversion layer under the buried oxide (BOX), and the blocking voltage can only be sustained by the drift region and the BOX [1], [2]. Due to the limitation of the device's vertical dimension, it is difficult for conventional SOI LDMOS to obtain a BV higher than 600 V. To allow SOI LDMOS to be used in high voltage integrated circuits, many new device structures have been proposed [3]- [15], some with breakdown voltages (BVs) exceeding 1000 V [13]- [15]. However, these high voltage structures are all based on the research results of StBV. Whether these structures are suitable The associate editor coordinating the review of this manuscript and approving it for publication was Kalyan Koley .
for the transient breakdown voltage (TrBV) is still awaiting analysis and verification.
SOI LDMOSs are often used as switching devices. The operating frequency of an SOI LDMOS is several hundred kHz at a BV above 100 V and that of a radio frequency power SOI LDMOS with a BV lower than 100 V can reach more than 1 GHz. When the device is turned off quickly, the drain voltage increases sharply. There is no time to generate minority carriers in the substrate depletion layer to form the inversion layer, so the depletion layer can only be extended in depth, and substrate deep depletion (DD) appears [16]. The temperature of an SOI LDMOS during normal operation is controlled to 473 K. At this temperature, the time from the appearance to disappearance of the DD effect is not particularly short. This effect has a significant influence on the TrBV of the device and cannot be ignored. E. Napoli et al. carried out in-depth research on the SOI LDMOS TrBV [16]- [22], but few relevant research results VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ have been reported by other scholars. In [16], E. Napoli et al. proposed the concept of using DD to allow the substrate to participate in sustaining the BV to improve the BV of SOI LDMOSs. In addition, through simulation and experiment, they proved that reducing the doping concentration of the substrate can enhance the DD effect and further improve the device TrBV [16], [17]. In [18], the device substrate is divided into two doping regions: a high doping region and low doping region. The high doping region of the substrate below the source reduces the source surface electric field, and the depletion layer can be further extended downward in the substrate low doping region below the drift region and the drain, so a good compromise between the dynamic withstand voltage and specific on-resistance is obtained [18]. In [19], E. Napoli hypothesized a condition where the device is a thin SOI and fully depleted and proposed a one-dimensional TrBV model that can be used to analyze the influence of various device parameters on TrBV. In [23], we proposed a two-dimensional electric field analytical model for when the device has just been turned off to analyze the maximum TrBV that the device can reach. E. Napoli et al.'s research results mainly focus on thin SOIs. Although the proper reduction of the doping concentration of a thin SOI substrate can improve TrBV, the device BV decreases when the concentration is reduced too much, which is more serious for nonthin SOIs. In addition, the electric field distribution in the drift region of SOI LDMOS devices is two-dimensional, and the breakdown may occur at the source surface, the drain surface or the Si side of the Si/SiO 2 interface below the drain. The one-dimensional BV model can only analyze the breakdown at the drain end. Different from StBV, TrBV involves the substrate DD effect. The area of the substrate depletion region is related to the doping concentration and is affected by the generation rate of minority carriers, which changes with time. The charge in the substrate is distributed in the depletion layer and the inversion layer and changes with time. The depletion layer and charge in the substrate affect the vertical and transverse BV of the device, respectively. Therefore, the analysis of TrBV with only the two-dimensional electric field distribution at the moment just after turn-off is not comprehensive enough.
Based on that the depletion layer and charge distribution in substrate change with time, the influence of DD on the TrBV of the device is analyzed in this paper with two-dimensional device simulation software. This study also provides the results of the maximum TrBV and turn-off nonbreakdown time by optimizing the doping concentration in the drift region and the doping concentration in the substrate, which provides a basis for the BV design of fast switching SOI LDMOS power devices.

II. SIMULATION AND DISCUSSION
A simple circuit is used to simulate the turn-off process of the device. As shown in Fig. 1, the source and substrate electrodes of SOI LDMOS devices are grounded. The gate voltage V g is applied to the gate electrode through resistance R g , V g reduces from 15 V to 0 V until the device is turned off, and T f is the time of this reduction. The drain voltage V d is applied to the drain electrode through the resistance R d , whose role is to limit the maximum drain current when the device has broken down. According to the parameters of the SOI LDMOS, the choice of the appropriate values for R g , R d and T f can cause the devices to turn off quickly, ensuring DD in the substrate. In the simulation, the V d step increases until the device is broken down in the off state, and the BV of the device is equal to V d . When the drain current increases rapidly and exceeds 1 × 10 −7 A in the off state, the device is broken down. The parameters of the device structure are shown in Fig. 1, where L d is the length of the drift region, t S and t I are the thicknesses of the drift region and BOX, respectively, and N d and P sub are the doping concentrations of the drift region and substrate, respectively. In addition, the gate oxide thickness of the device is 50 nm, and the channel length is 4 µm. The two-dimensional device simulation software Medici is used to analyze the TrBV of the device [24]. The physical models adopted in the simulation are the same as that in study [18]. Compared to other recombinations, Shockley-Hall-Read recombination plays a leading role in the substrates of SOI LDMOS. The Shockley-Read-Hall electron lifetime and the Shockley-Read-Hall hole lifetime used in the simulation are both 1 × 10 −7 s, and the device temperature is 300 K without special instructions [24].
To reveal the different mechanism of StBV and TrBV, the influence of P sub on StBV is first analyzed. For the high StBV of SOI LDMOS, it is usually not necessary to consider P sub . In the realization of the process, the device P sub is low, commonly at the magnitude of 10 14 cm −3 . The P sub values of the two simulation devices are set as 7 × 10 14 cm −3 and 2 × 10 15 cm −3 , and the other parameters are the same for both devices. Fig. 2 shows the potential and substrate charge distribution when the two devices are broken down. It can be seen from Fig. 2 (a) that although the thicknesses of the two device depletion layers are different, both of layers are very thin, so the contribution to the vertical BV can be ignored. At the same drain voltage, the thickness of the inversion layer of device varies minimally in the P sub range of 10 14 cm −3 to 10 15 cm −3 , and the substrate charge is mainly distributed in the inversion layer. As shown in Fig. 2 (b), the substrate charge distribution of the two devices is similar at the same drain voltage. The similar substrate charge distribution has almost the same modulation effect on the surface electric field of the drift region of each device. In addition, the high concentration negative charge layer under the BOX shields the electric field in the substrate, so the vertical BV of the device is only sustained by the drift region and the BOX [1], [2]. Therefore, P sub has minimal effect on StBV. The StBV values of the devices with substrate doping concentrations of 7 × 10 14 cm −3 and2 × 10 15 cm −3 are 194 V.
Because of the DD effect in the substrate, P sub has a significant influence on TrBV. When an SOI LDMOS is just turned off, the depletion layer in the substrate greatly expands similar to that of an LDMOS device. As shown in Fig. 3 (b), the negative charge is evenly distributed in the substrate depletion layer, and the charge concentration is equal to P sub . As shown in Fig. 3 (a), although the depletion layer more readily expands and makes a greater contribution to the vertical BV in the substrate devices with low doping, the negative charge concentration of the depletion layer in the substrates with low doping is also low, the weakening of the source electric surface field is not sufficient, breakdown occurs on the source surface too early, the devices are not fully depleted, and the transverse BV is not high. Limited by the transverse BV, the BV of the device with P sub of 7 × 10 14 cm −3 is only 149 V, even lower than its StBV. For the device with P sub of 2 × 10 15 cm −3 , the charge in the substrate depletion layer not only effectively reduces the surface electric field at the source and enhances the transverse BV but also partially sustains V d and increases the vertical BV of the device, so there is no breakdown at V d = 194 V. The above results of simulation show that for the conventional SOI LDMOS, the methods designed according to StBV are not suitable for the TrBV of the device, and simply reducing the substrate doping concentration does not necessarily enhance the device BV but sometimes reduces the device BV. In the simulation, the N d optimized according to StBV is 4.6 × 10 15 cm −3 . To provide a comparison with other N d for TrBV, the simulation results for this N d value are added to Fig. 5 and Fig. 8.
For TrBV, an SOI LDMOS has a reduced surface electric field (RESURF) effect similar to that of an LDMOS. The higher the P sub is, the more obvious its weakening of the  source surface electric field and its strengthening of the drain surface electric field are. Fig. 4 shows the surface electric field distribution of the broken down device when N d = 4 × 10 15 cm −3 and P sub differs. It can be seen in Fig. 4 that when P sub = 1.5 × 10 15 cm −3 , the surface electric field has a maximum value at the source, breakdown occurs at the source surface, and BV is 275 V. When P sub = 2.3 × 10 15 cm −3 , the surface electric field has similar peak values in the source and the drain. Breakdown occurs at the interface between the drift region and the BOX below the drain, and the maximum BV reaches 317 V. When P sub = 4.5 × 10 15 cm −3 , the maximum value of the surface electric field appears at the drain, breakdown occurs on the surface of the drain, and BV decreases to 284 V. Fig. 5 shows the impact of N d and P sub on TrBV. When N d is constant, optimizing P sub can yield the maximum TrBV. The lower N d is, the higher the maximum BV after optimizing P sub . This is because the lower N d is, the more likely it is for the drift region of the device to be depleted, and the lower the P sub optimized for the maximum BV is. Regarding improvement in the vertical BV, low P sub is conducive to the expansion of the depletion layer in the substrate, so the substrate sustains higher BV. In Fig. 5, when N d is 2 × 10 15 cm −3 and P sub is 3 × 10 14 cm −3 , the TrBV of the device reaches 352 V, which is 81.44% higher than the StBV of 194 V. In this case, it is not the vertical BV but transverse BV that restricts the device BV. However, low N d makes the BV more sensitive to the variation in P sub near the maximum BV, which results in higher requirements for the device manufacturing process because with increasing P sub , the transition period in a low N d device from incomplete depletion to full depletion becomes shorter, and correspondingly, the BV increases more quickly. However, when the device is completely depleted, the electric field on the drain surface of the low N d device increases faster with increasing P sub , which leads to a rapid decrease in the BV of the device. It can also be seen from Fig. 5 that with increasing P sub , the depth of the substrate depletion layer decreases, the BV sustained by the substrate decreases, and TrBV is closer to StBV and tends to be saturated. The larger the N d value is, the greater the positive charge concentration introduced at the interface between the drift region and the BOX is. It can be concluded from the boundary condition of electric displacement that the enhancement in the electric field in the BOX enhances the BV it sustains. Therefore, the higher the N d value is, the higher the saturation value of BV.
Discussed above is the maximum drain voltage that the device can sustain when the device has just been turned off and the substrate depletion layer expands to the maximum, namely, the maximum TrBV (TrBV max ). With increasing turn-off time, the depletion layer in the substrate decreases, as does the TrBV of the device. Therefore, TrBV max can only represent the maximum BV under the condition that the device parameters have been determined and cannot be used as a reference for its working frequency. Obviously, it is not comprehensive to describe the TrBV characteristics of an SOI LDMOS only by TrBV max . In this paper, a turnoff nonbreakdown time (T nonbv ) is defined, that is, when a positive voltage is applied to the drain electrode of the device, the time that the device remains in a nonbreakdown state in the off state. In this way, the lowest operating frequency of the device at a certain blocking voltage can be determined according to the drain voltage and T nonbv . First, the process from turning off to breakdown of the device is analyzed. Fig. 6 shows the charge distribution on the lower surface of the BOX, the vertical potential and electric field distribution at the drain end, and the electric field distribution on the device surface in four corresponding equal intervals during the period from effective shutdown to breakdown. It can be seen from Fig. 6 (a) that when the device is effectively turned off at 5.85 µs, the substrate DD layer appears, but the inversion layer does not form. The charge concentration on the lower surface of the BOX is equal to the concentration of P-type impurities in the substrate, which is 2.3 × 10 15 cm −3 . After that, as the electrons generated in the depletion layer of the substrate continuously reach the lower surface of the BOX, the inversion layer begins to form, and the charge concentration Q S on the lower surface of the BOX increases continuously, reaching 2.11 × 10 16 cm −3 when the device is broken down. It can be seen from the boundary condition of the electric displacement that increasing Q S decreases the electric field on the Si on the lower surface of the BOX and increases the electric field on the BOX. With decreasing depletion layer of substrate, the drain voltage of the substrate is lower. However, with increasing drain voltage sustained by the drift region and the BOX, their electric fields increase constantly until the device is broken down. Breakdown occurs in the drift region of the drain end and the Si side of the BOX interface. It can be seen from Fig. 6 (b) and (c) that the maximum electric fields in the drift region and the BOX increase from 2.74 × 10 5 V/cm and 8.55 × 10 5 V/cm at the time of turn off to 3.19 × 10 5 V/cm and 1.01 × 10 6 V/cm at the time of breakdown, respectively. While the drain voltage sustained by the drift region and the BOX increases from 148 V to 194 V, the drain voltage sustained by the substrate decreases from 112 V to 66 V. It can also be seen from Fig. 6 (d) that the substrate charge has a strong modulation effect on the surface electric field, which is specifically shown by the fact that with increasing charge concentration under the BOX of the drain end, the source surface electric field weakens, and the drain surface electric field significantly increases. This shows that when the drain voltage and other parameters of the device are not changed, if too low N d is used, the surface electric field at the drain increases rapidly under the modulation of the substrate charge on the surface electric field, which inevitably leads to a decrease in T nonbv .
Next, the influence of N d and P sub on T nonbv is analyzed. When the SOI LDMOS is turned off, V d is sustained by the drift region, BOX and substrate. If the voltage sustained by the drift region and the BOX is V 1 (t), and the voltage sustained by the substrate is V 2 (t), then: In the off state, with the decreasing depletion layer, V 2 (t) decreases, and the decreased voltage is sustained by the drift region and the BOX; that is, the amount of decrease in V 2 (t) is equal to the amount of increase in V 1 (t). V 1 (t) increases continuously to the limit voltage sustained by the drift region and the BOX, V bv1 , until the device is broken down. Breakdown occurs in the drift region. When the drift region is completely depleted, V bv1 is determined by the vertical dimension of the device, and its value is approximately equal to StBV. Higher N d slightly improves V bv1 . T nonbv is determined by two factors: one is V (t 0 ) = V bv1 − V 1 (t 0 ), in which t 0 is the effective turn-off time of the device; the other is the increased speed of V 1 (t), whose value is equal to the decreased speed of V 2 (t). The larger V (t 0 ) and the smaller the increasing speed of V 1 (t) are, the larger T nonbv is. With increasing time, When V (t) = 0, the device is broken down. The decreased speed is closely related to the decreased speed of the depletion layer of the substrate. If the decreased area of the substrate depletion layer is S in unit time and the area of inversion layer is ignored, then In (2), S(t) is the area of the depletion layer and is the net carrier generation rate in the depletion layer. In the simulation, the electron capture coefficient is equal to the hole capture coefficient; that is, r n = r p = r, the recombination center energy level is equal to the forbidden band central energy level, and the carrier concentration in the depletion layer is far lower than the intrinsic carrier concentration, so we obtain G: In (3), N t is the recombination center concentration, and n i is the intrinsic carrier concentration. According to (2) and (3), we obtain: It can be seen from (4) that when P sub is constant, the decreasing speed of the depletion layer changes from fast to slow with increasing time, and the size of the substrate depletion layer is the main factor that determines the voltage value sustained by the substrate, so the value of the decreasing speed of V 2 (t) changes from high to low. It can be seen from Fig. 6 (c) that in the same time interval, the amount of voltage reduction sustained by the substrate changes from large to small, which is consistent with the previous analysis. In addition, it can be seen from (4) that the higher P sub is, the slower the reduction speed of the depletion layer is. Fig. 7 shows the vertical potential distribution of the drain end at different times and different drain voltages for two devices in the off state. In device 1, N d = 5 × 10 15 cm −3 , and P sub = 6 × 10 15 cm −3 , while in device 2, N d = 4 × 10 15 cm −3 , and P sub = 2.3 × 10 15 cm −3 . As shown in Fig. 7 (a), when t = 5.85 µs, the two devices are effectively turned off, and their drain voltage is 220 V. The P sub of device 1 is more than twice that of device 2, and the area of the depletion layer of device 1 is significantly smaller than that of device 2. The V 2 (t 0 ) values of the two are 56 V and 91 V, respectively, and the V 1 (t 0 ) values are 164 V and 129 V, respectively. The N d of device 1 is higher, which leads to a slightly higher V bv1 . The V bv1 values of the two devices are 195 V and 194 V respectively, from which it can be calculated that their V (t 0 ) values are 31 V and 65 V, respectively. However, from (4), it can be seen that the S of device 2 is significantly larger than that of device 1, the same as the decreasing speed relationship of V 2 (t) and increasing speed relationship of V 1 (t). When t = 27635.85 µs, the V 2 (t) values of device 1 and 2 are reduced to 28 V and 26 V,  respectively, and the V (t) of device 2 is reduced to 0, having just been broken down. At this time, for device 1, V (t) = 3 V. Because its increasing speed of V 1 (t) is slow, it is not broken down until t = 36705.85 µs. The potential distribution of the two devices when V d = 240 V is shown in Fig. 7 (b). It can also be calculated that the V (t 0 ) values of device 1 and 2 are 19 V and 55 V, respectively. Compared with the conditions when V d = 220 V, the V (t 0 ) of device 1 decreases more because the P sub of device 1 is higher and the substrate depletion layer expands less when the increase in V d is the same, which results in the increase in the V 1 (t) of device 1 being greater than that of device 2 when the device has just been turned off. Therefore, the decrease in the V (t 0 ) of device 1 is too large. Even though the increase in the V 1 (t) of device 1 occurs more slowly, it is still broken down before device 2 at t = 15527.85 µs. It can be seen from the above analysis that the value of V (t 0 ) and increasing speed of V 1 (t) are affected by V d , N d , and P sub . When the device is completely depleted, increasing N d can only slightly increase V (t 0 ). An increase in P sub reduces V (t 0 ) on the one hand and decreases the increasing speed of V 1 (t) on the other hand. When V d is high enough, the decrease in V (t 0 ) along with the increase in P sub is dominant, and T nonbv decreases rapidly. When V d is low enough, the decrease in the increasing speed of V 1 (t) along with the increase in P sub is dominant, and T nonbv increases. Fig. 8 (a) shows the influence relationship VOLUME 8, 2020 of V d , N d and P sub on T nonbv when the device temperature T is 300 K. With increasing V d , the V (t 0 ) of the device with higher P sub decreases faster, which leads to a faster decrease in T nonbv . In contrast, the lower the P sub is, the flatter the decrease in the T nonbv of the device with increasing V d is. When V d is low, such as 220 V, the higher P sub is, the higher T nonbv is. However, with increasing V d , the higher the P sub is, the more T nonbv decreases. When V d is relatively high, the T nonbv of device with higher P sub may be lower than that with low P sub . Therefore, when V d is consistent, the maximum T nonbv can be obtained by optimizing N d and P sub . Fig. 8 also shows the impacts of different T , V d , N d and P sub on T nonbv . It should be emphasized that with increasing device temperature, StBV increases. If V d is close to StBV, T nonbv becomes very large and is not easy to observe in Fig. 8. Therefore, with increasing device temperature, the lower limit of the value of V d used in the simulation increases. n i is a function of temperature, which increases approximatively exponentially with T . From (4), it can be seen that with increasing T , S speeds up rapidly, which leads to a decrease in T nonbv . When T increases, the trend that the T nonbv of devices with the same N d and P sub increases with V d does not change. For devices with different P sub , the lower the P sub is, the larger the S(t) is. Considering the relationship between n i and T , we can obtain through (4) that with increasing T , the S of the device with lower P sub is much larger than that with higher P sub . This means that when increasing to the same temperature, the T nonbv of the device with low P sub decreases more. For this reason, it can be seen in Fig. 8 that with increasing T , the curve distance of T nonbv corresponding to different P sub changing with V d becomes larger. When T = 450 K, the five curves have almost no overlap.

III. CONCLUSION
Because of the DD effect on SOI LDMOSs, TrBV has completely different characteristics from StBV. The charge in the substrate depletion layer modulates the surface electric field, which affects the transverse BV of the device. Additionally, the substrate depletion layer sustains part of the vertical BV. The TrBV max value can be obtained by optimizing N d and P sub . Under a given drain voltage, the maximum T nonbv can be obtained by optimizing N d and P sub . In addition, the T nonbv of the device is greatly reduced with increasing temperature. The lower P sub is and the higher the temperature is, the more the T nonbv of the device decreases.