Blind Estimation of Spreading Sequence and Data Bits in Direct-Sequence Spread Spectrum Communication Systems

At the transmitter of a Direct Sequence Spread Spectrum (DSSS) communication system, data bits are spread using a spreading sequence. To demodulate the transmitted data bits, the received signal should be de-spread using the same spreading sequence. However, there are many non-cooperative communication systems, where a receiver does not have the information on the spreading sequence. In such systems, to demodulate the transmitted data bits across a wide area, it is necessary to blindly estimate the spreading sequence at low Signal-to-Noise Ratio (SNR). Furthermore, for real-time processing, the computational complexity for the blind estimation should be minimized. In this paper, a novel algorithm is proposed to blindly estimate a spreading sequence and data bits based on turbo processing for both synchronous and asynchronous cases. The proposed algorithm can significantly improve the error rates of estimated data bits and the chips in the spreading sequence compared to an Eigen-Value Decomposition (EVD) based algorithm. Furthermore, compared to the EVD-based algorithm, the proposed algorithm drastically reduces the number of required multiplications.


I. INTRODUCTION
Direct Sequence Spread Spectrum (DSSS) has been widely used in both military and commercial communication systems [1]- [6]. At the transmitter of a DSSS communication system, to generate a wideband signal, data bits are multiplied by a spreading sequence, which comprises multiple chips [2]. The transmitted data bits are demodulated after the received signal is despread with the same sequence. The ratio of the chip rate to the data bit rate is defined as processing gain. Due to the processing gain, the received signal has low probability of interception and can be demodulated even below the level of Additive White Gaussian Noise (AWGN) power [2], [5]- [7].
There are several non-cooperative communication systems, where the receiver does not have information on a transmitted DSSS signal. The applications of these systems include eavesdropping, spectrum surveillance and source localization [8]- [11]. In non-cooperative communication systems, it is common for the receiver to possess information on The associate editor coordinating the review of this manuscript and approving it for publication was Zilong Liu . the modulation parameters, including data rate and a spreading sequence used in the transmitter. Furthermore, there are cases where the receiver does not even have information of the presence of a DSSS signal.
The receiver should blindly estimate several modulation parameters and a spreading sequence to recover transmitted data bits. Without the information on a DSSS signal, the usual procedure for blind estimation is implemented as follows [12]: The receiver detects whether there is a DSSS signal. If there exists a DSSS signal, the receiver estimates the modulation parameters such as the data bit rate and the length of a spreading sequence from the received signal. After parameter estimation, a spreading sequence is estimated to demodulate the transmitted signal.
To detect the presence of a DSSS signal, several studies have been performed based on energy radiometry [13] and the autocorrelation of received signals [7], [14]. In addition, several studies have investigated the blind estimation of modulation parameters [15]- [18].
To recover transmitted data bits in non-cooperative communication systems, critical challenge is the estimation of a spreading sequence from a received DSSS signal. This estimation problem is extremely difficult even with the information of the data bit rate and the length of a spreading sequence. Several studies have examined the blind estimation of a spreading sequence [9], [10], [19]- [25]. In [9], a spreading sequence was estimated in a multi-path environment based on a multi-channel identification technique [26], [27]. Neural network algorithms were applied for the blind estimation of a spreading sequence in [22]- [24]. In [10] and [25], an Eigen-Value Decomposition (EVD)-based algorithm was proposed for the blind estimation of a spreading sequence. This algorithm estimates a spreading sequence based on the EVD of the autocorrelation matrix of the received signal. The EVD-based algorithm is one of the best performing algorithms for blind estimation of a spreading sequence. However, the EVD-based algorithm requires high computational complexity. Furthermore, there exists a partial-encoding problem in an asynchronous case [25]. To solve the partial-encoding problem, several modified algorithms have been proposed based on the EVD-based algorithm in [15], [28]- [30]. However, these algorithms result in increased computation complexity and performance degradation.
In non-cooperative communication systems, it is essential to blindly estimate a spreading sequence and data bits from DSSS signals at low SNR. Furthermore, for real-time processing, computational complexity should be minimized for the blind estimation. Therefore, in this paper, a novel algorithm is proposed to blindly estimate a spreading sequence and data bits based on turbo processing. With the proposed algorithm, a receiver calculates extrinsic information based on received signals and updates Log-Likelihood Ratios (LLRs), iteratively [31], [32]. Turbo processing has been applied to decoding problems, equalization, coded modulation, and joint source and channel estimation [31]- [33]. However, there has been no previous research on the blind estimation of a spreading sequence and data bits based on turbo processing.
The contributions of this paper are as follows: • A novel algorithm is proposed to simultaneously blindly estimate a spreading sequence and data bits simultaneously. This is the first approach based on turbo processing in estimating a spreading sequence for non-cooperative communication systems.
• The proposed algorithm can be implemented for both synchronous and asynchronous cases. In other words, even when the receiver does not have prior information on time synchronization, the proposed algorithm provides a method to jointly estimate a spreading sequence and data bits and to acquire time synchronization.
• The performance of the proposed algorithm is evaluated via simulations. From the simulation, it is shown that the proposed algorithm can achieve better estimation performance than that of an EVD-based algorithm. Especially, a performance gain of approximately 3.0 dB performance gain is observed in an asynchronous case.
• The computational complexity is analyzed for the proposed algorithm. As the proposed algorithm drastically reduces the number of multiplications compared with the EVD-based algorithm, it is less computationally complex.
• With the proposed algorithm, a spreading sequence is estimated without a partial-encoding problem. The remainder of this paper is organized as follows. In Section II, the system model is presented for this paper. In Section III, a novel algorithm is proposed to blindly estimate a spreading sequence and data bits. Then, simulation results are shown and discussed in Section IV. Finally, the conclusions of this paper are presented in Section V.

II. SYSTEM MODEL
In this section, a system model is presented for the proposed blind estimation algorithm. In the system, a transmitter sends a baseband DSSS signal, which is the product of data bits and a spreading sequence c = {c 1 , c 2 , · · · , c L }, where L is the length of a spreading sequence. The spreading sequence is a random binary sequence of length L and a data bit is modulated by Binary Phase Shift Keying (BPSK). It is assumed that the length of the spreading sequence is equal to spreading gain and that the spreading sequence is repeatedly used to transmit multiple data bits.
The transmitted baseband signal s(t) is expressed as where a k is the kth data bit (a k ∈ {−1, 1}), c l is the lth chip in a spreading sequence (c l ∈ {−1, 1}), T c is the chip duration of a spreading sequence (T c = T s /L), T s is the period of a data bit, and p(t) is a pulse-shaping filter.
In non-cooperative communication systems [8]- [11], a receiver does not have the information of the spreading sequence c. Therefore, in this paper, the receiver simultaneously estimates a spreading sequence c and data bits. It is assumed that the data bit period T s and the length L of a spreading sequence are known to the receiver before the blind estimation of a spreading sequence as in previous studies [9], [10], [19].
At a receiver, a received signal r(t) is expressed as where w(t) is the complex AWGN with zero mean and variance N 0 and τ is the unknown desynchronization value between the receiver and a transmitter. 1 In this paper, without loss of generality, it is assumed that τ = 0, but the receiver does not have the information of the τ value. In addition, N 0 is assumed to be known to the receiver and channel estimation is not required since the transmitted signal is a baseband signal. The received signal is sampled at a rate T c . The sampled signal z[i] can be expressed as where ζ is an arbitrary value in the rage of [0, T c ). Let us define two different types of blind estimation of a spreading sequence and data bits. One is a synchronous case, where a receiver has the information of the desynchronization value τ . The other is an asynchronous case, where the receiver does not have the information of the desynchronization value τ .
With the proposed algorithm, a spreading sequence and M spread data bits are simultaneously estimated based on an input matrix, which is constructed by sampling the received signal. The block diagram of the system is shown in Fig. 1.
Let us define y m, as follows: where (·) T is a transpose operator and denotes a time offset. Here, the time offset is the number of shifted samples to construct an input matrix. Subsequently, with the time offset , an input matrix Y is expressed as follows: The element in the kth row and the lth column of Y is denoted by y (k,l) . For a time offset , let us define a time synchronization error as the time difference between the beginning of a data bit and the first sample in an input matrix, where is a value in the range of [0, T s ). In this paper, since τ is assumed to be zero, is the same as T c . In a synchronous case, it is sufficient to consider only an input matrix Y with = 0. Then, the input matrix Y 0 is expressed as where W 0 is the noise part of the input matrix Y 0 and is expressed as where In the mth row of Y 0 , a k is multiplied with the spreading sequence c. In addition, in the lth column of Y 0 , each data bit is multiplied by the same chip c l of the spreading sequence. Then, the element in the kth row and the lth column y 0 where w 0 (k,l) is the element in the kth row and the lth column element of W 0 .
In an asynchronous case, since a receiver does not have the information of the desynchronization value, the proposed algorithm constructs L input matrices. The L input matrices are constructed from the (M + 1)L − 1 samples with L different time offsets = 0, 1, · · · , L − 1. Fig. 2 shows the construction of L input matrices from the samples for the proposed algorithm.
Therefore, for the proposed algorithm, ML and (M +1)L−1 consecutive samples are required in synchronous and asynchronous cases, respectively.
If is not zero, the input matrix Y is expressed as where W is the noise part of the Y with a time offset , and In the kth row of Y , a k is multiplied by the last L − chips in the spreading sequence and a k+1 is multiplied by the first chips in the spreading sequence due to the synchronization error.

III. PROPOSED ALGORITHM
In this section, the proposed algorithm is presented for blind estimation of a spreading sequence and data bits simultaneously. This proposed algorithm is based on the turbo processing principle for a maximum a posteriori probability decision. In the proposed algorithm, the channel LLRs of chips in a spreading sequence and those of data bits are iteratively calculated to obtain a posteriori LLRs.
At each iteration, after the channel LLRs of chips in a spreading sequence are first calculated, a priori probabilities of chips in a spreading sequence are updated with the calculated channel LLRs. Subsequently, the channel LLRs of data bits are calculated with the updated a priori probabilities of chips in a spreading sequence. Moreover, a priori probabilities of data bits are updated with the calculated channel LLRs. 2 The extrinsic information of the calculated channel LLRs is used in the next iteration.

A. LOG-LIKELIHOOD RATIO
Let us consider a synchronous case. In this case, the input matrix Y is constructed with a time offset = 0.
With a time offset , a posteriori LLR L (c l ) of c l , is defined as where and L pr (c l ) = log Pr (c l = 1) Pr (c l = −1) .
With a time offset , a posteriori LLR L(a k ) of a k is defined as 2 It is possible to change the order of the LLR calculation between chips in a spreading sequence and data bits. For convenience, in this paper, the LLR calculation of chips in a spreading sequence is followed by the LLR calculation of data bits. where u (k, ) is the kth row of Y , L ch (y (k,l) | a k ) is the channel LLR of y (k,l) for a k and L pr (a k ) is a priori LLR of a k . Here, and From (12) and (15), it is observed that a posteriori LLR of c l can be calculated with the lth column of Y and a posteriori LLR of a k can be calculated with the kth row of Y . Fig. 3 shows how to calculate a posteriori LLRs from an input matrix.
In a synchronous case, as y (k,l) is expressed as y (k,l) = a k c l + w (k,l) , the channel LLR of y (k,l) for c l is calculated as (18), shown at the bottom of the page where γ (x|y) = −x 2 +log Pr(y), Re[x] is a real part of x and the approximation (a) is obtained from [34] log[exp(x 1 ) + exp(x 2 )] ≈ max(x 1 , x 2 ).
As max(x 1 , x 2 ) is the same as (x 1 + x 2 + |x 1 − x 2 |)/2, the channel LLR of y (k,l) for c l is expressed as where sgn(x) is a sign function [31].
≈ max γ VOLUME 8, 2020 Similarly, L ch y (k,l) | a k , the channel LLR of y (k,l) for a k , can be expressed as For the turbo processing, the extrinsic information for c l and a k are denoted as λ c l and λ a k , respectively. The extrinsic information is expressed as follows where n 1 and n 2 are the smallest integer greater than or equal to log 2 M and log 2 L, respectively. 3 The extrinsic information is used to update a priori probability.

B. SYNCHRONOUS CASE
Let us consider a synchronous case, where the receiver has the information of a desynchronization value τ . Then, the aposteriori LLRs of chips in the spreading sequence L 0 (c l ) and those of data bits L 0 (a k ) are calculated from (12) and (15) for the input matrix Y 0 , respectively. At each iteration, L 0 (c l ) and L 0 (a k ) are calculated for l = 1, 2, · · · , L and k = 1, 2, · · · , M . To calculate L 0 (c l ) and L 0 (a k ), the a priori probabilities Pr(c l = 1) and Pr(a k = 1) are updated based on the extrinsic information obtained from the previous iteration. Before the first iteration, the a priori probabilities Pr(c l = 1) and Pr(a k = 1) are initialized for all l and k values. After the initialization, L 0 (c l ) is first calculated from (12). Subsequently, the extrinsic information λ 0 c l for c l is fed back to update the a priori probability of Pr(c l = 1) as follows: 3 As division by a power of two can be easily implemented by a shift operation, its computational complexity is negligible compared with a multiplication operation.  where f atv (x) is an activation function. In this paper, as in [35]- [37], a logistic function is used for the activation function. This function is expressed as [38]: where µ is a positive coefficient. Fig. 4 shows plots of the activation function (25) for different coefficient µ values. After Pr(c l = 1) is updated, L 0 (a k ) is calculated from (15). Then, the extrinsic information λ 0 a k for a k is also fed back to update the a priori probability of Pr(a k = 1) as follows: The updated a priori probabilities are used at the next iteration to calculate L 0 (c l ) and L 0 (a k ). Fig. 5 summarizes the overall iterative procedure for the proposed algorithm. After the end of the last iteration, the estimated chips in a spreading sequence and data bits are obtained based on the sign of L 0 (c l ) and L 0 (a k ) as follows:

C. ASYNCHRONOUS CASE
Let us consider an asynchronous case, where the receiver does not have the information of the desynchronization value τ . In this case, the receiver estimates a spreading sequence and data bits for all possible desynchronization values. Therefore, L input matrices are generated from the consecutive (M + 1)L − 1 samples with L time offsets .
148070 VOLUME 8, 2020 Subsequently, among the L estimations of chips in a spreading sequence and data bits, the receiver selects the most reliable one. For each time offset , the a posteriori LLRs of chips in a spreading sequence and those of data bits are calculated from (12) and (15). After the end of the last iteration for each value, tentative estimations of a spreading sequence and data bits are obtained as Then, from the tentative estimation, an input matrix Y is regenerated as The receiver computes the Euclidean distance between an input matrix Y and a regenerated input matrix Y . The computed Euclidean distance is used as a reliability measure for a tentative estimation. Let us define as the time offset , with which the minimum Euclidean distance is obtained. Then, is expressed as where y (k,l) is the kth row and the lth column element of Y .
(a) is derived as follows: (i) In the second line of (32), with i = L, L+1, · · · , ML−1, the first term (z[i]) 2 is included for all . Therefore, this term can be simplified as the first and the second terms of the third line in (32). (ii) As the value of y (k,l) is 1 or −1, ( y (k,l) ) 2 is always one for all l and k. Therefore, the final estimation of a spreading sequence and data bits can be obtained as follows: a k = a k ( ) , k = 1, 2, · · · , M .
Algorithm 1 presents the proposed algorithm as a pseudo code for an asynchronous case.

D. COMPUTATIONAL COMPLEXITY
In this subsection, the computational complexity is analyzed for the proposed algorithm. In addition, the computational complexity is compared with that of the conventional EVD-based algorithm. Let us first consider a synchronous case. The computational complexity is summarized as follows: • Normalization of an M × L input matrix by N 0 (signal-to-noise ratio normalization): -ML multiplications • Calculation of channel LLRs as in (20) and (21): -2MLN iter additions 4 • Calculation of extrinsic information based on the calculated channel LLRs as in (22) and (23): • Update of a priori probabilities using a logistic function as in (24) and (26), that can be implemented with a look-up table [39]: -(M + L)N iter memory accesses for a one-dimensional look-up table of a logistic function • Calculation of a priori LLRs similar to that in (14) and (17), which can be implemented with a look-up table: -(M +L)N iter memory accesses for an one-dimensional look-up table of a logarithm function • Calculation of a posteriori LLRs as in (12) and (15): -(M + L)N iter additions Therefore, the proposed algorithm requires approximately ML multiplications and 4N iter ML additions for the synchronous case, as the shift operation and memory access for a look-up table are negligible compared with an addition or a multiplication.
On the other hand, in the asynchronous case, the proposed algorithm requires L input matrices of size M × L obtained from (M + 1)L − 1 samples. In addition, to calculate the Euclidean distance between an input matrix Y and its regenerated matrix Y , 2L −1 multiplications and L(ML −1) additions are required. Therefore, the proposed algorithm requires (M +1)L +2L −2 multiplications and 4N iter ML 2 +L(ML −1) additions. Thus, for the asynchronous case, computational complexity is approximately L times that of the synchronous case.
For the conventional EVD-based algorithm [10], [20], [25], it is necessary to compute the average of M covariance matrices of size L × L. Subsequently, after the calculation of eigen-decomposition of the averaged covariance matrix, the spreading sequence is estimated based on two largest eigenvalues and the corresponding eigenvectors. Therefore, ML 2 +L 3 additions and ML 2 +L 3 multiplications are required for this algorithm [21], [40], [41]. With the EVD-based algorithm, almost the same computational complexity is required for both synchronous and asynchronous cases. Table 1 summarizes the computational complexity of the EVD-based algorithm and proposed algorithm in synchronous and asynchronous cases.

IV. NUMERICAL RESULT
In this section, simulation results of the proposed algorithm are presented. A simulator was built to obtain the results for the proposed algorithm in an AWGN channel. The performance of the proposed algorithm was compared with that of an EVD-based algorithm.
The estimation performances were obtained from 10,000 runs of Monte Carlo simulations for an SNR value between −20.0 dB and −10.0 dB. For the simulation, 100 data bits were spread with a spreading sequence of length 31 and the coefficient µ for an activation function is fixed to 3.0. The results were obtained after N iter iterations, where N iter is an integer in the range [1,25]. In the asynchronous cases, the desynchronization value was set to iT c , where i is an integer, uniformly distributed between 0 and L − 1. Table 2 summarizes the parameters used for the simulation. Let us define P e (x), which is an ideal BER (bit error rate) performance of BPSK for SNR of x after despreading. P e (x) is expressed as where erfc(x) is an error function and G is the processing gain [42]. As the proposed estimation algorithm cannot outperform the ideal BER P e (x), P e (x) is used as a lower bound for estimation performance. For the estimation of a data bit, as a data bit is spread by a spreading sequence of length L, G becomes L. On the other hand, for the estimation of a chip in a spreading sequence, as it can be regarded that a chip in a spreading sequence is spread by a sequence of length M , G becomes M . Fig. 6 shows the error rate versus SNR for a chip in a spreading sequence and a data bit. The solid and dashed lines represent the performances of the algorithms in synchronous and asynchronous cases, respectively. The results were obtained after 10 iterations with the proposed algorithm. Fig. 6.(a) shows the plots of the error rate of a chip in a spreading sequence for the proposed and EVD-based algorithms. In the synchronous case, for the error rate of 10 −2 , −13.9 dB and −12.6 dB are required with the proposed and EVD-based algorithms, respectively. Furthermore, in the asynchronous case, for the error rate of 10 −2 , −13.4 dB and −10.0 dB are required with the proposed and EVD-based algorithms, respectively. Compared to the EVD-based algorithm, the proposed algorithm achieves better performance with respect to chips in a spreading sequence. Particularly, in the asynchronous case, the proposed algorithm has performance gain of approximately 3.0 dB compared with the EVD-based algorithm. Fig. 6.(b) shows plots of the error rate of a data bit for a proposed and EVD-based algorithms. In the synchronous case, for the error rate of 10 −1 , −14.7 dB and −14.5 dB are required with the proposed and EVD-based algorithms, respectively. Furthermore, in the asynchronous case, for the error rate of 10 −1 , −14.4 dB and −13.6 dB are required with the proposed and EVD-based algorithms, respectively. Compared to the EVD-based algorithm. the proposed algorithm achieves better performance with respect to data bit error rate.
From the Fig. 6.(a) and Fig. 6.(b), it is evident that the estimation performance of a chip in a spreading sequence is better than that of a data bit for a fixed SNR. This is because the size of column M is smaller than that of row L with an M × L input matrix.
The proposed algorithm is based on the iterative calculations of a posteriori LLRs. Therefore, the estimation performance is dependent on the number N iter of iterations. To investigate the influence of N iter on the estimation performance, Fig. 7 shows the plots of the error rate for different N iter with the proposed algorithm. For the results, SNR is fixed at −15.0 dB. As N iter increases, the error rate of a chip in a spreading sequence converges to approximately 2.1×10 −2 or 4.2×10 −2 in a synchronous or an asynchronous case, respectively. In addition, the error rate of a data bit converges to approximately 9.8 × 10 −2 or 12.5 × 10 −2 in synchronous or asynchronous case, respectively. Fig. 7 show that the performances saturate after 10 and 20 iterations for an asynchronous and a synchronous cases, respectively. In the asynchronous case, as estimation performance degrades due to the time synchronization error, the error rate converges to a higher value compared with that in the synchronous case. Therefore, in the asynchronous case, the error rate saturates after fewer iterations than in the synchronous case.

V. CONCLUSION
In this paper, a novel algorithm is proposed to blindly estimate chips in a spreading sequence and data bits based on turbo processing principle in non-cooperative baseband communication systems. With the proposed algorithm, the a posteriori LLRs of chips in a spreading sequence and data bits are calculated and a priori probabilities are updated based on channel LLRs. The proposed algorithm can be implemented for both synchronous and asynchronous cases. Therefore, regardless of the information of a desynchronization value, chips in a spreading sequence and data bits can be estimated simultaneously. The simulation results show that the proposed algorithm can achieve better estimation performance than an EVD-based algorithm. Especially, in the asynchronous case, a performance gain of approximately 3.0 dB was achieved compared to the EVD-based algorithm to estimate the chips in a spreading sequence.
In addition, this paper analyzed the computation complexity of the proposed algorithm. The complexity of the proposed algorithm is compared with that of an EVD-based algorithm. As the proposed algorithm considerably reduced the number of multiplications required, it is less computationally complex than the EVD-based algorithm.