Scalable Modeling Approach and Robust Hardware-in-the-Loop Testing of an Optimized Interleaved Bidirectional HV DC/DC Converter for Electric Vehicle Drivetrains

Automotive Original Equipment Manufacturers (OEMs) require varying levels of functionalities and model details at different phases of the electric vehicles (EV) development process, with a trade-off between accuracy and execution time. This article proposes a scalable modelling approach depending on the multi-objective targets between model functionalities, accuracy and execution time. In this article, four different fidelity levels of modelling approaches are described based on the model functionalities, accuracy and execution time. The highest error observed between the low fidelity (LoFi) map-based model and the high fidelity (HiFi) physics-based model is 5.04%; while, the simulation time of the LoFi model is ~104 times faster than corresponding one of the HiFi model. A detailed comparison of all characteristics between multi-fidelity models is demonstrated in this paper. Furthermore, a dSPACE SCALEXIO Hardware-in-the-Loop (HiL) testbench, equipped with a minimal latency of $18\mu $ sec, is used for real-time (RT) model implementation of the EV’s HV DC/DC converter. The performance of the entire HiL setup is compared with the Model-in-the-Loop (MiL) setup and the highest RMSE is limited to 0.54 among the HiL and MiL results. Moreover, the accuracy (95.7%) of the passive component loss estimation is verified through the Finite Element Method (FEM) software model. Finally, the experimental results of a full-scale 30-kW SiC DC/DC converter prototype are presented to validate the accuracy and correlation between multi-fidelity models. It has been observed that the efficiency deviation between the hardware prototype and multi-fidelity models is less than 1.25% at full load. Furthermore, the SiC Interleaved Bidirectional Converter (IBC) prototype achieves a high efficiency of 98.4% at rated load condition.

performance and reliability of power electronic (PE) components, enhanced energy efficiency, affordability and environmental awareness of policymakers and consumers [4], [5]. To keep pace with the exponentially expanding EV-market, current research is challenged to investigate the reduction of time-to-market, cost, energy consumption, while confirming the improvement in safety and comfort [6]. These challenges demand the growth of the efficacy of the development process and testing time, leading to virtualization in the design phase. Therefore, modelling and simulation have been established as a mandatory part of virtualisation tool at the conceptual design stage in the place of physical tests, as real-time (RT) testing is a time-consuming and highly costly process [6]- [8].
Hence, accurate and scalable modelling of the EV PE components is a crucial method to achieve a highly reliable simulation tool for system characterizations, optimization, validation and performance measurement in the early design phase.

A. ISSUES IN HIGHLY ACCURATE MODEL
To accomplish the safety design functionality of the EV power electronics (PEs) components, several hundred kilometres of test data are required based on targeted vehicle type and legislation such as the New European Driving Cycle (NEDC), a European certified cycle for light-duty EV with an average speed of 33.6 km/h and having 1180s duration, the EPA Federal Test Procedure (FTP-75) and Japanese cycle (JC-08) are certified in the USA and Japan respectively, having an average speed of 34.1km/h and 24.4km/h, and duration of 1874s and 1204s [9], [10]. These tests evaluate the performance (controllability, efficiency, and ageing), safety, and manufacturability of EV components. This process involves extensive test coverage in the virtual platform, which mandates 8000 h-10000 h of the EV simulation as a set of complete life cycle requirements [11]. A detailed and accurate HiFi simulation model could slow down the whole EV simulation process as the HiFi PE component's simulation requires very small simulation step-size (1 µs or 0.1 µs) to attain highly accurate results [12]- [16]. In contrast, a standard step-size for an entire EV simulation is 0.01s [17]. When using 1 µs step size to simulate a HiFi model of an EV, approximately 15 minutes is required to perform just 1ms of simulation using a personal computer (PC) with Intel® Core i7 Processors. Hence, this PC would require approximately 52 years to simulate one complete Worldwide Harmonized Light Vehicle Test Procedure (WLTP) driving cycle.

B. SCALABLE MODELLING APPROACH
To speed up the power electronics component's simulation time, a multi-scale modelling approach is proposed as a proper solution [6], [16], [18]. Scalable modelling has consisted of High-Fidelity (HiFi) modelling, Medium-Fidelity (MFi) modelling, Low-Fidelity (LoFi) modelling, and mapbased modelling, with simulation step-sizes varying from 0.1 µs to 0.01s. As the simulation step-size are increased, there is a high chance to lose accuracy. A few functionalities need to be compromised from model to model, such as short circuit test, transition impact on voltage and current due to device turn on and off, sensitivity to duty ratio and temperature response during critical behaviour (braking/rush driving) [12], [18]. According to the model's functionalities, the HiFi model is employed for fault diagnosis and prognosis of the optimized PE converter's (PEC) semiconductor module and thermal model. The MFi model is focused on the mission-profile oriented temperature profile of all devices in the context of ageing stress and durability analysis. This modelling technique represents Design for Reliability (DfR) of the PECs in the EVs application to predict reliability and durability benchmarks. Thanks to a less accurate fast models for speeding the several EV optimization tasks and several thousands of EV driving simulation.

C. NECESSITY OF HARDWARE-IN-THE LOOP TESTING
Currently, the OEMs prefer to use Model-based-Development (MBD) techniques for PE components, which introduce HiL tests for the EVs traction subsystems [19], [20]. At the design stage, the HiL testbench can be utilized to verify the effect of the inclusion of Wide Band-Gap semiconductors (WBGs), such as Silicon-Carbide (SiC) and Gallium Nitride (GaN), in the EVs of the PE converters [19], [21]. The stress in the PE converters due to using WBGs is precisely measured using the RT-models. In addition, the RT-models can be utilized as digital-twins for predictive maintenance of the EVs components [22]. Moreover, the RT-models can be used to verify the reliability of the PE converters for different mission profiles, thus providing a guideline to estimate the PE components ageing factor [23]. Hence, an RT-model analysis can facilitate the creation of an innovative system configuration for a new class of affordable, safe and efficient EV with less scrutiny [6], [16].

D. ROLE OF THE HV DC/DC CONVERTER IN THE BEVS
The battery electric vehicles (BEVs) have multiple architectural variants. FIGURE 1 depicts a simplified block diagram of the BEV powertrain, which is the most common architecture of the BEV drivetrain, currently available on the market [24], [25].
The BEV drivetrain architecture consists of: • Rear Wheel Drive (RWD); • Electric Motor (EM); • Differential Transmission; • Optional High Voltage (HV) DC/DC Converter between Battery and Motor driver (Inverter). In the BEVs, the voltage level of the propulsion battery system is 48V-375V, which is usually lower than the required voltage of 400V-750V for the EM [26]. Therefore, high voltage (HV) DC/DC converter topologies are commonly used to interface the battery with the HV DC link in the BEVs drivetrains. The HV DC/DC converter can provide a fixed or variable DC link voltage regardless variation of the battery voltage. The DC/DC converter also allows a higher DC-link voltage than the battery voltage, as mentioned above. The higher voltage offers higher efficiency in the drive system components (such as PE and EM) and prolongs battery lifetime. Furthermore, low voltage in battery systems permit to reduce the complexity of battery packs reducing series connection of cells, increasing safety, recovering more energy during regenerative braking and finally reducing the cost of the battery system. Disadvantages include higher costs and losses from the converter itself [26], [27]. In the BEVs, the HV DC/DC converter needs to support bidirectional power flow while ensuring efficient energy conversion and provides a variable DC link optimizing the inverter efficiency according to the operating modes. In the propulsion mode, energy flows from the battery to the motor load, while in regenerative braking mode, the momentum of the vehicle enables the EM to act as a generator, transferring the energy back to the battery.

E. AUTOMOTIVE HV DC/DC CONVERTER'S RESEARCH TRENDS
In recent years, several bidirectional HV DC/DC converter topologies have been studied and designed for the BEV applications such as Synchronous Boost Converter (SBC) [27], Resonant Boost Converter (RBC) [28], Full-Bridge Converter (FC) [27], ZVS-Boost converter (ZBC) [29], Multidevice Interleaved Boost Converter (MDIBC) [30], Multiport converter (MPC) [31], and 3-Phase Interleaved Bidirectional Converter (IBC) [32]. Each topology has its own advantages and drawbacks and should be chosen based on the functionalities, requirements, efficiency, component count, controllability, compactness, cost and reliability [26]. For the high-power BEV a standard 3-phase IBC topology has been proposed in [4], [22], [26], [31]- [37], thanks to its less device current stress, simple controllability, compact design, high power-density, better efficiency and high reliability. Numerous articles have been published on the HV DC/DC converter for the EVs applications. On the one hand, the MDIBC presented in [30], [38], depicts a converter topology and operation with average losses of converter at rated load, digital control technique and hardware-prototype. In [39], a detailed structure of a 4-Phase IBC is presented, together with an advanced control technique and experimental results. In [31], a suitable MPC topology, an optimization process and an average losses model is proposed. On the other hand, authors in [40], describe a 2-phase IBC with a detailed DSPbased controller and verified results with a 1 kW and 120 V hardware prototype. Additionally, a 6-phase interleaved FC is proposed in [41], it describes a detailed HiL setup for the HV DC/DC converter in Class 3 vehicle system and illustrated advantages of the inclusion the converter in the EVs. A 3-phase DC multifunctional converter is presented in [35], considering the functionality of the topology, the control scheme and the average losses contribution of the semiconductor modules. Finally, a time-efficient electro-thermal model of a 3-phase IBC is presented in [42].

F. CONTRIBUTIONS OF THIS ARTICLE
None of these publications in [26]- [44], discussed converter's optimization processes with detailed modelling issues such as universal switch model, instantaneous loss profile of power device and passive components (inductor and capacitor) and liquid-cooling thermal modelling for dynamic BEV simulation.
The unique scalable modelling approach presented in this article will guide the non-power electronics users (OEMs/ end users) to select the appropriate fidelity based on the testing purpose and development objectives of the BEVs as the short circuit testing in the semiconductor module or the energy consumption and the thermal consumption routine optimization of several hundred km of the EV's driving do not required the same level of functionalities, accuracy and speed.
While most of the publications usually present a single semiconductor technology modelling as Silicon [30], [37] or Silicon Carbide (SiC) [15], [43]- [45], this article depicts a universal modelling technique for interchangeable semiconductor technologies and evaluates the superiority of utilizing the WBGs in the DC/DC converter topology in terms of power losses and efficiency.
Moreover, this article presents a detailed HiL model preparation method with a low latency of 18µsec, which could be utilized by all the automotive power electronics engineers to attain acceptable accuracy in comparison with a model-inthe-loop (MiL) model.

G. ARTICLE ORGANIZATION
This article is structured as follows. Section II depicts the converter structure, system specifications and optimization methodology of the converter to meet the system design objectives. Section III presents the detailed electrical behaviour modelling technique of the semiconductor devices, including switch and diode. Section IV describes a comprehensive thermal behaviour modelling approach of the semiconductor devices. Section V shows 1D and 3D modelling and losses estimation techniques of the passive components (inductor and capacitor). Section VI describes the robust RTmodelling method for HiL setup using a minimal sampling rate. Afterward, section VII analyses scalability approaches of the multi-fidelity models. Section VIII illustrates the experimental results of a full-scale 30-kW SiC-based IBC prototype. Section IX presents the comparison between HiL and MiL results and shows performance comparison among multi-fidelity models characteristics. In addition, the accuracy of the passive components losses and IBC efficiency are compared. The conclusions and recommendations are presented in Section X.  Ideal-topology structure of the 2 level 3-phase IBC (with interleaved phase current I LRST and phase voltage V LRST , V bat , six switches and antiparallel diodes, V bus and I Dc are highlighted). Equivalent series resistance (ESR) of the capacitor R C and internal resistance of interleaved inductors R L are also highlighted. Here, V bat is the battery voltage, V bus is regulated DC-link voltage and it is connected to the EM through a 3-phase motor drive named as DC/AC converter. FIGURE 2 depicts the topology structure of the IBC, which comprises six power switches and six antiparallel diodes: T R1 -D R1 , T R2 -D R2 , T S1 -D S1 , T S2 -D S2 , T T1 -D T1 , T T2 -D T2 ; three interleaved inductors L 1 , L 2 and L 3 ; a DC-Link capacitor C and input side capacitor C L .
The limited driving range has constrained growth in the EVs applications in the past decade. Hence, regenerative braking (RB) has been developed as the most appropriate approach for extending the driving range of EVs. Using the RB of the EVs, kinetic energy can be converted into electrical energy in the EM, which charges the battery. The transfer of electrical energy from the EM to the battery requires a converter. For converting load voltage from 400V-750V to 240V-375V, a buck converter is required. As the battery is recharged through the RB, the battery state-ofcharge (SoC) increases, which expands the battery lifetime. Besides, the maximum battery charging current is kept limited, even during the maximum power period of the EM, to ensure the battery protection from the large charging current. The detailed operational mode of the IBC is discussed below.

A. MODES OF OPERATION
In the propulsion mode, the IBC operates as a boost converter and the energy flows from the battery to the EM. During this mode T R2 , T S2 and T T2 are used as primary switches, which are alternately switched on or off at the switching frequency f sw , while switches T R1 , T S1 and T T1 remain switched off. When T R2 , T S2 and T T2 are switched on, the current in the inductors increase and store energy by creating a magnetic field. When T R2 , T S2 and T T2 are switched off, the current of the inductor flows through the free-wheeling diode D R1 , D S1 and D T1 . In the RB mode, the IBC operates as a buck converter and energy flows from the EM to the battery, thus allowing the battery to recapture some of the braking energy. During this mode, T R1 , T S1 and T T1 are used as primary switches, which are alternatively switched on or off at the switching frequency f sw , while switches T R2 , T S2 and T T2 remain switched off. When T R1 , T S1 and T T1 are switched on, the inductor current flows linearly from the EM to the battery. When T R1 , T S1 and T T1 are switched off, the current of the inductor flows through the free-wheeling diode D R2 , D S2 and D T2 .
The L R inductor stores energy in both modes of the IBC operation when T R1 or T R2 is switched off, the L S inductor stores energy when T S1 or T S2 is switched off, and the L T inductor stores energy when T T1 or T T2 is switched off. Such inductors operate in propulsion mode as the boost inductors and the braking mode as low-pass filter inductors. The DC-link capacitor and C L act as the energy buffer for smoothing.
The phase shift between interleaved phase switches is 120 • , which reduces the ripple current flowing into these inductors for acceptable ripple voltages on both the DC-link side and the battery side. In addition, this interleaving technique allows the IBC to work at reduced power due to the failure of parallel strings of the battery cells. Hence, in the EVs, the IBC modularity helps the EM to function even under cell-defective conditions, prolonging BEVs' lifespan.

B. SYSTEM SPECIFICATIONS
A light-duty commercial BEVs' battery specifications and initial parameters are selected as the target specifications. The boundary value condition for the IBC has been chosen based on the design target. The specifications and initial design parameters are shown in TABLE 1.

C. DESIGN OPTIMIZATION OF THE CONVERTER
The IBC's design parameters are shown in Table 2, which is formulated using a Multi-Objective Genetic Algorithm (MOGA) Optimization tool to achieve highefficiency and high power density while meeting the specifications and initial design parameters of the system as shown in TABLE 1.
This subsection shows, in chronological order, the steps followed in the optimization tool: a. First, the objective functions for the optimization process are identified in equation (1): b. Then, all degrees of freedom (DoF) and constraints in the converter designing process are categorized as per equation (2). Afterward, lower, and upper bound values Purple points indicate Pareto optimal solutions of the multi-objective optimization and red mark denotes the optimal global solution. Where the total inductor weight is 2.4kg/phase, the ripple current is 3.8A/phase and the average converter loss is 432W (∼98.5% η at full load).
have been selected to generate meaningful results for each DoF. [Constraints] c. Non-dominated Sorting Genetic Algorithm-II (NSGA-II) [46] is utilized to solve the non-convex and mixed-integer multi-objective optimization problem in (1). The presence of multiple objectives in a problem results in a set of Pareto-optimal solutions, as shown in FIGURE 3. d. Finally, the average ranking method (AR) is used to obtain the most appropriate solution [47] from the set of Pareto-fronts for the above-mentioned system specifications and constraints. The optimal solution is coloured as a red point in FIGURE 3. The optimal value for the number of phases (N ph_min ), switching frequency (f sw_min ), the inductance value (L ph_min ), and the capacitance value (C DC_Link_min ) are obtained to fulfill the system functional requirements using the developed MOGA optimization tool, whose detailed method is derived in [31].

III. SEMICONDUCTORS: ELECTRICAL BEHAVIOUR MODELLING
As described previously, the semiconductors (three pairs of controlled switches and their antiparallel diodes) allow controlling the transferred power in both buck and boost modes of the DC-DC converter. These semiconductors are modelled in this work considering the following physical phenomena, according to the description of [16]: • Conduction behaviour; • Switching power losses; • Blocking behaviour; • Thermal behaviour. To develop a fast simulation tool, a model based on the universal losses model has been implemented, which is named as the 3 rd approach in [46].  The universal losses model comprises the decoupling of the conduction and the switching losses of the semiconductor. The semiconductor is modelled as electrically ideal as shown in FIGURE 4 and the power losses are calculated in parallel considering the obtained ideal current and voltage waveforms.
In the first term, the conduction model requires identifying which semiconductor is conducting, considering the topology of the converter, and depending on the instantaneous current and gate commands of this branch's active switches (gTx). The switching model relies on the identification of the instantaneous conducting semiconductors, i.e. identifying the semiconductors which are switched on and off in each transition. Once the conductive semiconductors are identified, a voltage drop is calculated between their terminals and thus the losses of the conductions are estimated using instantaneous losses (Psw, on, Psw, off), shown in FIGURE 4, according to the ideal waveforms of current and voltage involved.
In terms of the blocking behaviour of the semiconductors, the losses produced during the blocking state can be considered negligible compared to conduction or switching losses. Modelling a specific blocking model could only be worthwhile for a few particular working conditions, such as standby operation. Thus, ideal blocking behaviour (null current conduction during off state) has been considered for most of the developed fidelity models. The blocking behaviour has only been implemented in the Simscape Multibody based high-accuracy HiFi model, because it requires a real physical behaviour (a several megaohms resistor has been considered), but the resultant blocking current and losses are negligible.

A. CONDUCTION LOSSES MODEL
The conduction losses of any semiconductor is usually calculated as the sum of a threshold voltage drop (V th ) and an on-resistance (R on ) voltage drop because of its simplicity and relative accuracy, as shown in FIGURE 5 [48]. Present modelling tools allow implementing more accurate models efficiently utilizing multi-dimensional lookup tables (LuT), which simplify the coupling between different variables such  as voltage, current and temperature, in exchange for a slightly higher computational cost.
Taking into account the accuracy and computational cost requirements of a given application, different modelling approaches can be defined, as described in [16], from the most accurate current-and-temperature-dependent LuT-based conduction model to an ideal (null losses) conduction model.
For this work, a 2D-LuT based conduction model, as shown in FIGURE 6, in which the voltage drop produced during conduction (V d ) depends on the conducted current and the junction temperature is considered. The instantaneous voltage applied to the inductance of each interleaved phase depends on the voltage drops of the conducting semiconductors in that phase. The conduction losses are modelled according to the voltage drop by means of equation (3).
Different accuracy levels can be achieved regarding the conduction losses depending on the model chosen for the voltage drop, as explained in [16]. As the voltage drop model for this work is based on a 2D-LuT, which couples the current and temperature dependence, the conduction losses are modelled according to equation (4).

B. SWITCHING LOSSES MODEL
As described previously, the universal losses model [12], [49]- [51] simplifies the switching transitions considering them ideal in electrical terms, thus avoiding the coexistence of current and voltage that would notoriously increase the complexity and computational cost of the model. The power losses produced in each transition are added afterwards as instantaneous energy losses (E sw,on , E sw,off ), distributed along a switching step time T s equation (5), depending on the immediately prior and immediately subsequent ideal voltage and current values.
The switching losses can be estimated by means of different approaches (ideal, analytical method, LuTs, etc.), as described in [16]. For this work, the most detailed model based on 3D-LuT is chosen, which considers the coupling of conducted current, blocking voltage and junction temperature, as shown in equations (6)-(7).
where E sw,on,3D−LuT (I , V , T j ) and E sw,off ,3D−LuT (I , V , T j ) refer to the current, voltage and junction temperature dependent on and off energy losses respectively as shown in FIG-URE 7. The data to feed the LuT can be obtained from the datasheet or specific double pulse tests (DPT) performed on the semiconductors.

IV. SEMICONDUCTORS: THERMAL BEHAVIOUR MODELLING
The modelling variants of the semiconductors' electrical behaviour previously described, consider the coupling of the junction temperature with the current and voltage dependence. In order to obtain a junction temperature coupled to the instantaneous power losses, the thermal model of each semiconductor consisting of junction-to-case (Z th,j−c ), caseto-heatsink (Z th,c−s ) and heatsink-to-coolant (Z th,s−a ) models need to be implemented.

A. JUNCTION-TO-CASE THERMAL MODEL
The physical structure of a semiconductor's thermal model is usually represented as a cascaded RC network [12]. Although the Cauer model represents the real physical behaviour of materials inside each thermal layer, it results in a complex model. Therefore, Foster networks are usually preferred [52], as shown in FIGURE 8. The Foster network RC stages do not represent any physical layer; however, it can be provided with a model that mathematically behaves like a Cauer model with reduced complexity while it retains the accuracy.   Although different accuracy approaches can be implemented to model the thermal behaviour following the guidelines presented for the inverter in [16], among the different variants, the most accurate individual 5-stage thermal model is chosen for this work. A 5-stage thermal model is good enough for accurate approximation of the foster network.
This model consists of 5 cascaded RC Foster stages. Foster network simplicity lies in the fact that each RC stage can be transformed into a first-order transfer function, as depicted in FIGURE 9 and equation (8), which can easily be implemented in an equation-based simulator, illustrated in FIGURE 10. The sum of the temperature drop of each RC  stage represents the junction-to-case temperature difference, where their input is the semiconductor's power loss and their output the temperature drop.
The parameters of each RC Foster network are obtained from the thermal impedance (junction-case) curve provided by the manufacturer using a single pulse test. The time (x-axis of FIGURE 12) and thermal impedance (y-axis of FIGURE 12) data from the datasheet curves are taken as input in the Curve fit tool of MATLAB®. Afterward, a coherent curve fitting technique is employed to estimate Rth,i and C th,i parameters of the desired RC Foster pairs [12], [52]. Time constant τ th can be found via equation (9): The thermal model developed for a single semiconductor can be extended to the 2-level 3-phase IBC as depicted in FIG-URE 11, and it is accordingly implemented in the Simulink model by linking the transfer function blocks of FIGURE 8 corresponding to each semiconductor. The dynamic junction temperature can be calculated by using equations (10)- (12): T JS = P n Z th(jC)n (11) where T jn is the junction temperature, T JC is the junction to the case temperature drop, Z th(jC) is the junction to case thermal impedance and P n is the power losses of n th MOSFET or diode in the converter, R th,1−5 and τ th,1−5 are parameters of 5 stage foster network.

B. CASE-TO-HEATSINK THERMAL MODEL
Thermal grease is considered as the case to heatsink material. Again, the RC parameters of thermal grease are determined from vendor datasheet using the Curve fit tool of the MAT-LAB®. The separate switch and diode power losses merge into the case and flow into the heatsink and dissipate to the coolant. The case-to-heatsink temperature can be represented by equations (13)- (15). where T ch is the case temperature, T ch is case-to-heatsink temperature drop, Z th(ch) is the case thermal impedance, R (ch) is the grease thermal resistance and P Total is the total power losses of MOSFET and diode in each switch module.

C. HEATSINK-TO-COOLANT THERMAL MODEL
Modelling an accurate heatsink-to-coolant thermal behaviour is a complex task since it is highly dependent on the mechanical setup of the heat exchanger and the cooling parameters such as coolant flow rate (l/min) and inlet coolant temperature. As explained in [16], two Foster stages model is implemented by following the example described in SEMIKRON's SKiiP1814 GB17E4-3DUW stack and can be formulated as equation (16).
Here, R th,ha,1 , R th,ha,2 τ th,ha,1 and τ th,ha,2 represent the thermal parameters of the two Foster networks, and unlike the semiconductors' R th and τ th values, these parameters should be varied depending on the coolant flow rate and inlet coolant temperature. These variations can easily be implemented by means of LuT. The heatsink to coolant output temperature can be expressed as equations (17)- (18): T ha = Z th(ha) P Total,con (18) where T ha is the heatsink-to-coolant temperature, T ha is heatsink-to-coolant temperature drop, and Z th(ha) is the heatsink thermal impedance, P Total,conv is the total power losses of in the IBC.
The electro-thermal model of the HV DC-DC converter permits the coupling of the electrical losses output with the thermal circuit. The electro-thermal coupling allows accurate power losses to be obtained based on the electrical switching pattern and the junction temperature. A mission profile oriented stepwise modelling method of the IBC for the BEVs applications is depicted in FIGURE 13.

V. PASSIVE COMPONENTS MODELLING
The optimized values of inductance and capacitance have been selected based on the MOGA tool, as mentioned in Section-II. The goal of this section is to model highperformance inductors having high relative permeability with low eddy current using the available data of the vendors and estimating inductor loss accurately. As for the DC-link capacitor, it is selected with low equivalent series resistance (ESR) to reduce ripples and temperature rise in output voltage. Estimation of ESR is considered during the capacitor loss estimation.

A. INDUCTOR MODELLING IN 3D-FEM
A 3D-FEM model has been utilized to simulate the designed inductor. A second-order polynomial fitting function is used to find the inductance value in terms of airgaps and the number of turns, as shown in FIGURE 14(a).
The FEM simulation is also used to verify the optimal inductance value. The losses distribution in the inductor also simulated using FEM and the losses were highly localized on the edges of the core. The accuracy of the FEM losses compared to simulation losses is discussed in Section-IX. FIGURE 14(b) shows the FEM result of the flux density distribution and current distribution in the inductor.

B. ESR ESTIMATION FOR CAPACITOR MODELLING
A function is used for capacitor selection based on Equivalent Series Resistance (ESR) as equation (19).
where R 0 = resistance of foil, tabs, and terminals ( ), R 1 = resistance of electrolyte ( ), R 2 = dielectric loss resistance ( ), C 2 = dielectric loss capacitance (F), f = frequency (Hz). In according to system specification for maximum 75kW power ratings, type 947C and type 947D polypropylene DC link capacitors from Cornell Dubilier are analysed. After comparing both types, type 947C has been selected since it offered decidedly smaller ESR, the high capacitance per volume and low voltage ripples and temperature rise. The comparison of ESR as a function of frequency and temperature is shown in FIGURE 15, which ensures optimum response of type 947C capacitor at the same capacitance level.

C. LOSSES MODELLING OF PASSIVE COMPONENTS
The inductor loss is comprised of core loss P fe , air-gap loss P gp and copper loss P cu . Rectangular HF 299 Litz wire is used to wire the inductor. The inductor copper loss P cu can be calculated as equation (20): where R Lz is the resistance of Litz wire and I L,RMS is the rootmean-square current of the inductors. The Improved Generalized Steinmetz Equation (IGSE) is used to estimate the core losses and gap losses of the inductor as equations (21)-(23), where SE parameters are taken into consideration. The parameters are accumulated from the vendor datasheet.
where W t is the weight of the core material, k ns and k are the loss coefficients for non-sinusoidal waveform and C-shaped core material, f sw is the switching frequency, B max is the maximum flux-swing at the rated condition, x and y are core material parameters, k g is the coefficient for gap loss, c is the core depth factor, l g is the air-gap coefficient, N is the number of turns, F is the core packaging factor, I is the current ripple, lg is the total gap length, MPL is the mean path length in cm, and µ m is the material characteristics.
The expression for calculating DC-link capacitor losses is obtained from equation (24), where I C,RMS is the rootmean-square current value of the DC-link capacitor and ESR is capacitor equivalent series resistance, which is frequency depended shown in FIGURE 15.

VI. THE IBC HIL TESTBENCH DEVELOPMENT
Standard modelling procedures are used by OEMs to reduce the time, cost, and risk associated with the full-scale testing of products. For that, model verification-based HiL has become a fundamental methodology used to make engineering predictions with confidence that can be quantified [41]. The HiL test consists of a type of RT simulation that verifies the modelling and the control system strategy of dedicated hardware that is often in the development stage [53]. For power electronics systems, RT simulation is used as a step in the engineering process, either to validate the RT compatibility of models or to connect preliminary physical hardware to an RT digital control model to prove data compatibility [54]. The general structure used to evaluate a system model into an RT platform is presented in FIGURE 16. The RT processing units, such as SCALEXIO is often composed of several different cores allowing parallel executions of simulation models to speed up simulations. To use this capability, the initial model must be split into as many submodules as available cores. Hence, a four-core SCALEXIO system is used for the HiL setup, and three cores are available for the execution of the simulation, while one core is dedicated to the management of the service overhead. To ensure the consistency, the equal number of execution tasks are assigned to a specific core of the RT processing unit. Please refer to the appendix to see the specifications of the RT hardware used in this paper.

A. HIL MODELLING PROCESS
In order to go from an initial model running in MATLAB-Simulink environment to an RT application correctly executed in SCALEXIO, several steps must be performed in the correct order. The RT system designing procedure is divided into three main parts: • Initial Model Partitioning: describes how to partition the initial model into several parts in the Simulink® environment and then creates new independent models from the initial model with standardized interfaces utilizing dedicated dSPACE RT blocks. • Partitioned Model Execution: describes briefly how to use ControlDesk for measuring the correct real-time execution of the partitioned model. By using the dSPACE application library, it will automatically create the three new independent models with RT interfaces ready for compilation. After compilation of the Simulink model, the application is moved to the dSPACE environment and ConfigurationDesk handles the rest of the process. In ConfigurationDesk, a few more steps are performed before the simulation is sent to the RT platform. First, the machine code is flashed into the RT target memory, then the system description file of the application is loaded to the cores in the RT target; afterward, the description of the variable for each of the three models is initialized.
Finally, when the entire setup is ready, the RT test can be carried out, the subsequent considerations are as follows:

B. VEHICLE DYNAMICS MEASUREMENT
An M1 segment EV RT-measurement is used in this HiL testing. The specifications of the vehicle parameters are shown in TABLE 3 and these parameters have remained constant throughout the test.

C. CURRENT PROFILE
The current profile requested on the input side of IBC lasts 1800s. It corresponds to the different characteristics that the vehicle exhibits, including its mass, drag coefficient, rolling resistance and acceleration during the WLTP cycle.

D. BATTERY PACK VOLTAGE
Currently, the battery pack voltage level in HiL testbench consider the worst-case scenario. IBC is tested for the minimum voltage level of the M1 segment vehicle.

E. HIL RESULT ANALYSIS
For analysing the correct execution of the IBC model in the RT target with the given load, the main timing parameters to be checked are:''Task Turnaround Time,'' which indicates the fastest execution time, and ''Overrun Count'', which depicts the number of times the RT target failed to finish execution within a specific timeframe. The test is executed directly in a multi-core configuration since the performance is slightly enhanced using this method.
The result for power demand load current for the IBC is shown in FIGURE 17(a). The total power losses of the IBC and semiconductor losses of the IBC are shown The computation effort is quantified in TABLE 4 and  TABLE 5. As can be understood from the tables that the model performance is satisfactory on a periodic task of 18µs, though some overruns occur on the execution of the thermal calculation block. However, these overruns mainly occur during model initialization and do not affect normal operation. It can be seen from FIGURE 17 that the total simulation time required for the RT platform is approximately 9 hours (∼32378 s).
It is worth noting that for long homologation tests such as WLTP or NEDC (used in automotive application), simulation using a PC or laptop will be unfeasible because of the high  computational time needed and are only possible using an RT testbench such as dSPACE.

VII. MODEL SCALABILITY
There are different levels of fidelity that can be used during simulations involving models of semiconductor-based power electronics systems, which allow the users to adjust to their desired accuracy versus computation cost requirements. While highly accurate models are required to gain critical insights for some cases, during other times, faster simulation speed is desired. To account for such necessities, different scalable levels of model fidelity are designed. The detailed scalable modelling approach is shown in FIGURE 18.

A. HIGH-FIDELITY (HiFi) MODEL
A high-fidelity model is the most accurate simulation of a physical system, often at the cost of enormous computing resources. It models the physical parameters, including the electrical, thermal, mechanical aspects of a system, and often is a highly specific model. For example, a HiFi model can be used to simulate the most detailed electrical phenomena, such as short circuits and other failure situations. In MATLAB/Simulink®, the HiFi models are based on the physical Simscape Multibody library. The disadvantage of the HiFi model is the enormous simulation time required just to simulate brief instances of the real system, for example, ∼25 hours of simulation time needed to simulate 0.1 seconds of a PE system.

B. MEDIUM-FIDELITY (MFi) MODEL
To overcome the shortcoming of the HiFi model, a minimal amount of accuracy is traded off to get computationally faster simulation using the medium-fidelity model. The MFi model replaces the physics behind a system with equations describing whichever phenomena are being investigated. Since every single physical aspect is not modelled, the simulation speed increases; this allows users to simulate long periods to detect trends, instead of mere seconds allowed by the HiFi model. In MATLAB/Simulink, the MFi models are based on the Simulink® common blocks. The MFi models provide the same input and output fidelity as a HiFi model, as shown in [6], [18].

C. LOW-FIDELITY (LoFi) MODEL
The low-fidelity model is implemented by averaging techniques, considering only the fundamental harmonic, and thus neglecting the switching behaviour of the converter, as described in [16], [18]. These modelling approaches provide essential improvements in computational cost, which could allow working in real-time (HiL platforms, embedded control systems) or faster than real-time platforms (for long-term simulations) while they keep acceptable accuracy levels. Often only the first and second-order dynamic equations are modelled, and the simulation time step is much more significant compared to MFi or HiFi model.

D. MAP-BASED MODEL
The map-based models could be other alternatives tailored to improving the computational cost. The map-based model is described in this paper comprises determining all possible operating conditions of a converter and obtaining detailed losses in each of them and generating a multi-dimensional LuT that can be easily accessed to interpolate instant losses based on immediate operating conditions. Finally, the scalability approach in terms of modelling technique and platforms, compatibilities and characteristics are summed up in TABLE 6. Based on the specific use cases, the OEMs must benchmark the workflow and type of modelling required for the EVs applications. The detailed performance analysis and accuracy comparison of the scalable models are illustrated in section IX.

VIII. EXPERIMENTAL RESULTS
The SiC-based IBC hardware parameters are presented in TABLE 2. FIGURE 19 shows the experimental setup for the IBC performance validation. A programmable bidirectional EV battery emulator (1000V, 2 × 80kW) is used as a power supply for the IBC. Furthermore, the output is connected to a dynamic resistance-based load, which can be varied from 3 kW to 30kW. A Xilinx Kintex-7 XC7K325T, an FPGA programming board in dSPACE MicroLabBox, is utilized to implement a discrete control strategy for the inner inductor current loop and outer output voltage loop. Life energy motion (LEM) current and voltage sensors are used for measuring feedback signals. Furthermore, a FLIR thermal camera is used to monitor the thermal profile of the IBC, and a YOKOGAWA WT1806E power analyser is used to monitor both inputs and outputs of the IBC to determine its efficiency. . Experimental setup of the SiC-based IBC, bidirectional power is supplied by the Digatron EVT module (1000V, 2 × 80kW), liquid-cooling thermal is processed through the chiller, FLIR thermal camera is used to observe the thermal distribution and YOKOGAWA WT1806E power analyser is used to measure the IBC efficiency and variable RLoad (3kW-30kW).
In the IBC, the current controller bandwidth is designed at 3kHz, while the voltage controller bandwidth is maintained at 300 Hz. The interleaved inductor's current response of the IBC, operating in the boost mode for V BAT of 200V, V 0 of 385V and load power of 27kW, is shown in FIGURE 20(a), while FIGURE 20(b) shows interleaved current response for V o of 395V, V BAT of 200V and load power of 22kW and operating at buck mode. The interleaved inductor current response of the RT system validates the susceptibility of controller design at ∼60kHz switching frequency in bidirectional mode.
The efficiency is obtained for the SiC IBC at different load variations from 10% to 100% for a V in of 200V, V o of 385V and f sw of 60kHz is illustrated in FIGURE 21. The highest IBC efficiency is obtained 98.4% at 26.5kW by exploiting a YOKOGAWA WT1806E precision power analyser (analyser accuracy ∼0.02%).

A. SCALABLE MODELS COMPARISON
In order to compare the model accuracy between multifidelity models, an operating condition has been chosen as presented in   comparison between the multi-fidelity models, the HiFi model response is not considered.

1) ELECTRICAL CHARACTERISTICS COMPARISON
For electrical characteristics comparison, the output load varies from 30kW to 40kW; the battery voltage changes from 250V to 325V and buck mode is tested at −30kW load condition.   responses during load variation, battery voltage variation and mode change operation; however, as can be seen from the plots, the LoFi and Map-based models give an average output (or filtered) of the MFi outputs, which accurately models the transients.
2) ELECTRICAL LOSSES COMPARISON FIGURE 23 (a) depicts the switching losses comparison among the MFi and LoFi models in the steady-state condition. For a fair comparison, the average MFi waveform is plotted. It can be seen from the FIGURE 23(a) that the average MFi switching losses is coinciding with the LoFi switching losses in steady sates and the mean percentage error (MPE) between these two switching losses models is 3.25%. The MPE formula is shown in the appendix. accuracy between the average MFi switching losses and the LoFi switching losses in transient condition. It should be pointed out that the MPE between these two switching losses models is 1.25%. FIGURE 24 (a) depicts the switching losses comparison between the MFi and LoFi models in the steady-state condition. It can be seen from the FIGURE 24 (a) that the average MFi switching losses is highly correlated to the LoFi switching losses in steady sates and the MPE between these two switching losses models is 0.15%. FIGURE 24 (b) similarly depicts a high correlation between the average MFi switching losses and the LoFi switching losses in transient and the MPE between these two switching losses models is 0.25%.

3) ACCURACY COMPARISON
The HiFi model is considered as an ideal model with 0% error. The MPE has been considered for the accuracy measurement between multi-fidelity models and calculated as percentage deviation between the HiFi model output and the output of another fidelity level. A maximum of 5% error has been found between the less accurate map-based model and HiFi model for total average power losses estimation. In contrast, there is a very high 99.75% accuracy is found between the HiFi and the MFi models' response. The highest MPE for junction temperature measurement is 0.61%, 4.65% for the average DC-link voltage response, and 2.50% for the interleaved   inductors current analysis. The accuracy of the multi-fidelity modelling approaches of the IBC is illustrated in TABLE 8.

4) SPEED COMPARISON
It can be viewed from TABLE 9 that the HiFi model is considerably slower than the RT model. The HiFi simulation model requires 90720sec to simulate just 0.1sec. Moreover, the HFi model failed to run in the HiL setup. The MFi model  The simulation speed between different fidelity of models is demonstrated in TABLE 9.

B. PERFORMANCE VALIDATION IN THE HiL SETUP
To verify the HiL testbench results, MiL simulation model has been selected, which is an equation based MFi model in Simulink. The same generic base vehicle model, as depicted in TABLE 3 and real-life mission profile WLTP has been taken into consideration for the MiL simulation test. For performance validation, one lap of the IDIADA's dynamic track has been selected as a load test scenario. This dynamic track has a length of 23 km, with highly varying slopes and altitudes. For the validation of the performance between the HiL and the MiL model, a standard statistical method rootmean-square-error (RMSE) is utilized, as shown in appendix. The comparison has been evaluated for three essential characteristics of the converter, which are total power losses of the IBC, battery current (output current of the converter) and DC-link current (load power/DC-link voltage). FIGURE 25 shows an excellent accuracy between the HiL and the MiL model performances as the highest RMSE is limited to within 0.54 for IBC power losses during the 1800 seconds of dynamic mission-profile. Since the highest RMSEis less than 1, it indicates high degree of correlation between the MiL and the HiL setup performace.

C. INDUCTOR LOSS VALIDATION IN FEM
A comparison of the inductor loss among the 1D simulation model and the 3D FEM model is depicted in FIGURE 26. A high accuracy has been achieved in the simulation loss model in comparison to FEM loss results. In case of switching frequency variation from 40kHz to 100kHz, the maximum error of around 4.3% is obtained at 100 kHz. The error is caused due to the high fringing fields near to the air gap created during high switching frequency, which is difficult to consider in analytical calculation. In case of battery voltage variation from 200V to 350V, the maximum error of around 2.7% is obtained at 200V. The error was high at the lower voltage input as high inductor current and high inductor ripple current limit the accuracy.

D. EFFICIENCY VALIDATION WITH THE PROTOTYPE
The experimental measured efficiency, as shown in FIGURE 27, is plotted with 1.25% error bar to present the measurement uncertainties. It can be seen from FIGURE 27 that the maximum MPE for efficiency estimation among multi-fidelity models is less than 1.2%. The largest MPE of 0.2% is found in the HiFi model concerning the experimental measured result, 0.45% in the MFi model, and 1.11% in the LoFi model. The maximum deviation between the simulation and experimental results is obtained at full load condition due to the PCB losses, thermal interface material (TIM) losses and sensor errors, which are not taken into consideration in the analytical models.
TABLE 10 is depicted the comparison regarding the maximum error in efficiency estimation among the multi-fidelity models developed in this paper and models mentioned in the literature. The comparison considers the maximum MPE in the efficiency estimation and the capability of a standard driving cycle simulation.

E. PERFORMANCE COMPARISON BETWEEN SiC & SI
To ensure the superiority of the WBG semiconductor switches over Si, the IBC is assessed to measure the converter losses and efficiency. The most important benefit of replacing the Si IGBT with SiC MOSFET is the reduction in the semiconductor losses around 63.3% at 20kW load, as shown in FIGURE 28 (a). The losses are calculated for Si at 20kHz frequency, whereas for SiC 60kHz frequency is used. Usually, a Si IGBT takes a long time to turn off due to its characteristic tail current, which increases turnoff losses in the IGBT module. The SiC MOSFETs have no minority carriers and thus no tail current, so their turnoff losses are significantly reduced (typically six times lower than an IGBT).
Moreover, the SiC MOSFETs significantly reduce conduction losses and have extremely low reverse recovery losses. The comparison of power losses is shown in FIGURE 28(b) and the total losses breakdown of the IBC is shown in FIGURE 28(c). It can be seen that the semiconductor losses contribution is high around 75% of total losses in case of Sibased IBC, which is reduced comprehensively around 43% of total losses in the SiC-based IBC even at the higher switching frequency. The low power losses of the SiC MOSFET could be improved the efficiency of the overall system, decreased weight, and size, reduced thermal stress and cooling. Hence, the WBG semiconductors allow the use of more-compact heat sinks and supports higher operating temperatures.

X. CONCLUSION
In this paper, a unique scalable modelling concept is presented for the high voltage interleaved bidirectional DC/DC converter to support different stages of the EVs development in a virtual world. The scalable modelling approach is depicted and validated with a full-scale hardware prototype. The maximum MPE of around 0.2% is attained between the experimental measured efficiency and the HiFi model efficiency due to load changes from 10%-100%. The highest efficiency error among hardware and scalable models is restricted to within 1.2%. Furthermore, multi-fidelity models are compared to observe the accuracy and speed between scalable models. The highest MPE is found to be 5.04% between less accurate map-based model and HiFi model in case of average power losses estimation. The highest 99.75% accuracy is achieved between the HiFi and the MFi model's responses. The error in the efficiency estimation among literature studies and the proposed multi-fidelity models is used to verify the accuracy of the proposed methods. In addition, the maximum error between the 3D FEM model and the simulation model of inductor losses is found to be around 4.3% at a high switching frequency. These excellent results between multi-fidelity models ensure the acceptance of the scalable modelling approach for PE converters modelling in EV applications.
A HiL test is executed at a very low latency of 18µs and a high degree of correlation is achieved between the MiL and the HiL model for output characteristic and the highest RMSE between these two models is limited to within 0.54 over an entire driving cycle.
Furthermore, from the performance comparison between SiC and Si, it can be concluded that the IBC could gain substantial improvement in cost, power density and weight while using the SiC MOSFET power modules. Hence, WBG-based IBC can contribute in enhancing the range of EVs.
Finally, the WBG-based optimized IBC prototype has attained the high efficiency of 98.4% at rated load condition during traction mode operation, which could be considered as a significant efficiency improvement.
From these remarkable results, it can be concluded that the scalable modelling approach would be a valuable asset to the EV industry, as scalable models can be rapidly deployed to multi-objective targets, including EMS and TMS optimization, reliability testing, short-circuit fault testing and predictive health maintenance. The requirements dictate whether execution time or accuracy is required to be modelled; but regardless of the selected models, the simulation results are guaranteed to produce deviations within 5%, thereby adding credence to the output. It will be useful for non-PE users of the EV industry to optimize the EV's modelling steps so that the proper selection criteria can be developed in choosing model with the appropriate level of execution speed versus complexity and accuracy.

APPENDIX
The main characteristics of the RT platform are listed below: •    Since 2017, she has been a Lecturer with Mondragon Unibertsitatea. Her main research interests include renewable energies, power electronic converters, power transmission and distribution, and energy storage systems.
PATRICE GARMIER was born in Roanne, France, in 1979. He received the degree in electronic from the Université de Saint Etienne. He was with PSA in integration and validation of electronic systems at vehicle level, for a period of seven years. He is currently an Electronic Engineer in HiL bench and real-time systems with Applus IDIADA. He is currently a Researcher and a Lecturer with the Department of Electronics, Faculty of Engineering, Mondragon Unibertsitatea. He has participated in various research projects in the fields of traction and stationary systems for railway applications, renewable energy applications, energy storage applications for traction, and on-grid and off grip systems. His current research interests include power electronics modeling, energy storage modeling, and control of energy storage systems via power electronic converters.
OMAR HEGAZY (Member, IEEE) received the Ph.D. degree from the Department of Electrical Machines and Energy Technology (ETEC), Vrije Universiteit Brussel (VUB), Belgium. He is currently the Head of the Power Electronics and Electrical Machines (PEEM) Division [Power Electronics Innovation Laboratory (PEIL) and Powertrain Innovation Laboratory (PIL)], ETEC Department, and the MOBI Research Centre, where he coordinates the research activities in this field in several national projects, such as VLAIO (ex. IWT), innoviris, Flux50, and so on., and European projects, such as SAFEDRIVE, UNPLUGGED, ELIPTIC, ORCA, ASSURED, HiFi-Elements, GHOST, HiPERFORM, ACHILES, LONGRUN, eCharge4drivers, and so on. He is the author of more than 120 scientific publications. He is a member of EPE and IEC standards. His research interests include power electronics, electrical machines, electric and (plug-in) hybrid electric vehicles, digital twins, charging infrastructure, power/energy management strategies, battery management systems (BMS), V2x systems, optimization techniques, and smart DC grid with renewable energy.