A 0.5 V 8–12 Bit 300 KSPS SAR ADC With Adaptive Conversion Time Detection-and-Control for High Immunity to PVT Variations

In this paper, a low power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) involving the process, voltage, and temperature (PVT) compensation is presented. A proposed adaptive conversion time detection-and-control technique enhances the power efficiency, covering wide PVT variations. The proposed detection-and-control technique senses PVT variation in an aspect of conversion time, and adaptively controls the operation speed and power consumption. For PVT compensation, the proposed architecture includes the local supply/ground voltage. The local supply/ground voltage makes high $\vert \text{V}_{\mathrm {GS}}\vert $ for transistors in the comparator and capacitive digital-to-analog converter switches, resulting in enhanced operation speed. However, when PVT condition changes to be favorable for the conversion speed, the $\vert \text{V}_{\mathrm {GS}}\vert $ decreases for low power consumption. 30 chips were measured to verify the proposed ADC. Having the proposed architecture tested with 10 kHz input frequency, SNDR remained higher than 60 dB at unfavorable conditions such as −9 % supply voltage variation, or −20 °C temperature variation. On the other hand, at favorable conditions such as +9 % supply voltage variation, or 80 °C temperature variation, the power consumption of SAR ADC decreased without performance degradation.


I. INTRODUCTION
The successive approximation register (SAR) analog-todigital converters (ADCs) are the most promising candidate for low power applications such as battery-powered sensor nodes and bio-medical systems. SAR ADCs operating at low supply voltage for power efficiency have been reported [1]- [9]. Since using the low supply voltage can cause problems such as leakage current or low signal-to-noise The associate editor coordinating the review of this manuscript and approving it for publication was Omid Kavehei . ratio (SNR), many studies mainly have focused on the leakage current or low SNR. However, the low supply voltage SAR ADCs are also vulnerable to process, voltage, and temperature (PVT) variations. Recently, several ADCs involved temperature compensation technique for comparator under the low supply voltage, and PVT-stabilized technique for dynamic amplifiers [9]- [11]. Besides these problems, conversion speed also can be severely affected by PVT variations. Due to the uncertainty of PVT variations, ADCs should have much faster conversion speed than target specifications. However, it causes unnecessary power consumption at the PVT VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ conditions that are favorable for the conversion speed. When MOSFET is operating in the subthreshold region, the drain current is where I 0 = µ 0 C ox (W /L)U 2 T (m − 1), and µ 0 , C ox , U T , and m denote the carrier mobility, gate oxide capacitance, thermodynamic voltage (kT/q), and subthreshold slope factor, respectively [9], [12]- [13]. The high sensitivity of drain current to PVT variations can be inferred by using (1) [13]. Fig. 1. shows a normalized conversion time at the worst-case corner and temperature conditions depending on the supply voltage. The normalized conversion time means that the longest conversion times are divided by the conversion time that is required at the TT, 27 • C. When the supply voltage is 1.2 V, the conversion time becomes longer by 1.28-times at the SS and 80 • C in comparison with the conversion time at the TT and 27 • C. For 0.5 V supply voltage, the conversion time becomes longer by 7.66-times at the SS and −20 • C in comparison with the conversion time at the TT and 27 • C. These variations result in accuracy degradation due to incomplete conversion in asynchronous SAR ADC. In other words, the ADCs having 1.2 V supply voltage should have 1.28-times faster conversion speed than the speed that is required at the TT and 27 • C, which prevents performance degradation at the SS and 80 • C. However, for the ADCs having 0.5 V supply voltage, the conversion speed should be 7.66-times faster, which implies much larger power consumption. Therefore, in this paper, a low-power SAR ADC with full consideration of PVT variations is proposed. The proposed system detects the PVT variation by monitoring the conversion speed and then controls the supply voltage to reduce power consumption. Fig. 2. shows the PVT compensation and reduction in current by controlling the supply voltage depending on PVT condition. As shown in Fig. 2., the conversion time becomes short by increasing the supply voltage to compensate for the PVT variations. In the case of the other PVT conditions, the supply voltage level becomes lower for low power operation, which does not cause performance degradation. Section II will discuss the proposed architecture for sensing and compensating the PVT variation. In sections III and IV, the implementation of the proposed SAR ADC and measurement results will be presented. Lastly, a conclusion will be drawn in sections V. Fig. 3. shows the conceptual block diagram of the proposed PVT compensation system. The supply voltage generator supports the ADC's global supply voltage, and the I ADC represents the current. Once the 'PVT SENSING' block gives the information of PVT to the 'Local supply/ground' blocks, local supply/ground voltages of 'comparator' and 'switches' of a capacitive digital-to-analog converter (C-DAC) are adjusted. In the SAR ADC operation, the comparison time of the comparator, and settling time of C-DAC have a large portion of the overall conversion speed. This problem  becomes worse when the resolution of ADC increases. Thus, the change in local supply/ground voltages for these blocks can control the conversion speed of ADC, as described in Fig. 2. (a). If PVT changes to be favorable for the conversion speed, local supply/ground voltages become original values like Fig. 2. (b) to reduce the I ADC of Fig. 3, which assuring low power consumption.

A. SENSING THE PVT VARIATIONS
PVT SENSING block senses conversion speed (or conversion time) to sense the PVT variations. Since SAR ADC determines each bit in consecutive order, the least-significantbit (LSB) decision denotes the end-of-conversion (EOC). The detection logic compares the EOC with the next sampling clock that is synchronized by the reference clock to monitor the conversion speed [14]. If conversion speed becomes too slow to complete the conversion, the next sampling clock precedes the EOC. In this case, the PVT SENSING block increases the thermometer code (D DNC ) to accelerate the conversion speed. However, at some PVT conditions such as FF corner, higher supply voltage, or 80 • C, the accelerated conversion speed causes large power consumption. Therefore, if the EOC precedes the next sampling clock because of fast conversion speed, the PVT SENSING block decreases the D DNC to decelerate the conversion speed and reduce the power consumption. After several sequences of the tracking PVT, D DNC has two repeated codes in the locking state. Fig. 4. shows a locking state and the criteria to prevent the LSBmissing in the locking state. Since the deceleration of conversion speed can cause LSB-missing, the PVT SENSING block compares the sampling clock with a delayed EOC (DEOC) that is the delayed signal from EOC by T delay . Moreover, if the conversion time variation by changing D DNC ( T com ) is too large, LSB-missing occurs in the locking state. Therefore, T com should be shorter than T delay , i.e., detection-andcontrol has the following criteria.

B. COMPENSATING PVT VARIATIONS
Local supply/ground voltage can be easily realized by capacitor switching by using a temporal voltage shift because all sub-blocks of SAR ADC are the dynamic circuits. The local supply/ground voltage increases before the operation, and the sub-blocks operate fast with a high |V GS | and |V DS |. For convenience, only |V GS | will be mentioned in this paper.
After the operation of sub-blocks, the capacitors are charged again during the reset phase. The local supply/ground voltage has a multi-level, and the D DNC determines the voltage level. The number of levels determines the resolution of the control of power consumption. However, increasing the number of levels leads to the burdens of hardware complexity and power consumption, which cancels out the benefits. Moreover, the maximum number of cycles to find the locking state also increases. As shown in Fig. 5 (2). Delay block consists of inverters, and the number of inverters is determined by the worst-case PVT conditions to guarantee the condition of (2). Two T-F/F make the 1/2 divided and 1/4 divided CK_SAM clock (period of each signal is 2× and 4× period of CK_SAM) for PVT detection, and D DNC update, respectively. In other words, the compensation procedure is repeated every four conversion cycles and fully utilizes the given conversion time for lowpower operations.

B. VDD-BOOSTER AND VSS-SINKER FOR MULTI-LEVEL SUPPLY/GROUND VOLTAGE
The VDD-Booster and VSS-Sinker blocks generate the multilevel supply/ground voltage adaptively to compensate for the PVT variation. Fig. 6. shows the schematics of VDD-Booster and VSS-Sinker. The VDD-Booster generates a higher voltage than the supply voltage by switching the capacitors.   the momentary leakage current can be ignored. When CK becomes HIGH again, the gate of M P becomes LOW, and the bottom of capacitors switches from VDD to ground. The VSS-Sinker block operates similarly as the VDD-Booster block.

C. ADAPTIVE ACCELERATION C-DAC SETTLING SWITCH (ACS)
Since the capacitance of C-DAC exponentially increases with a resolution of ADC, C-DAC settling time should decrease to speed up the SAR operation. Fig. 7. (a) shows the implementation for adaptively accelerating the C-DAC settling switch (ACS). To enhance the C-DAC settling speed, VDD-Booster and VSS-Sinker are used to S-inverters (small W/L) driving L-inverters (large W/L) which drive the capacitors of C-DAC. In the split capacitor C-DAC [15], COMPX (COMPP or COMPN) nodes and MX (M1 or M2) nodes change from HIGH to LOW and from LOW to HIGH, respectively, during C-DAC switching. In a differential split capacitor C-DAC, four capacitors (C n ) take a role in one bit, and thus, four S-inverters share a single VDD-Booster and VSS-Sinker. The |V GS |s of PMOS and NMOS in the S-inverter are The proposed SAR ADC adopts a multi-period clock generator [14]. The multi-period clock generator selects the number of buffers according to D DNC , controlling the period of comparator clocks suitable for the C-DAC switching speed. Fig. 8. shows the schematic of the adaptive boosting comparator (ABC). The ABC comprises of an integrator-based amplifier and the latch [16]. VDD-Booster and VSS-Sinker are used to the second stage and the first stage, respectively. At a reset phase, the voltages of OUT1/OUT2 are VDD, and outputs of the second stage are LOW. During an evaluation phase, the OUT1/OUT2 nodes decrease with different speeds according to the input differences. The second stage uses the difference between OUT1/OUT2 nodes to determine the output of the comparator (OUTN/OUTP). Without acceleration, the discharging for load capacitors of the first stage takes a longer time, and the metastability problem of the second stage can be even worse. With acceleration, D Sink and D Boost signals that are decoded from D DNC and synchronized with clock( ) switch the bottom of capacitors of VSS-Sinker and VDD-Booster. Switching capacitors in VSS-Sinker and VDD-Booster blocks increase the |V GS | of input transistors in each stage. Consequentially, the ABC archives fast discharging and the decision. Table. 1. shows the simulation results of the noise and comparison time (T comp ) of the ABC. The noise includes quantization noise (V Q ), thermal noise (V T ), and comparator noise (V C ). The simulation results show that the comparison time at SS corner and −20 • C is longer than that of TT and 27 • C without boosting. However, with the boosting, the comparison time decreases without degradation of SNR compared with TT, 27 • C.

E. RECONFIGURABLE C-DAC
The proposed SAR ADC also has the resolution reconfigurable functions [17]. Fig. 9. shows the schematic of the C-DAC with the resolution reconfigurability. External digital codes for the reconfigurable operation connect additional capacitors to 8-bit C-DAC. The switches between CTOP node and CTOP AUX1 or CTOP AUX2 are 2.5V NMOS transistors (I/O transistor), and the gate voltage swing is 2.5V for the linearity.

IV. MEASUREMENTS
The prototype was fabricated in 65 nm CMOS, and the size is 0.039 mm 2 (0.318 mm × 0.123 mm). Fig. 10. shows the fabricated die micrograph. Even though ADC involves the VDD-Booster, VSS-Sinker, and DNC blocks, there is no extra area for them because the C-DAC area dominates the ADC area. The temperature chamber changed the chip temperature, and the power supply changed the supply voltage. Lastly, 30 chips from 2 wafers were measured to consider process variation. Fig. 11. shows the measured ENOB and current where A, B, and C indicate 'disable the proposed scheme (conventional),' 'enable (ACS + ABC),' and 'enable (ACS + ABC + DNC),' respectively. In these   measurements, the PVT variations include the supply voltage variation from 0.46 V to 0.54 V (+/− 9 % variations), temperature variations from −20 • C to 80 • C, and the sampling rates ranging from 100 KSPS to 700 KSPS. At the harsh condition of 700 KSPS, 0.46 V, or −20 • C, ENOB of 'C' (adaptively managing) has the same ENOB with the same in 'B' (continuously accelerating). And, at the favorable situation for ENOB, such as slower sampling rate, higher supply voltage, or higher temperature, the current in 'C' mode is decreased by 27% compared to 'B' mode without ENOB degradation. Unlike 'A' and 'B', 'C' mode has relatively consistent FoM W in the wide PVT variations. That is, the proposed SAR ADC can adaptively control the power consumption and conversion speed depending on PVT variations. 30 dies from two different wafers of an MPW shuttle were tested to verify the performance over chip-to-chip variations. Measurement results show their ENOBs at 300 KSPS, 500 KSPS, and 700 KSPS as a function of samples. Fig. 12. and 13. shows the measurement results of dynamic performances and DNL/INL of the proposed ADC at 12-bit configuration, respectively. The   Table 2. shows the dynamic performances   [9], [11]. At the various PVT conditions, such as process variation (30 chips), voltage variations (+/− 9 % supply voltage), and temperature variations (from −20 • C to 80 • C), SNDR remains over 60 dB.

V. CONCLUSIONS
Low power SAR ADC with adaptive conversion time DNC for high immunity to PVT variation has been presented. The DNC block of the proposed SAR ADC detects the conversion time according to PVT variations, and adaptively controls the conversion speed and power consumption. The prototype ADC with the reconfigurable 8-12-bit resolution was fabricated using the 65nm process. In comparison with the other state-of-the-art low supply voltage ADCs, the proposed work shows the high immunity to PVT variations. In 2009, he joined Nanyang Technological University, where he is currently an Associate Professor. He has authored or coauthored more than 110 journal and conference papers and has 17 U.S. and Korean patents registered. His current research interests include low-power and high-performance digital, mixed-mode, and memory circuit design, ultralow-voltage circuits and systems design, variation and aging tolerant circuits and systems, and circuit techniques for 3-D ICs. He has served numerous conferences as a Committee