Asymmetric SECE Piezoelectric Energy Harvester Under Weak Excitation

Piezoelectric energy harvesters (PEHs) are widely used to convert energy from a piezoelectric transducer into a stable DC form, which enables low-power IoT devices to have an unlimited operating life without using batteries. Under weak excitation conditions, however, the power-extraction efficiency of conventional PEHs is too low to provide power even to low-power IoT devices that requires low operation voltages less than 2 V. This paper proposes an asymmetric synchronous electric charge extraction (ASECE) scheme that improves the extraction efficiency of PEHs at low output voltages under weak excitation. The proposed ASECE is implemented using <inline-formula> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS technology. The figure-of-merits (FOMs) of the proposed ASECE while operating under 2 V of output voltage are 7.14 and 6.24 at weak and strong excitations, respectively. The maximum FOM for various different excitation levels is observed to be as high as 7.7. The proposed ASECE is superior to prior art with respect to FOM, by at least <inline-formula> <tex-math notation="LaTeX">$1.15\times $ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$1.63\times $ </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">$2.21\times $ </tex-math></inline-formula> under 2 V, 1 V, and 0.5 V outputs, respectively, under strong excitation.


I. INTRODUCTION
Battery-powered IoT devices have been widely used for embedded and remote sensors, but frequent replacement of their batteries due to limited lifetimes leads to higher operation and maintenance (O&M) costs. Energy harvesters eliminate the need for batteries, allow for unlimited operating lives, and thus lower O&M costs [1]- [5]. Among various energy sources, vibration-energy harvesting can utilize any mechanical vibration from common household goods, smart factories, vehicles, airplanes, constructions, and so on [6]- [10]. There are three main approaches regarding the implementations of a vibration-energy harvesters: electrostatic, electromagnetic, and piezoelectric. In-plane and out-of-plane capacitors produced using a micro-electro mechanical system (MEMS) can be used as electrostatic energy harvesters [11], but electret potential is a lot higher than several tens of Volts that requires higher voltage switching devices and causes higher The associate editor coordinating the review of this manuscript and approving it for publication was Yingxiang Liu . conduction losses. For periodically stressed applications, electromagnetic energy harvesters can be realized at the expense of bulky magnets and macro-scale coils [12]. Finally, piezoelectric energy harvesters (PEHs) are the simplest devices to fabricate, because their structural vibrations are directly converted to a voltage output without any additional complexity. In addition, PEHs can produce 3 to 30 times more power than their electrostatic or electromagnetic counterparts can at the compatible size [10], [13].
An example of a piezoelectric energy-harvesting system is shown in Fig. 1. Because the converted energy from the piezoelectric transducer (PT) is in a variable AC form, it cannot be directly used in most electronic devices requiring a stable DC supply voltage. When only a small amount of vibration energy is available, it is required to have a highly efficient PEH followed by a low-power IoT device using low operating voltage. These sensors indicate that an operating voltage of less than 2 V is widely used for lowpower applications [14]- [21]. Inductor-based PEHs such as SSHI, SECE, and precharging SECE in [7], [8], [22]- [35]  are widely used for IoT devices. Recently, the sense-andsat (SaS) scheme in [36] enhances the harvested power by maintaining the input near the maximum-power point at the expense of multiple switching in a cycle. In addition, the short-circuit synchronous electrical charge extraction (SC-SECE) in [37], phase-shift synchronous electrical charge extraction (PS-SECE) in [39], frequency tuning synchronous electrical charge extraction (FT-SECE) in [38], and conjugate impedance matching method in [40] have been developed for improving efficiency in wideband energy harvesting. However, the power extraction efficiency under weak excitation in the aforementioned PEHs is still too low to drive low-power IoT devices. In this paper, a highly efficient PEH that can operate under weak excitation conditions is proposed for lowpower IoT devices with low operation voltage. The proposed PEH adopts the SECE method to obtain a constant output power regardless of the output voltage. Furthermore, the proposed method harvests, flips, and precharges energy only once in a cycle to maximize power under weak excitation.

II. CONVENTIONAL PEHs
In order to analyze and compare various PEHs simply, all the components are considered to be ideal without any loss. A conventional full bridge rectifier (FBR) in Fig. 2 is a basic approach to harvest energy from a PT modeled with an internal capacitance C PZ and a sinusoidal input current i PZ , where the amplitude and frequency depend on the magnitude and period of the mechanical vibration, respectively. A FBR charges the output capacitor C O according to the positive and negative input currents through two different paths. Assuming that the diode forward voltage is zero, i PZ will charge C PZ until v PZ  charges C O till the end of a negative half cycle. The maximum charge available in each half cycle is q PZ . The shaded area in the first period depicts the charge stored in C PZ , represented by q FB_lost , which is not delivered to the output. q PZ and q FB_lost can be defined by where V PP is the peak-to-peak open-circuit voltage of v PZ . Next, the harvested power of an FBR, P FB , can be defined as where E H and f O are the harvested energy for each cycle and the vibration frequency, respectively. V O at the maximumpower point can be obtained by differentiating P FB with respect to V O .
The maximum-power point can be found when V O = 0.25V PP . Therefore, the maximum P FB becomes To eliminate the charge lost in C PZ , inductor-based PEHs have been researched as shown in Fig. 3. A synchronized switch harvesting on inductor (SSHI) in Fig. 3(a) has been widely researched in [6], [22]- [25]. In phase 1 (harvest), q PZ is fully delivered to C O because v PZ equals V O . Phase 2 (flip) is defined at the end of each half cycle, where S P turns on and v PZ is flipped to -V O through an inductor L. The operation in phase 3 is identical to that in phase 1, except that i PZ is reversed. The harvested power of a SSHI, P SSHI , can then be defined as Recently, a synchronized switch harvesting on capacitor (SSHC) has also been researched, wherein bulky inductors have been replaced with smaller capacitors [26]- [28]. As P SSHI has a linear relationship with V O , it is not appropriate for low-voltage applications. Fig. 3(b) shows the process of synchronous electrical charge extraction (SECE), wherein the harvested power is not limited by the output voltage [7], [8], [29]- [31]. In phase 1 (store), q PZ is stored in C PZ to its positive direction. In phase 2 (harvest), at the end of each C PZ to L. The charge is then harvested to the output when v PZ becomes zero by switching S P off and S S on. In phase 3, q PZ is stored in C PZ to its negative direction. The harvested power of an SECE, P SECE , can be defined as The harvested power is four times larger than that of an FBR. To increase the harvested power of an SECE, the process of precharging SECE, as shown in Fig. 3(c), has been VOLUME 8, 2020 researched [32]- [35]. Phases 1 and 3 are the same as those in an SECE. In phase 2 (harvest and precharge), S S is switched on in order to harvest charge from C PZ to C O and to charge C PZ to the precharged voltage value V PC (or -V PC ) through L depending on the previous phase. The harvested power of a precharging SECE P PSECE can be defined as where the power enhancement in a precharging SECE compared with that in an SECE is 2C PZ V PP V PC f O . Assuming that the change in V O is very small because of the large value of C O , the voltage across L is inverted for the entire duration of phase 2. The V PC is then defined as where V PC is V PC at the previous half cycle.  V PC becomes larger when V PP > 2V O , which may lead to problems due to overvoltage. To obtain a constant value of V PC , various alternatives have been researched [34], [35].

III. PROPOSED ASYMMETRIC SECE
A. BASIC IDEA Fig. 4 shows the circuit and timing diagrams of the proposed asymmetric SECE (ASECE). Phase 1 (store) corresponds to storing energy to C PZ . i PZ charges C PZ to a positive value from the initially charged value v PZ = V PP + V PC . In phase 2 (precharge & harvest), at the end of the positive half cycle, S P is on for precharging C PZ until v PZ reaches the preset value −V PC . The charged energy in C PZ is transferred to L. The rest of the energy stored in C PZ is harvested by switching S S on until the inductor current i L becomes zero. The operation in phase 3 (store) is similar to that in phase 1, except for the initially charged value of v PZ = −V PC and i PZ in the opposite direction. In phase 4 (flip), at the end of the negative half cycle, switching on S P allows for v PZ to be flipped to the positive as v PZ = V PP + V PC . The harvested power of the proposed ASECE P ASECE is defined as where the proposed ASECE extracts twice as much power as the SECE does, which can be observed from the first term of the equation. Moreover, the power is further increased by an amount corresponding to the second term of the equation, upon precharging C PZ . 99134 VOLUME 8, 2020   Fig. 5 shows a block diagram of the proposed PEH. All switches are implemented using transmission gates controlled by a pre-configured sequence at each phase. To find the end of phases 1 and 3, the peak detector monitors detector (ZCD) sets the digital output V ZCD to a high value at the instant that the inductor current becomes zero, in phases 2 and 4. The control logic receives the output signals from each block and generates the switching signals S S , S P , and S SP for each phase. The circuit and timing diagrams of the peak detector are shown in Fig. 6. The rectified voltage v REC is generated by M 3 and M 4 from v PZ + and v PZ − . An AC current flows from C 1 to R 1 as v REC increases, making V − higher than V + . v REC decreases after v REC reaches its peak value, resulting in V + > V − . When V + exceeds V − by V H , the hysteresis comparator CMP 1 sets the digital output V PK to be high. The peak detector is then reset by S SP immediately afterwards. Fig. 7 shows the circuit and timing diagrams of ZCD. To place ZCD into sleep mode, reset signals V R [0] and V R [1] are set to be high in phases 1 and 3, respectively. When v PZ + exceeds v PZ − , ZCD is enabled for phases 2 and 4 by making V R [0] and V R [1] low, respectively. If i L is larger than zero in phase 2, the on-resistance of M 1 depicted in Fig. 5 leads v PZ + to become negative. Thus, the timing for i L = 0 can be obtained at the condition v PZ + = 0. In phase 4, the timing for i L = 0 is detected in the same manner as the peak value of v PZ + is determined in phase 1 from the peak detector. Tables 1 and 2 summarize and compare theoretical power harvested for various PEHs described in Section II under ideal conditions and the configurations with recent publications, respectively.    Fig. 8 shows the simulated transient response of the proposed ASECE at the steady state. Phases 1 and 3 are operated over a positive and negative half cycle, respectively. These phases are slightly delayed because of hysteresis in the peak detector. In phase 2, S P and S S are switched on until v PZ − reaches V PC and i L reaches zero, respectively. In phase 4, v PZ − is flipped to v PZ + during the period in which S P is switched on. Fig. 9 displays the simulated output power with varying V PC , at various values of V PP . The output power of the proposed ASECE increases as V PC or V PP increases. The normal operating voltage of the proposed ASECE is set to |2V PP + V PC | ≤ V MAX , where V MAX is the maximum operating voltage of each transistor. In order to maximize VOLUME 8, 2020  the output power, V PC can be adjusted to satisfy the equation

IV. SIMULATION RESULTS
The calculated FOM of the proposed ASECE is compared with that of the conventional PEHs under the ideal condition shown in Fig. 10(a), wherein the FOM in [36] is defined as As shown in Fig. 10(a), the FOM of the proposed ASECE is higher than that of the conventional PEHs under an output voltage of 2 V. The simulated FOM of the proposed ASECE, compared with that of conventional PEHs designed with the same process, is shown in Fig. 10(b). An FBR comprises a Schottky diode supplied by the CMOS process. The switches of an SECE and SSHI are designed to be the same size as that   of the proposed ASECE. The FOM of the proposed ASECE maintains a value ranging from 12.6 to 14.2, which is higher than that of the conventional PEHs under an output voltage of 2 V. Fig. 11 shows a microphotograph of the proposed ASECE. The proposed ASECE is fabricated using 0.18 µm CMOS technology, and it occupies an area of 0.12 mm 2 . The experimental setup is shown in Fig. 12. A commercial PT (Mide PPA-1022) with a 0.9 g tip mass is placed on a shaker (Bruel & Kjaer type 4810) excited by a sine-wave signal. The signal, having a resonant frequency of the PT (85 Hz), is generated from a function generator and amplified by a power amplifier (Bruel & Kjaer type 2718). In Fig. 13, an accelerometer modeled BW 23204 is used for measuring V PP according to  Fig. 15 shows the measured input and switching waveforms of the proposed ASECE. As previously explained, i PZ is stored in C PZ during phases 1 and 3. In phase 2, the stored energy in phase 1 precharges C PZ to V PC , and the remaining energy is harvested. In phase 4, the stored energy in phase 3 is flipped to v PZ + . The detailed input and switching waveforms in phases 2 and 4 are shown in Fig. 16. In phase 2, S P is switched on until v PZ − reaches V PC . In phase 4, v PZ − is flipped to v PZ + , with v PZ + being slightly lower than v PZ − because of the conduction loss of the switching path. Fig. 17 shows the measured output power of the proposed ASECE in weak and strong excitations, compared with that of an FBR fabricated on a separated chip. Under weak excitation, the value of the output power delivered is up to 0.57 µW at an output voltage of 0.4 V. In contrast, under strong excitation, the output power remains almost constant over the wide output range, with a peak value as high as 4.05 µW. The maximum FOM under an output voltage of 2 V is measured at various values of V PP and is depicted in Fig. 18. The FOM under weak excitation is considerably higher than that under strong excitation, with a peak value of 7.7 at V PP = 1.25 V.   The proposed ASECE is superior to prior art under strong excitation. In Table 3, the proposed ASECE is compared with prior art with different topologies described in [18], [21], [28], and [31]. FOM values for three different conditions the proposed PEH is superior to prior art by at least 1.15× under an output of 2 V, 1.62× under an output of 1 V, and 2.21× under an output of 0.5 V. These results demonstrate that the proposed ASECE is more efficient than prior art under VOLUME 8, 2020

VI. CONCLUSION
A piezoelectric energy harvester with asymmetric SECE is proposed to achieve improved extraction efficiency, especially under conditions of low output voltage. Theoretically, the proposed ASECE extracts more power than conventional PEHs do. In order to measure the FOM, an FBR is fabricated using the same process as the proposed ASECE. The FOMs of the proposed ASECE with an output voltage of under 2 V are 7.14 and 6.24 under weak and strong excitations, respectively. The maximum FOM for various excitation levels is observed to be as high as 7.7. Compared with prior art, the proposed ASECE improves the FOM by more than 1.15×, 1.62×, and 2.21× under output voltages of 2, 1, and 0.5 V, respectively. Therefore, the proposed ASECE can be more practical compared with other PEHs when applied in lowpower IoT devices.