A 28-GHz Cascode Inverse Class-D Power Amplifier Utilizing Pulse Injection in 22-nm FDSOI

Current Mode Class-D (CMCD) Power Amplifiers are of particular interest in outphasing transmitters or Doherty configuration. This is because the output capacitance can be absorbed in the RLC output matching network and 100% theoretical efficiency. In this paper, a 28 GHz current mode (inverse) Class-D power amplifier was simulated, implemented, and measured in 22nm FDSOI. In order to overcome the breakdown voltages of the devices, the amplifier employs a stacked topology, which enables higher output powers and efficiency. The stacked transistors are also pulse injected to further increase the efficiency. Measurement results shows a peak PAE of 46%, peak drain efficiency (DE) of 71% and a saturated output power of 19 dBm. The implemented CMCD PA reports the best performance in literature compared to other CMOS based CMCD PAs.


I. INTRODUCTION
The performance of a power amplifier (PA) is an essential factor in the performance of a transmitter as a whole specifically when it comes to efficiency. The PA is the most power hungry component; hence, having a high efficiency PA results in less power consumption, cooling, and overall cost [1]. Switching PAs, in specific, have been of particular interest due to their ability to achieve 100% efficiency theoretically [2]- [4].
Switched-mode PAs (SMPA) are usually designed to operate at the maximum efficiency with the highest output power. This scheme is suitable for signals with a constant envelope. However, emerging technologies such as 5G employ signals with high peak-to-average power ratio (PAPR) since more complex modulation schemes are used. This means that the input signal has varying power levels which the PA needs to maintain its high efficiency at. With higher frequencies, the efficiency of SMPAs is limited due to the device parasitics and the limited switching speed [5].
SMPAs are able to achieve high efficiencies due to minimizing the overlap between the drain voltage and current.
The associate editor coordinating the review of this manuscript and approving it for publication was Vittorio Camarchia .
Such PAs are Class-E, Class-F, and Class-D (both voltage and current mode) [6], [7]. Table 1 shows a comparison in the performance of various switching amplifiers. From the table, current mode (inverse) Class-D (CMCD), introduced in [8], is able to achieve the largest peak power with a theoretically 100% efficiency. Inverse Class-D PA can also provide higher bandwidth compared to other SMPAs in case a wideband input matching is used [9]. CMCD also has the advantage of having the output drain capacitance absorbed into the output matching network allowing it to operate at higher frequencies compared to other SMPAs along with a relatively simple output matching network [10].
Some work in literature as in [4], [10]- [14] have implemented CMCD PAs with various CMOS technology or III-V technologies at lower frequencies. This work will utilize the high power capabilities of 22nm FDSOI technology with high f max of 371 GHz (NFET) at RF frequencies due to reduced parasitic to the substrate [15] along with the capability of CMCD to operate at high frequencies compared to other SMPAs.
This paper presents design, simulation, and measurements of a CMCD PA at 28 GHz utilizing Globalfoundries 22nm FDSOI technology. In order to overcome the breakdown voltage of the devices, increase efficiency, and deliver more output power, the implemented PA utilizes the cascode (stacking) topology [16]. In order to maximize efficiency, a new technique, pulse injection from the input transistor to the stacked transistor is proposed. The paper is organized as follows: Section II will discuss the principle of operation of the classical CMCD, Section III will present the design methodology of the proposed CMCD and introduce the concept of utilizing a cascode topology along with pulse injection. Section IV will discuss measurement results and comparison to the state-of-the-art CMCD PAs and section V will conclude the paper.

II. CONVENTIONAL CMCD PA
Unlike linear PAs, the transistors in SMPAs act as a switch. In a voltage mode class-D (VMCD) such as in Fig. 1, a square input signal is applied, an LC resonant tank is inserted in series with the load resistance to enable a sinusoidal current to pass through. This results in a non-overlapping peak drain voltage of VDD and peak drain current of VDD/R L . This non-overlapping behavior results in a 100% theoretical efficiency. However, the VMCD PA results in a large power dissipation at GHz frequencies. The CMCD PA overcomes this by utilizing an LC tank resonating at the fundamental frequency that absorbs the parasitic drain capacitance into the output network as shown in Fig. 2. The output voltage is sinusoidal where the overlap between current and voltage is also minimized. The drain voltages of each transistor (V D1 , V D2 ) are half sinusoidal. The current waveforms (i D1 , i D2 ) are square wave. The transistor currents i D1 and i D2 can be described as: where R on is the ON resistance of the device. The voltage on R load can then be expressed as: where A and B are the amplitudes of the two drain-source voltages with phase φ. Since the RLC tank allows only the resonance frequency current through the load, a sinusoidal voltage at f 0 is seen at R load . The output power can then be defined as: assuming A and B are equal; and the DC current through the transistors would be calculated as: The DC power P DC can then be defined as: The drain efficiency (DE) of the CMCD PA can then be represented by: From the equation above, it can be deduced that in order to increase the efficiency R on must be increased, which means a smaller device size. This then, is conducive to lower output peak power. In order to distribute the voltage stress, use  a higher supply voltage and deliver higher output power, a cascode configuration could be used with a relatively larger transistor size. Fig. 3 shows the topology of a cascode CMCD PA. The two input transistors are driven by equal input signals that are 180 • out of phase. The cascode transistors are biased at a constant DC input and serve the purpose of overcoming the breakdown voltage of the devices by allowing for a higher VDD. The circuit is symmetrical and the RLC tank results in a a sinusoidal voltage output at the drain. Fig. 3 shows the current and voltage waveforms of an ideal stacked CMCD PA. So an ideal CMCD PA should see an open circuit with no current for even harmonics and short circuit for all odd harmonics resembling a push-pull version of inverse Class-F PA [17].

III. PROPOSED CMCD TOPOLOGY
In order to enable the use of high output power, a higher supply voltage is needed. However, due to the limited breakdown voltage of the devices, this is limited. Thus, a cascode configuration is used.
Adding a cascode transistor, however, affects the charging and discharging time of the capacitance at the middle node negatively. This additional capacitance can be tuned out by adding a parallel inductor at the common node between the input transistors and the stacked ones. This helps achieve Zero Voltage Switching (ZVS) at high frequencies. Fixed gate bias of stacked CMCD PA suffers from efficiency degradation. The output capacitance increases by the gate-source capacitance of the cascode transistor resulting in a resonance frequency shift to a lower frequency.
In order to minimize the output parasitic capacitance, different gate biasing techniques can be used. A novel technique called pulse injection is proposed that entails the injection of signal from the input transistor to the output transistor (see Fig. 5). This way, we prevent the input transistor to turn on when the cascode transistor is off. Fig. 6 shows the improvement in peak DE when using pulse injection against having a fixed gate bias at the cascode transistor by 28%.
The input RF signal is applied to the gates of the under transistor and cascode transistor through transmission lines terminated on their characteristic impedance used also for biasing the gates of the cascode and under transistor to two different gate voltages VG2 and VG1. The lines are designed to have 100 so at the RF inputs we ''see'' 50 . The inductor L2 serves to resonate out the gate-source capacitances of the transistors M2 and M4 and the parastitic drain capacitances of the transistors M1 and M3. The capacitance seen at the intermediate nodes can be defined as: Since the frequency of operation is defined by: We can define the total parasitic capacitance C P Total as: Therefore, the value of L2 becomes: The value of the inductor L2 was accordingly designed to the maximum value without compromising on the quality factor. The center-tap inductor L1 connects to the supply voltage through a transmission line in order to choke the VOLUME 8, 2020  fundamental current of the tank. The load is resonant with inductor L1 and the capacitors C1-C2-C1. The purpose of the capacitive divider is to transform the high impedance of the tank to a differential impedance of 100 . This can apply to a 100 differential antenna or a single ended 50 antenna if one of the outputs is terminated with a dummy on-chip 50 resistance. The values of the capacitive divider C1-C2-C1 represented in Fig. 8 can be calculated as follows. To resonate at frequency f RF , the equivelant capacitance C eq is: The quality factor Q can then be calculated as: where C t is the total capacitance. Setting the BW to 1 GHz, the quality factor (Q) is 28. Since L1, Q and f RF is known, then: Replacing into the equation for f RF : C1 and C2 can the be calculated by: Fig. 5 shows the schematic of the pulse injected CMCD PA. The gate-source capacitance of the stacked transistor is 40 fF. With a 50 input, the impedance at the gate is very low (37 ) and the cut-off frequency is much higher than 28 GHz. This provides a broadband input bandwidth without adding any additional capacitance at the gate of the stacked transistors. Fig. 4 shows the simulated non-overlapping drain voltage and current waveforms of the output transistor using harmonic balance simulation at peak PAE. Fig. 7 shows the small signal parameters of the PA with broadband input matching.

IV. MEASUREMENTS RESULTS
The chip in Fig. 9 was implemented in the Global Foundries CMOS 22nm FDSOI technology. The testing was done on-chip using the Elite 300 semi-automatic probe station. The input and output signals are measured using ground-signalground-signal-ground (GSGSG) probes while the DC signals are applied through a multi-wedge probe.
The applied out-of-phase input signals were supplied from two signal generators frequency locked to the same reference and adjusted in anti-phase (180 • ) from their phase control knob. The measurements took into account the losses of the connected wires. Fig. 11 shows the simulated and measured  PAE and DE. The PAE is measured as: The measured Peak PAE and DE shows 46%/72% respectively (see Fig. 11) with peak PAE at 0 dBm input power. Fig. 10 shows a maximum output power of 19 dBm with a power gain of 17 dB to a 50 load. The frequency was swept from 26 GHz to 30 GHz and output power was recorded. The CMCD PA shows a narrow-band response as shown in Fig. 13 with output power greater then 15 dBm for a 1 GHz bandwidth. In order to measure power delivering capabilities, the supply voltage was increased and output power was recorded (see Fig. 12). The CMCD PA is able to deliver higher power with a higher VDD; however, it is limited to the breakdown voltage of the device. VOLUME 8, 2020    Table 2 shows a comparison between the performance of the proposed pulse injected CMCD PA and other switching PAs reported in literature in various technologies. When comparing the performance of PAs, it is important to keep in mind the operating frequency compared to the f max of the devices used. We are able to report the best measured peak PAE in literature compared to other CMCD PAs in CMOS. Our design also utilizes much less area due to a less number of passive elements; by only using 2 inductors compared to other designs using 5 such as in [12]. Other technologies such as GaAs HBT and GaN are able to report higher efficiencies and output power on the expense of cost and integration capabilities such as in [4], [13] at lower frequency bands. Overall, we are able to report the best performance at RF frequencies as high as 28 GHz compared to similar work reporting compatible efficiencies at 2.25 GHz in [10], [11] and better efficiency compared to other switching PAs near 28 GHz in [18]- [20]. To the best of our knowledge, no other work in literature reports similar performance at similar frequency bands.

V. CONCLUSION
In this paper, a novel 28 GHz Current mode class-D was implemented and measured in 22nm FDSOI. In order to overcome the limited breakdown voltage of the devices, use a higher supply voltage and deliver high output power, the architecture relies on stacked topology. A novel technique, pulse injection, was implemented to the cascode transistors to improve efficiency. The measured CMCD PA reports a peak PAE of 46% and a peak DE of 71% with output power of 19 dBm. It represents the highest performance reported for a CMCD PA in CMOS at 28 GHz. This amplifier is suitable for outphasing transmitters or a Doherty configuration to improve efficiency and handle large PAPR signals.
NOURHAN ELSAYED (Student Member, IEEE) received the B.Sc. degree in electrical and electronics engineering from Khalifa University, Abu Dhabi, United Arab Emirates, in 2014, and the M.Sc. degree in electrical engineering from The Petroleum Institute, Abu Dhabi, in 2016. She is currently pursuing the Ph.D. degree with Khalifa University. She has been working on multiple mm-wave designs from the simulation to the layout and measurement phase. Her current research interest includes RF circuit design specifically high-efficiency transmitter design for 5G applications.
HANI SALEH received the B.Sc. degree in electrical engineering from the University of Jordan, the M.Sc. degree in electrical engineering from the University of Texas at San Antonio, and the Ph.D. degree in computer engineering from the University of Texas at Austin. He has been an Associate Professor of electronic engineering with Khalifa University, since 2012. He is currently a Co-Founder and an Active Researcher with the Khalifa University Research Center (KSRC) and the System on Chip Research Center (SOCC), where he lead multiple IoT projects for the development of wearable blood glucose monitoring SOC and a mobile surveillance SOC in addition to AI edge devices. He has a total of 19 years of industrial experience in ASIC chip design, microprocessor design, DSP core design, graphics core design, and embedded system design. Prior to joining Khalifa University, he worked for many leading semi-conductor design companies, including a Senior Chip Designer (Technical Lead) at Apple incorporation, Intel (ATOM mobile microprocessor design), AMD (Bobcat mobile microprocessor design), Qualcomm (QDSP DSP core design for mobile SOCs), Synopsys (designed the I2C DW IP included in Synopsys DesignWare library), Fujitsu (SPARC compatible high performance microprocessor design), and Motorola Australia. His research interests include the Internet-of-Things design, deep learning, AI hardware design, DSP algorithms design, DSP hardware design, computer architecture, computer arithmetic, SOC design, ASIC chip design, FPGA design, and automatic computer recognition. He has 12 issued U.S. patents, eight pending patent application, and over 100 papers published in peer-reviewed conferences and journals in the areas of digital system design, computer architecture, DSP, and computer arithmetic.