An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO

In this paper, an ultra-low power, adaptive all-digital integer frequency-locked loop (FLL) with gain estimation and constant current digitally controlled oscillator (DCO) for Bluetooth low energy (BLE) transceiver in Internet-of-Things (IoT) is presented. For locking DCO frequency closest to the target channel, it adaptively controls capacitor banks with binary algorithm. With decrease in frequency resolution, DCO clock counts for each capacitor bank bit evaluation dynamically increases with the proposed technique for accurate frequency tracking. For compensating PVT variations and finding the BLE frequency deviation, the configurable digital DCO gain estimation is incorporated. The low power and constant current DCO operates in sub-threshold region and its power consumption is minimized by <inline-formula> <tex-math notation="LaTeX">$g_{m}/I_{D}$ </tex-math></inline-formula> methodology optimization, constant current source for limiting current in DCO core through adaptive low-dropout regulator (LDO) and lowering the supply voltage. The proposed design is integrated in an ADPLL for BLE transceiver and it is fabricated with 1P6M TSMC 55 nm CMOS technology. The all-digital adaptive FLL is fully synthesizable and its area is <inline-formula> <tex-math notation="LaTeX">$1800~\mu \text{m}^{2}$ </tex-math></inline-formula> with 1.233 K gate count. The RMS current consumption is <inline-formula> <tex-math notation="LaTeX">$103.32~\mu \text{A}$ </tex-math></inline-formula> from 1 V voltage supply with <inline-formula> <tex-math notation="LaTeX">$103.32~\mu \text{W}$ </tex-math></inline-formula> power requirement. The experimental results reveal, DCO draws <inline-formula> <tex-math notation="LaTeX">$480~\mu \text{A}$ </tex-math></inline-formula> current from 0.55 V supply voltage at center frequency. It has frequency resolution of 4.8 kHz. The oscillator PN, FOM and FOM<sub>T</sub> at 1-MHz offset frequency from 2.44 GHz carrier frequency are −122.85 dBc/Hz, 196.38 dBc/Hz and 208.19 dBc/Hz, respectively.


I. INTRODUCTION
Recently, the research on IoT devices for low power applications are increasing rapidly [1]- [4]. Ultra-low power, small area and low cost designs are the fundamental requirements for battery operated IoT devices. The BLE is very famous The associate editor coordinating the review of this manuscript and approving it for publication was Yong Chen . low power wireless connectivity standard in IoT applications. The BLE standard has been adopted as a popular solution for wireless connectivity in the IoT applications [5]- [8]. Similar to other wireless RF transceivers, BLE supported devices place a design challenges on the jitter performance, phase noise (PN) and modulation bandwidth of frequency locked loop. In RF transceiver applications, frequency synthesizer, frequency multiplier and phase locked loop (PLL) demand VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ circuits which bring oscillator frequency accurately closest to the target frequency. This essential task is performed by a frequency locked loop which is a vital circuit in RF devices and clock multipliers [9]- [11]. The type-1 PLL, depicted in Fig. 1(a) is composed of phase detector (PD), loop filter (LP) and voltage controlled oscillator (VCO) [12]. The FLL operation is performed in negative feedback loop with phase detector. It is simplest PLL due to single integrator in its control loop and high stability margin, unlike type-2 PLL [13]. However, if there is frequency drift, it cannot achieve zero average steady state phase error. Also, it has locking range constraint, limited disturbance capability and significant reference spur due to persistent ripples on the VCO control line [12], [14]. In analog type-2 PLL, a phase and frequency detector (PFD) acts as analog FLL to bring VCO frequency closest to target frequency [15]- [17]. The PFD circuit compares the f ref and f div to generate up/down signals and tunes VCO frequency closest to the target frequency as shown in Fig. 1(b). Other than digital PFD technique, for the high frequency PLLs a voltage multiplier makes a trick by multiplying f ref and f div signals and getting a phase variation in DC to bring VCO frequency close to target frequency. These PFD circuits drive charge pump circuitry which cause an increase in area, power and lock time. The charge pump suffers from charge injection and clock feed through. However, type-2 PLL achieves zero average steady-state phase error under both frequency drifts and phase angle jumps, unlike type-1 PLL. Also due to the fast scaling in CMOS technologies, analog FLL circuits suffer from process, voltage and temperature (PVT) variations, loop filter encounters current mismatch, capacitor leakage and limited dynamic range which cause undesired performance in RF applications [18]. To overcome these limitations of PFD, a digital FLL is introduced [19]- [24]. A counter senses VCO/DCO output frequency and then the value is compared with a target frequency control word (FCW) as shown in the Fig. 1(c) and Fig. 1(d). It reduces power consumption by eliminating the charge pump and lock time reduces by introducing coarse and fine tracking strategies. Different oscillator topologies are investigated for improving phase noise (PN) with small area and low power. The single LC-tank oscillators are compact in size but shows inadequate PN. The multi-core VCOs enhance PN and figure-of-merit (FOM) at the cost of additional chip area. Recently, the single-core multi-LC-tank oscillator topologies are reported with compact size and high FOM for mm-wave wireless applications [25], [29]. The digital designs are proven robust to these PVT variations. This brings the idea of all digital FLL design for the wireless applications which meets strict frequency requirements of RF domain [22], [30]. All digital FLL offers significant advantages as compared to analog FLL. Analog FLL requires more area, strict supply voltage requirements, large loop filter capacitors and severe degradation in the performance due to capacitor leakage, current mismatch and PVT variations. Also implementation of state of the art loop calibration algorithms to encounter the PVT variations are not easily possible in analog domain [31]. While the all digital FLL offers advantages like small on chip area, fast settling, reconfigurable loop filter and portability to other process technologies. Current frequency tracking methodologies [19]- [25] use fixed DCO clock cycles for frequency locking closest to the target frequency. The PLL output frequency is measured and its difference from FCW is provided to DCO. The counting duration of DCO output significantly affects the accuracy and the lock time. In prior works, fixed counting duration is used which results large deviation of the locked frequency from the target one. To overcome this limitation, an adaptive FLL is proposed which efficiently adjust the counting mask automatically and significantly improves the locked frequency accuracy. This paper focuses on alldigital frequency loop for BLE applications in IoT devices. The major contributions of proposed design are as follows: (a) An adaptive all digital frequency loop in which DCO clock cycles are counted adaptively in an increasing order as the frequency resolution decreases to achieve DCO fine tuning, (b) DCO gain estimation which is the single bit frequency resolution for PVT variations and frequency-shift keying (FSK) modulation in RF transmitter, (c) Four different configurable operating modes for various control levels of DCO frequency and (d) Constant current DCO.
The rest of this paper is organized as follows: Section II presents the design of the proposed all-digital frequencylocked loop (ADFLL). The detailed description of the proposed architecture at building block levels is included in Section III; Section IV shows the simulation and experimental results; Finally, the paper is concluded in Section V.

II. PROPOSED ADAPTIVE ALL-DIGITAL FLL DESIGN
An all-digital phase locked loop structure is composed of integer and fractional loops. The fractional loop is typically composed of, digital loop filter (DLF), time-to-digital converter (TDC) and DCO [32]. In integer loop, also known as frequency-locked loop, the DCO coarse tuning is achieved by controlling the coarse (MSB, LSB) capacitor banks. It tunes the free running DCO frequency closest to target channel frequency which is an integer multiple of reference clock. It reduces the frequency locking time and DCO fine tuning range. It operates only once in the beginning when one of the forty BLE frequency channels is selected. When integer loop finishes, then the fractional loop starts its operation. The fractional loop accommodates the fractional part of frequency and aligns the phases of both DCO and reference clocks in the lock state. This loop is always active while ADPLL is operating. In proposed design, before fractional loop, DCO gain is estimated for compensating PVT variations and FSK direct modulation. Numerous techniques for integer loop design are discussed in literature [19], [20]. This paper explores a very simple, reliable adaptive design for all-digital frequency-locked loop in ADPLL applications for BLE transceiver. The binary algorithm is used in a dynamic adaptive way for evaluating binary bit values of MSB and LSB capacitor banks.  If N M DCO clock cycles are measured in T M duration, then the DCO frequency is found in (2) as follows: Now, the target frequency f CH for a particular BLE channel is already known, then the number of DCO clock cycles, N C is calculated mathematically as follows in (3): The DCO capacitor banks are tuned in such a way that the measured N M and calculated N C number of DCO clock cycles are same. When this condition (N M ≈ N C ) is achieved then the DCO frequency f DCO is closest to the target channel frequency f CH . In ADPLL design, this goal is achieved in the integer loop before the gain estimation and fine tuning and phase locking in fractional loop. Thus, the design of FFL is very critical in order to achieve an accurate target frequency in an ADPLL.
In this paper, a simple, hardware friendly adaptive FLL design for integer loop is presented. For the evaluation of each bit of coarse capacitor bank, DCO frequency is measured for an adaptive number of reference clock cycles instead of fixed duration. The number of calculated DCO clock cycles are also adaptive with respect to the capacitor bit position. In the proposed design, the adaptive number of reference clock period, N REF (n) is defined as follows in (4): where, N is the total number of bits in the binary capacitor control word (CCW) for MSB and LSB capacitor banks. The n is current bit position which is being evaluated for DCO frequency measurement. Its range is 0∼N − 1. The N REF (n) is the function of capacitor bank bit position and its value increases dynamically as n decrements from N − 1 to 0. The total duration for DCO cycles count also becomes adaptive and is function of n, defined in (5) as follows: When, N M is measured for T M (n) interval for particular bit position n, then the DCO frequency is given by (6) as follows: The calculated number of reference clocks is now the function of CCW bit position, n and selected frequency channel. It is also adaptive and changes dynamically as the frequency channel and bit position vary. The adaptive number of reference clock cycles, N C (n, k) are given in (7) as follows: where, k = 0, 1, 2, 3 . . . 39 which corresponds to selected BLE frequency channels CH0∼CH39. The simplified result VOLUME 8, 2020 of (7) is given as follows in (8): The N FCW (k) is the frequency control word as a function of k and is computed by (9) as follows: Here N CH 0 is the base frequency magnitude of CH0, M is the DCO frequency multiplier factor and N is the DCO frequency division factor. Since, the inductor size is very critical in LC-tank based DCO design therefore, for any specific application, the minimum frequency f MIN is limited by the maximum inductance L MAX . For lower frequencies, the inductor size is bigger which results in an increase in area, power consumption and cost. One technique for comparatively reducing inductor size is to design DCO with integer multiple of the required frequency and then divide the frequency with the same integer to get required frequency. In this way the inductor size is reduced. This technique also improves the DCO phase noise. If, M is this multiplying factor then the DCO is running with the frequency as given in (10): The DCO running frequency is measured by counting its clock cycles. The counter size is dependent on the frequency and mask time. The DCO frequency is divided by an integer division factor D to reduce the area and power consumption of the counter.

B. DCO GAIN ESTIMATION
After FLL locking, the DCO gain estimation, single bit fine capacitor bank resolution, is determined before the fine tuning in integer loop. The gain estimation is essential for compensating PVT variations and calculating the deviation ratio before the start of direct modulation in BLE transceiver. It is calculated by counting the DCO clock cycles with setting the FINE capacitor back to its maximum and minimum values. The DCO gain, K DCO is computes as follows by the (11): (11) where, N MAX and N MIN are the maximum and minimum number of DCO clock cycles when the FINE capacitor bank is set to its minimum and maximum positions respectively and N FINE is the total number of fine capacitor bank bits.

C. LOW POWER DCO DESIGN
The oscillation condition [27] for low power CMOS cross coupled LC-tank DCO is written as follows: where, R P and g m are the equivalent parallel resistance of the passive section and the equivalent transconductance of active section respectively. The g m of the NMOS transistors is added to g m of the PMOS transistors constructively in the CMOS complementary structure. Therefore, compared to NMOS-only or PMOS-only architecture, the power consumption of cross-coupled structure is halved with the same current consumption. In now a day's battery operated devices, the low power consumption and low supply voltage are highly desired. The MOS transistor operation in sub-threshold region is suitable for low power consumption and low supply voltage requirements. The gate to source voltage V GS is less than the threshold value V TH in sub-threshold region. The drain current, I D in sub-threshold region is described as follows: where U T = KT /q, K , T , q, µ 0 , and C ox are thermal voltage, Boltzman's constant, temperature, electron charge, surface mobility and gate-oxide capacitance respectively. The parameter m represents capacitive coupling between silicon surface and gate. In sub-threshold region, the transconductance is expressed as follows: By selecting larger inductances, the power consumption is minimized. The R P is calculated as follows: where, f 0 is oscillation frequency, L is inductance value and Q L is quality factor of inductor. From (12) and (15), the oscillation condition is expressed as follows: Thus, minimum transconductance, g m,min is as follows: According to (17), the oscillation condition is satisfied with larger inductance and smaller g m in the sub threshold region. This results in less power consumption with lower supply voltage. The tail bias current is I bias = 2I D and its lower limit for sustainable oscillation is described as follows in (18): For the given bias condition in (18), MOS transistors provide high transconductance when operating in the sub-threshold region. The transconductance efficiency (g m /I D ) is maximum in the sub-threshold region while it is minimum in superthreshold region. The oscillation frequency f 0 of LC-tank DCO is given by the following (19): where, C and L are the effective capacitance and inductance respectively. This relation is re-written in more detail as follows in (20): where L F is the fixed inductance including the parasitic inductance and C F is the fixed capacitance including the parasitic capacitance. The N is the total number of bits and C is the minimum capacitance. From (20), the oscillation frequency of DCO is approximated as follows: where (21), the inductance of the DCO LC-tank is computed as follows in (22): For the particular DCO application, f MAX is defined to a fixed value and as a result fixed maximum inductance L MAX is achieved. Hence, C F defines an upper limit for L MAX . According to (22), with smaller C value, fine frequency step f is achieved and it controls DCO quantization noise within entire system. If the C is divided into MSB, LSB and FINE capacitor banks, then (20) is given as follows in (23): where; The C MSB , C LSB and C FINE are the unit capacitances for MSB, LSB and FINE capacitor banks respectively for attaining desired frequency resolution.

III. ADAPTIVE ALL-DIGITAL FLL ARCHITECTURE
The detailed architecture of the proposed all-digital FLL is depicted in Fig. 3. The major building blocks includes, alldigital adaptive FLL controller (ADAFLLC), LC-tank DCO and adaptive LDO (ALDO). The detail of each block is discussed in next sub-sections.

A. ALL-DIGITAL ADAPTIVE FLL CONTROLLER
The synthesizable digital circuit design methodologies using behavioral description languages is of great interest due to reusability, simplicity and easy scalability of the circuit  as compared to custom design [21]. Therefore, proposed ADAFLLC is designed with fully synthesizable digital controller and it tunes coarse (MSB, LSB) capacitor banks for target frequency and also performs gain estimation. The FLL main controller (FMC) ensures the operation of each block and generates the exact CCW for selected frequency channel in various modes. After, integer frequency is locked, the DCO gain estimation is computed. The FMC flow diagram is depicted in Fig. 4      In the presented FLL design, four configurable operating modes are proposed. These modes control the masking duration for counting DCO clock cycles in various methods. The fully adaptive mode (FAM) is the default mode, in which the counter mask is fully adaptive from MSB to LSB of the capacitor banks. This is the most accurate mode in terms of frequency measurement at the cost of comparatively more locking time. In partial adaptive mode (PAM), the counter mask is adaptive for selectable initial MBS and then become fixed for remaining bits to reduce the lock time. One of the configurable mask is selected and remains fixed during all iterations for capacitor bits in the fixed configurable mode (FCM). In this mode, the locking time depends in the selected mask. In external manual mode (EMM), the capacitor bits and locking signal are directly controlled from external controller for manual debugging and analysis purpose.

B. DIGITALLY CONTROLLED OSCILLATOR (DCO)
The LC-tank DCO is key building block in ADPLL and it consumes most of system power for generating local frequency [1], [25], [31], [33], [35]. Therefore, ultra-low power and ultra-low voltage DCO design significantly reduces system power consumption [36], [37]. The DCO performs digital-to-frequency conversion [32]. The constant current DCO configuration and simplified circuit diagram with MSB, LSB and FINE capacitor banks is shown in Fig. 8 [27]. Since the DCO power consumption is dominant factor in ADPLL in open loop operation, therefore DCO is designed with low power techniques. For minimizing current consumption and relaxing reliability problems, DCO supply is 0.55 V and it is relatively lower than other building blocks. The DCO is designed with ULP process and threshold voltage, V TH is very small (0.18 V∼0.2 V) for this process. The overdrive voltage is 0.1 V. The two transistor can get enough voltage form 0.55 V power supply. The 4-stack transistor (negative gm transistor) can get needed overdrive voltage from 0.55 V power supply. The sigma-delta modulator for dithering and binary to thermometer encoder (B2T) DCO digital sub-blocks can operate at 0.55 V supply. The DCO operates and have oscillations with supply voltage from 0.55 V to 1 V. The power consumption will increase if the DCO supply is increased from 0.55 V to 1V. Therefore, the lowest possible supply voltage of 0.55 V is used for minimum power consumption. The 1.2 V devices are used for the presented DCO and transistors reliability is assured for 1.32 V as maximum voltage. Although, peak voltage exceeds than oscillator VDD, it does not increase more than 1.2 V as analyzed from simulation results. Since a larger inductor reduces DCO power consumption, therefore, the main inductor is maximized while the parasitic capacitance is minimized for desired frequency range. The DCO phase noise depends on the frequency resolution, which is limited by the minimum switchable capacitance. For DCO design flexibility and frequency step linearity, the coarse and fine capacitor banks are designed with unit weighted capacitor rather than binary weighted configuration. By optimizing capacitor redundancies, parasitic capacitance is reduced by utilizing flexible number of capacitors in unit weighted structure in comparison with a binary weighted structure. For attaining high linearity and small switchable capacitance, a customized lateral metal capacitor is designed and fabricated, as shown in Fig. 8. Its capacitance is calculated from RC extraction which has 16 aF value approximately. The configurable MSB and LSB capacitor banks are designed with a variable bias switched capacitor. To improve LC-tank Q-factor, metalinsulator-metal (MIM) and metal-oxide-metal (MOM) capacitors are commonly employed instead of MOS capacitors for MSB and LSB capacitor banks. The MOM capacitors are used for designing low cost DCO with improved Q-factor. For minimizing area and increasing capacitor density, these capacitors are stacked from Metal 2 to Metal 5. Because the LSB capacitor bank requires minimum capacitance in the process design kit (PDK) therefore these MOM capacitors are stacked from Metal 3 to Metal 5. The unit capacitor cell is composed of a switch, two capacitors and two blocking resistors as elaborated in Fig. 8. Conventionally, the switch source bias voltage is fixed to zero. However, in case of DCO large swing, switch is not turned off completely in OFF-mode. This causes phase noise degeneration. To overcome this problem, two inverters are utilized as control logic for providing variable biasing. In ON-mode, the switch transistor source voltage is biased at zero while gate voltage is VDD (1V). On the other hand, in OFF-mode, gate and source voltages of switch are biased at zero and about LDO OUT (0.55V) respectively to ensure complete switch turn off. An ultra-wide width aluminum (Al) pad metal pattern is incorporated to eliminate the parasitic resistance and inductance due to metal routings. This only creates additional capacitance between Al pattern and capacitor banks. There is no stray parasitic capacitance problem due to large distance of about 8.8 µm between Al pattern and substrate. Aluminum pad metal has sufficiently large thickness and no width limitation. All parasitic inductors are tied in parallel with ultra-wide width Al pad metal and via. In this way, parasitic inductors are eliminated effectively. As a result, the DCO is parasitic inductance free and ensures linear frequency steps. As a result, frequency steps are closer to that of measurement and accurate oscillation frequency is achieved without additional cost for Al pad layer. For dithering, one out of 64 cells of FINE capacitor bank is controlled by the first order sigma-delta modulator (SDM). Therefore, SDM dithering effective frequency resolution is 1/16 of the 1-bit frequency resolution of the FINE capacitor bank. In DCO design, there is trade-off between oscillation frequency range and power consumption. The two Lc inductors at top and bottom of DCO are customized design. The inductance of each of these inductors is 3 nH. Each inductor has very small resistance and there is very small voltage drop improving PN by 6 dB at 1-MHz offset. The purpose of these inductors is to improve the phase noise of the DCO. Firstly, two inductors are designed based on EMX simulation and then its quality factor and inductance values are calculated as 15 and 3 nH respectively. The negative gm-cell placement also affects DCO power consumption and frequency range. If all transistor switches are off, the DCO exhibits large parasitic inductance, reduces frequency and decreases current consumption when a negative g m cell is placed at capacitor banks end side. Similarly, if a negative g m cell is positioned at inductor end side then the negative g m cell Q-factor degrades and DCO power dissipation increases. Therefore, for designing low power DCO, the negative g m cell is located at capacitor banks end side in the proposed FLL.

C. ADAPTIVE LDO
The minimum oscillation and power dissipation of DCO changes with PVT variations. When constant voltage source is used, the DCO draws more current at corner cases due to decrease in g m . To provide constant current to DCO, an adaptive LDO [27], depicted in Fig. 9 is integrated as DCO driving voltage source. The LDO output voltage automatically changes with PVT variations to keep g m constant.
97222 VOLUME 8, 2020 The proportional to absolute temperature (PTAT) bandgap reference (BGR) compensates temperature variations and LDO function regulates voltage variation. With PTAT BGR, ALDO ensures constant voltage and current across DCO at corner cases. At corner conditions, constant current keeps DCO g m constant and reduces DCO power consumption significantly. With ALDO, around 50% power consumption is reduced at the corners.

IV. EXPERIMENTAL RESULTS
The proposed adaptive all-digital FLL is fabricated by using 55 nm 1P6M TSMC CMOS technology. It is part of ADPLL in BLE transceiver for IoT applications. The power supplies for fully synthesizable FLL and DCO are 1 V and 0.55 V respectively. Fig. 10(a) shows the chip microphotograph with 45 µm × 40 µm and 360 µm × 220 µm area of ADAFLLC and DCO respectively with total 0.081 mm 2 area. Fig. 10(b) shows the testing board with fabricated BLE chip for measuring proposed design. Fig. 11 shows lab experimental environment for measuring the performance of FLL and DCO for which spectrum analyzer, signal generator, oscilloscope and power supply are used. Fig. 12 shows the measurement results for integer ADAFLLC operations. The measurement results   show that the locked frequency for selected channel is more near to the target frequency with proposed adaptive design. In Fig. 12(a), the BLE CH0 target frequency is 2.402 GHz. The frequency deviation from target one is 2 kHz only with adaptive mode while it is 1.078 MHz without adaptive mode. Similarly, for CH19 and CH39, the frequency deviation is much less with proposed FLL in adaptive mode as shown in Fig. 12(b) and Fig. 12(c) respectively. The measurement results for frequency deviation of all forty BLE channels with and without adaptive mode are elaborated in Fig. 12(d).
The measurement results prove that the proposed ADAFLLC design is highly effective and lock the integer loop with frequency which is much closer to the target frequency. The frequency deviation is greater in case of without adaptive mode. Fig. 13(a) and (b) show the measured output spectrum and phase noise of DCO respectively. At 1-MHz offset, the measured PN is −122.85 dBc/Hz. The DCO measured performance of PN versus supply voltages and current consumption are plotted in Fig. 14. As shown in Fig. 14    and it is depicted in Fig. 15 (a). The MSB, LSB, FINE capacitor banks and SDM dithering measured 1-bit resolutions are 14.42 MHz, 870 kHz, 78.21 kHz and 2.41 kHz respectively as depicted in Fig. 16. Table 1 summarizes the performance of fully synthesizable FLL. Its power consumption is 103.32 µW for its full operation. For its implementation in chip, it requires only 1.233 K gates with 1800 µm 2 chip area. The lock time ranges 3.7∼6487 µs and it depends   on the selected mode and configured parameters. The DCO performance and comparison with existing designs is listed in Table 2. It needs 0.264 mW power for its full operation. It occupies a very small chip area of 0.0792 mm 2 when compared with prior works. The PN is −122.85 dBc/Hz. The FOM and total figure of merit (FOM T ) are 196.38 dBc/Hz and 208.19 dBc/Hz respectively confirming its good performance for low voltage and low power applications including  BLE. The FOM and FOM T are evaluated with (24) and (25) respectively [33], [34].
FOM T = |PN |+20 log 10 (( f 0 f )( %FTR 10 ))−10 log 10 ( P DC 1wW ) The FLL performance comparison with the exiting counter based topologies is summarized in Table 3 [22], [25], [26]. Most of previous integer FLL work such as in [22] and [25] used fixed number of clock cycles for each capacitor bank bit evaluation. In contrast, for locking DCO frequency closest to target channel, proposed FLL algorithm adaptively controls capacitor banks with binary algorithm. With decrease in frequency resolution, DCO clock counts for each capacitor bank bit evaluation dynamically increases with the proposed technique for accurate frequency tracking. Additionally, the configurable digital DCO gain estimation is incorporated for compensating PVT variations and finding the BLE frequency deviation. Finally, in the presented work, four configurable operating modes are proposed which control the masking duration for counting DCO clock cycles in various methods. The measured reference super for the fractional mode is less than −68 dBc, as depicted in Fig. 17. The ADLDO measurement and corner simulation results of is plotted in Fig. 18.  The V OUT increases with the increase in temperature. Without ADLDO, when constant voltage source is used, DCO draws more current due to the increase in g m . With ADLDO at the corner conditions, this biasing current remains 50% for powering the oscillator. For same g m with process variation, FF corner requires lower V OUT than TT and SS corner requires less V OUT than TT. With BGR constant current, diode connected MOS determines suitable reference voltages. The MOS transistors threshold voltage changes due to process variation and as a result the reference voltage also changes. The V OUT varies due to trimmed reference voltage and DCO has the same g m , consumes constant current and dissipates similar power.
The Fig. 19 shows co-simulation for presented integer loop for BLE channels 0, 19 and 28. Fig. 19(a) shows the simulation result for BLE CH0 with 2.402 GHz target frequency. The DCO is tuned to 2.403447 GHz after FLL locking with the deviation of 1.447 MHz. Fig. 19(b) and Fig. 19 (c) show the simulations for channels 19 and 28 in which the locked frequency values are 2.438383 GHz and 2.457939 GHz with 1.617 MHz and 61 kHz frequency deviations respectively. Fig. 20 shows DCO post-payout simulation with 0.55 V power supply and 4.88 GHz oscillation frequency. The phase noise analysis is shown in Fig. 20(a). At 1-MHz offset from the operating frequency, the phase noise is −126.114 dBc/Hz. Fig. 20(b) shows the transient simulation DCO output in which maximum voltage swing is 0.613 V. The output of DCO obtained from periodic steady-state (PSS) analysis is shown in Fig. 20(c). The RMS current consumption of proposed DCO is around 463 µA. Fig. 21 shows the simulated frequency tuning range curves for the DCO . Fig 21 (a) shows DCO frequency tuning range curves based on SP simulation results. For finding frequency tuning range, the SP simulation is run to calculate the imaginary part of admittance (Y11) of 50 Ohm antenna port connected at DCO output. The minimum and maximum frequencies are 2.19 GHz and 2.64 GHz at Y11 zero crossing with tuning range of 450 MHz when capacitor codes are all high and all low respectively for TT corner case as shown in Fig. 21 (a). The transient simulation of MSB capacitor bank change based DCO frequency tuning range is shown in Fig. 21 (b). Since, MSB capacitor bank is for coarse tuning and it controls main   capacitance, therefore its code is changed from minimum value to its maximum value to get the upper and lower DCO frequency limits respectively. With TT corner case, the transient simulation based DCO tuning range is 450 MHz as shown in Fig. 21(b).The Fig. 22 summarizes ADFLL simulation results for different proposed modes. This is post place and route (P&R) level open loop simulation of ADAFLLC digital part without the DCO in Synopsys R VCS R tool. Fig. 22 (a) shows the PAM simulation in which the cmg_mask is adaptive from cap_bn 9 to 2 and then become 256 as fixed for remaining bit positions. The CCG also generates cal_dco_cnt accordingly. Fig. 22(b) shows the fully adaptive mode simulation results. The ref_div, calc_dco_cnt and cmg_mask adaptively change as cap_bn sweeps from MSB to LSB for DCO free running frequency tuning. The fixed configurable mode simulation is elaborated in Fig. 22(c) in which the one of the pre-defined fixed counter mask is generated for all cap_bn values against any selected channel. The detailed simulation result for CMG is shown in Fig. 22(d).
The adaptive mask generation is elaborated in which the mask time increases exponentially. The counter mask is configurable and adaptive with respect to cap_bn. The cmg_start is asserted high from FMC which initiates mask generation process. After receiving cmg_start signal, CMG first clears the cmg_cnt and then generates the mask for configured number of clock cycles according to the algorithm.

V. CONCLUSION
An ultra-low power, adaptive all-digital FLL with gain estimation and constant current DCO for BLE transceiver is presented in this paper. The binary algorithm adaptively controls capacitor banks for locking DCO frequency closest to the target channel. For accurate frequency tracking and tuning, DCO clock counts automatically increase for evaluating each bit of capacitor bank. For compensating PVT variations and finding the BLE frequency deviation, the configurable digital DCO gain estimation is incorporated. The low power FIGURE 22. All digital FLL simulation results for different proposed operating modes and CMG simulation. VOLUME 8, 2020 constant current DCO operates in sub-threshold region and its power consumption is minimized by g m /I D methodology optimization, constant current source for limiting current in the oscillator core through adaptive LDO and lowering the supply voltage. The ADAFLLC is fully synthesizable, occupies 1800 µm 2 area, utilizes 1  Since 2012, he has been with the College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South Korea, where he is currently a Professor. His research interests include implementation of power integrated circuits, CMOS RF transceiver, analog integrated circuits, and analog/digital mixed-mode VLSI system design.