Modulation With Metaheuristic Approach for Cascaded-MPUC49 Asymmetrical Inverter With Boosted Output

This work introduces a 49-level Asymmetrical Inverter (AMLI) with boosted output based on the cascaded operation of two 7-Level Modified Packed U-Cell inverters (MPUC-7). The converter is capable of operation with a boosted voltage of up to 1.714 times the maximum DC voltage employed. It requires only 12 active switches and 4 voltage sources. With the sources set in the ratio of 14:7:2:1, the 7-level output of the two converters is so utilized that the 72 = 49-level output voltage is generated across the load. A detailed explanation of level formation is discussed. This converter is operated using an Artificial Neural Network (ANN) which is trained for the harmonic elimination in the output voltage waveform. For the calculation of optimum angles, a meta-heuristic based Genetic Algorithm (GA) technique is employed. The generation of 49-level output requires 24 transitions in one quarter of a cycle. All these angles are generated for various desired output voltages, and the ANN is trained offline for the same. The converter and its control are simulated in MATLAB/Simulink® environment, and the results are verified on the experimental setup. The multilevel output thus obtained is nearly sinusoidal and the Total Harmonic Distortion (THD) thus produced is under the specified limit of IEEE.


I. INTRODUCTION
Multilevel Inverters (MLIs) have shown their efficacy in medium and high power applications due to better quality output waveforms, low rating switches, and several other factors, and thus pose as a replacement technology to the conventionally employed 2-level inverters. The main advantage of MLIs is the ability to synthesize voltages of low harmonic content. MLIs are broadly classified into symmetrical and asymmetrical topologies based on the voltage sources employed. If the sources are of the same value, then the configuration will fall under symmetrical category; The associate editor coordinating the review of this manuscript and approving it for publication was Jonghoon Kim . else, it will be asymmetrical. Symmetrical multilevel Inverters (SMLI) have been explored exhaustively in the literature since their introduction as Neutral Point Clamped MLI (NPMLI) in 1981 [1], as Flying Capacitor MLI (FCMLI) in 1992 [2], and, as classical cascaded H-Bridge (CHBMLI) inverter in 1996 [3]. These configurations were based on the concept of synthesizing the stepped waveforms of higher voltage levels from various DC sources of lower ratings. Diode Clamped (DCMLI) or FCMLI topologies employ a large number of switching devices, diodes and capacitors. On the other hand, the CHBMLI topology seems to be a promising one, but suffers from employment of a large number of DC sources and switches. Asymmetric Multilevel Inverters (AMLI), on the other hand, employ voltage VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ sources of different ratings, and are gaining popularity over the conventional symmetrical toplogies. One such topology is the Packed U-cell (PUC) [4], which has shown some promising results with fewer switching devices and a single power supply. For instance, for a 7-level voltage profile in a single-phase operation, FCMLI employs twelve switches and six capacitors; CHBMLI employs twelve switches and three DC sources; whereas, the PUC employs six switches, one DC source and one capacitor. This accounts for a dramatic difference in terms of cost, complexity, reliability and losses. A detailed review on SMLI and AMLI is contained in [5]. The basic topology of PUC was introduced in [6] as a modification to CHBMLI with two DC sources. Later in [4], this topology was converted into a single voltage source (forming the main DC-link) and one capacitor (forming the auxiliary DC-link) topology that can generate five or seven levels, depending on the DC-link to auxiliary DC-link voltage ratio. The hysteresis control of this converter producing a 7-level output voltage is considered in [7]. Six bands on the inverter output voltage-output current curve are utilized to control the output currents. Through the addition of one more cell, this topology is able to produce fifteen levels, as shown in [7]. Its effectiveness as a potential DC-AC as well as AC-AC converter is shown in [8]. Model predictive control (MPC) was applied on PUC in [9] to regulate the auxiliary DC-link voltage at the desired voltage level of V dc /3, so as to achieve the 7-level operation, simultaneously monitoring the active and reactive power flow by controlling the current flowing at the point of coupling of the converter and the grid. A sensorless control, in which the voltage of the auxiliary DC-link is regulated without the usage of a voltage sensor, is proposed for a 5-level PUC in [10], which is also extended to a 15-level PUC in [11]. A proportional resonant controller is designed for a 5-level PUC with an appropriate filter design for grid connection in [12]. Trabelsi in [13] has explored the finite control set MPC for the grid connected 7-level PUC. Evaluation of level-shifted and phase-shifted PWM (Pulse Width Modulation) techniques for a 7-level PUC is presented in [14]. A novel and less complex modulation strategy in which sensorless control of auxiliary DC-link voltage employs only two carriers is presented in [15]. An improved PUC is discussed in [16], wherein a 5-level PUC is enhanced to a 7-level PUC with boosted output voltages to 1.5 V dc , by addition of three more switches to the existing topology. Harmonics are minimized in the output voltage of a 5-level PUC by employing the modified angles which are obtained by genetic algorithm (GA) [17]. A modified PUC (MPUC) was introduced in [18], which was able to generate 7-level output voltage whose magnitude was more than the DC-link value.
Converters with a large number of output levels by cascading operation are being discussed. One such example is contained in [19]. This cascading operation requires 4 DC source and produces 31-level output. Recently, a 49-level AMLI was proposed by cascading two PUCs [20], in which two asymmetrical batteries and two capacitors were employed. These 49 levels were achieved by employment of 2 DC sources and 12 IGBTs only. In this structure, one of the PUC was modulated at high switching frequency, while the other was modulated at low switching frequency in step mode, thus enabling operation in a variable frequency control mode. The cascading of a 7-level PUC with DC link voltage ratio at 1 : 7 and the corresponding auxiliary DC-link voltage at the ratio of 1 : 3, will produce a 49-level output voltage. A detailed discussion on such cascaded PUCs is contained in [21]. Other AMLIs are presented in [22]- [26].
This work discusses the cascaded operation of a MPUC where the THD (Total Harmonic Distortion) in the output voltage is reduced by mitigating the major harmonic content by calculating the switching angles using a metaheuristic approach. Metaheuristic approaches are now being extensively employed in power electronic control algorithms [27]. The method applied here is the Genetic Algorithm (GA), which is a search based algorithm that is employed to find solutions to the optimization problems where it is difficult to find an extrema through generalized differential calculuseither due to nonlinear structure of the problem, or due to its complexity. The advantages of this method are a guaranteed convergence (provided that the objective function is correctly defined), and its simplicity [17]. An Artificial Neural 96868 VOLUME 8, 2020 Network (ANN) based controller is then employed which generates the optimum switching signals, and is trained according to the solutions obtained from the GA-based algorithm. Some of the applications of ANN in power electronics control can be seen in [28], [29]. The advantages of the 49-level inverter employed in this paper over the inverter discussed in [20] is that this converter produces a boosted voltage of 1.714 times the maximum voltage employed in the circuitry, which is 1.5 times the voltage achieved earlier. Moreover, the voltage ratios of both the converters suggest that for same voltage output, the DC voltage source of low value will be employed in this inverter.
The paper proceeds as follows. Firstly, the cascaded operation of PUCs and the corresponding generation of 49-levels is discussed. Then the expressions are developed that describe the angles of level transition. In section IV, GA-based optimization is discussed and implemented to determine the optimum angles that will result in the mitigated output voltage. In the fifth section, the ANN-based controller is discussed, whose optimal weights are derived according to the angles achieved in the section IV. Finally, the results are verified by simulation in the MATLAB/SIMULINK environment and on a 1 kW experimental setup.

II. 49-LEVEL OPERATION OF CASCADED MPUC
The Cascaded MPUC (CMPUC) inverter, represented in Fig. 1, is obtained by slight modifications of the cascaded PUC inverter [20]. Cascading of the MPUC inverter has a multiplicative effect, that results in a significant increase in output voltage levels. In order to obtain higher voltage levels, one solution is to modify the traditionally used inverters and the other solution can be cascading (as performed by the authors here). Cascading results in a large number of voltage levels, with minimal use of switches. In CMPUC, in order to obtain 49 levels, the constraint on the choice of input side voltages is given by (1): where V 1 and V 3 are the primary DC link voltages and V 2 and V 4 are the corresponding auxiliary voltage levels respectively. The main feature of this configuration is the ability to boost the voltage more than the maximum DC magnitude available, which is contrasted with the CPUC49 discussed in [20]. The maximum voltage that is achievable is: where, E is the magnitude of the highest voltage source.
The CMPUC inverter comprises anti-parallel switches (Q 1 and Q 4 , Q 2 and Q 5 , Q 3 and Q 6 , Q 1 and Q 4 , Q 2 and Q 5 , and Q 3 and Q 6 ). The anti-parallel switches work in complimentary mode (i.e. no two anti-parallel switches are turned on simultaneously). The output voltage levels of the CMPUC inverter are listed in table 1. The switching operation of the CMPUC is defined by: The output voltage (V o ) of the converter is defined as: where, the points a, b, c, d, e, f and g are shown in Fig. 1. The output voltage in terms of switching function is established as: Thus, V ag or V o can be calculated as; All the states of the converter, of which the descriptive waveform is shown in Fig. 2, are shown in Table 1. Some of the states are shown in Fig. 3.

III. SHM IN 49-LEVEL PUC
In Selective Harmonic Elimination (SHE), the energy of the low-order harmonics (that are omitted) is transferred to the higher-order harmonics,and thus the harmonics are not removed but replaced. Thus, it is better to opt for Selective Harmonic Mitigation (SHM) in which the harmonic content is minimized without the energy being transferred to higher frequency zone.

A. BASIC WAVEFORM AND THD ANALYSIS
The proposed 49-level waveform of the inverter shown in Fig 2 can be written as a combination of the step functions: As the waveform displays half-wave and quarter-wave symmetry, the Fourier expansion of the waveform will only contain odd harmonics, whose amplitude is represented as: Putting V (t) from (7) in the above equation will lead to: where, V 1 < V 3 < · · · < V 49 , and α 1 < α 2 < · · · < α 24 .
The Total harmonic distortion can be calculated by: 96870 VOLUME 8, 2020

B. THE OBJECTIVE FUNCTION
The controller is designed in two stages. First, the equations discussed below are solved by Genetic Algorithm (GA) resulting in the solution of angles that ideally should reduce the magnitude of harmonic content up to 49 th order to zero. This requires the formation of a fitness function for GA in terms of harmonic equations. Taking V m as the magnitude of the fundamental voltage required, the expression can be written as: and thus the fitness function f required for to be optimized is expressed as: where, k 1 , k 2 , · · · , k 49 are the weighted constants, with

IV. GENETIC ALGORITHM
Metaheuristic approaches have shown their efficacy in solving real-world optimization problems that are inherently nonlinear and their convergence with conventional techniques either consume a lot of time or do not occur at all. Natureinspired evolutionary techniques have evolved and are being implemented in a myriad of optimization applications. In this paper, a Genetic Algorithm (GA) is utilized to minimize the objective function that is derived in (12). The beneficial features of GA are: (i) the convergence is guaranteed (with certain tolerance band) and, (ii) the knowledge of derivatives is not required (as the iterations proceed with input-output mapping). The necessary steps are discussed in the following subsections and are supported by a detailed flowchart.

A. STEPS 1) DESIGN VARIABLES
The angles exhibited in Fig. 4 (from α 1 to α 24 ) are the same angels in (12). These angles form the variables and are to be corroborated in a manner defined in Fig. 2. For that a random population of 100 chromosomes is generated. Each chromosome is formed by 24 bytes, thus forming a length of 24 × 8 = 192 bits. The selection of the initial population is purely random. The weighted constants k 1 , k 3 , · · · , k 49 are such defined that k 1 > k 3 > · · · > k 24 , with k 1 = 1000. This prioritizes the harmonics that are to be eliminated.

2) SELECTION
The next step after the population is initialized, is to select two random parents on a purely probabilistic basis. In this paper the approach is based on the Roulette wheel criteria. The random selection of the parents ensures greater exploration of the solution domain. This also reflects in the results as a sudden surge, as shown in Fig. 6(b).

3) CROSSOVER
The crossover means blending of the genes in a particular manner. In this work the child's chromosome is formed by taking half of the bits from the first parent and the other half from the spouse. This is done for the whole 24 bytes of the chromosomes, as is exhibited in Fig. 4(a). N such children are produced, where ε is the current child as shown in Fig. 5.

4) MUTATION
Mutation basically defines the improvement in the child over the parent's behavior. So, in GA algorithms, this is achieved by flipping the values of the bits. Here, a single bit of each byte of the child's chromosome is changed, as exhibited it Fig. 4(b). Furthermore, it is ensured that the whole children population is not mutated. Instead, a random number µ is generated, and, if its value is less than a fixed number M (here 0.2), then only the child will be mutated. This is shown in Fig. 5.

B. METHODOLOGY
The population is arranged according to their fitness after its initialization. Then the 50 children (mutated and non mutated) are replaced with the existing population according to their fitness. If the fitness of the child is poorer than the already existing solution, this child is discarded. These iterations continue until a pre-decided number is not reached.
Here, the number of iterations is set to 5000, which is denoted by K in the flowchart. δ is the current iteration.  Table 2.

V. ANN BASED CONTROLLER
Artificial Neural Networks (ANN) are robust control structures that improvise and improve themselves by imitating human learning behavior. The human learning process is complex and difficult to explain in an affordable mathematical sense. Thus, it is required that the ANN must have a simple structure, and the process learning must also be simple; at least simple to understand. This section discusses a simple neural network based on multi-layer perceptron, in which the learning process is achieved by a back-propagation method which is based on error correction learning.

A. NEURAL NETWORK STRUCTURE
A basic neuron or a single-layer perceptron is shown in Fig. 7(a). The input data (x 1 , x 2 , · · · , x n ), also known as an 96872 VOLUME 8, 2020  epoch, is given to the summer, which behaves as the processor of the unit. The data fed to the nucleus is weighted with the weights defined in such a manner that the output is justified. The output of the processor is given to an activation function which generally is a threshold function. Here it is a binary threshold function. The function introduces the non-linearity in the control structure, which is best suited for power electronic conversion systems for its binary control. Fig 7(b) shows the actual neural network employed for the purpose here. It is a multi-layer perceptron (MLP) structure, and its weights can be determined offline by back-propagation of error or by the Lavenberg-Marquardt (LM) technique. The latter is employed here and discussed in the next subsection. The input to the finally trained ANN will be the voltage level desired and the network must be capable of generating the sought output in terms of 24 angles. The MLP has multiple layers of neurons, namely, the input layer (which forms the input to the system), the hidden layer, and the output layer. Generally, the number of neurons in the hidden layer is more than the input layer. This is done to increase the dimensionality of the network and make the data separable. The data which may not be distinguishable in n dimensions, might be separable in n − 1 dimensions. This introduces a new problem of training of such networks. Training requires the optimal setting of the weights of the network links. Researchers have done commendable job in offering solutions to such problems, some of which are also discussed in [30].

B. TRAINING OF THE NETWORK
The offline training of the ANN requires a negligible error between the desired result and the one given out by the network. In order to achieve this training, researchers have proposed various techniques based on classical and metaheuristic approaches. In this work a classical LM based technique is employed. The network for this problem has one input and 24 outputs. The hidden layer has 10 neurons. The generalized theory of this technique is discussed as follows. Let us consider a k th neuron of the p th layer that is connected to the n th neuron of the previous layer, and is to be updated. The overall error that has to be minimized for a particular output is given as: where i varies from 1 to k and j varies from 1 to n. The total error that is to be minimized can be expressed as the mean square error of all the errors for N data samples as: The weight updating algorithm for any weight is given by: where γ k = w p k,n , and β k and δ k are LM parameters which are defined as: where the gradient ∇E(γ ) is rewritten in terms of the Jacobian matrix as: The Hessian matrix ∇ 2 E(γ ) is defined as:  which can be further simplified as 2J (γ ) T J (γ ), and based on this approximation a simplified experssion for γ k+1 is given as: where µ is a variable that changes with every iteration as

C. IMPLEMENTATION OF THE NETWORK
The implementation of the trained network is shown in Fig. 8.
The parameters employed to train the network are chosen as shown in Table 3. It takes a few random iterations before a particular weight of the connection is set. The data for which the network is trained is derived through GA algorithm, whose results are shown in Table 2. The convergence stops as soon as the least mean square error is achieved. Once the network is trained, it is utilized as shown in Fig 8.

VI. RESULTS
The proposed Cascaded MPUC employed with ANN controller is simulated in MATALB/Simulink environment to validate its effectiveness. In this work, the open-loop 96874 VOLUME 8, 2020   operation of the converter with all voltage sources as DC supplies is considered. The parameters employed for this converter are discussed in Table 4. Figure 9 demonstrates the simulation results. Voltage stress across the switches of the converter shows that the stress is highest on the middle switches (that is across Q 2 in converter 1 and across Q 2 in converter 2). Correspondingly, the frequency of switching of these switches is the lowest (at fundamental frequency) with respect to other switches of the respective converter, that is the switching frequency of Q 2 and Q 4 in converter 1 and Q 2 and Q 4 in converter 2 will lowest of all the switches of the converter. The overall frequency behavior of the switches is as follows: with f Q 2 = 50 Hz. Also, the voltage stress across these switches vary as follows: These behaviors can be seen easily observed from Fig. 9(a). The same is true for the complimentary switches (that is Q 5 , Q 4 , Q 6 , Q 5 , Q 4 , Q 6 ).
In Fig 9(b), the individual output of each converter is shown. The output waveform of converter 1 is stepped and has a maximum voltage of 105 V, while the maximum value of the stepped output voltage of converter 2 is 15 V. From these results it can be inferred that the switches of converter 1 must be high-voltage rating low-switching frequency, whereas, the switches of converter 2 have to block a very small amount of voltage. Thus, GTOs can be employed for converter 1 and IGBTs or MOSFETs for the second. Here, however, for the sake of simplicity, IGBT modules (of two switches) have been employed. The overall converter output of 49 levels is shown in Fig 9(c). The output peak is 120 V, which is 1.714 times the maximum applied voltage, as discussed in (2). Figure 10 exhibits the experimental setup employed to validate the simulation results and has been obtained by slight modifications in the same prototype that was employed by the authors in [20]. The test rig consists of two MPUC units, DC power sources, RL load and an Xilinx Vertex-5 FPGA controller. Each MPUC unit consists of six switches and is connected to two DC sources. The fin side of the heat sink is cooled by using a fan. The experimental results are shown in Fig. 11. In Fig. 11(a), the output of each converter, that is a 7-level output, is exhibited. The output of converter 1 is a stepped wave of higher voltage rating and corresponds to the first wave of the Fig. 9(b); and the output of the second converter is also a stepped wave of lower voltage rating which corresponds to the second wave of Fig. 9(b). The final wave of Fig. 11(a) is the 49-level output voltage with the output 1.714 times the maximum DC-link voltage applied in the converter. The output voltage, its fundamental component and the load current are shown in Fig. 11(b). The THD of the output waveform is shown in Fig. 11(c), which exhibits 1.5%, and is under the prescribed limit given by IEEE.

VII. CONCLUSION
This paper discusses a boosted output 49-level asymmetrical inverter. A cascaded operation of two 7-level modified PUC inverters (MPUC) with a voltage ratio 1 : 7 between the main DC-links, and 1 : 2 within the sources of individual converters led to such operation. The converter operation with all its switching states and analytics was discussed in detail. In order to minimize the harmonics, switching angles were derived by employing a metaheuristic approach. The technique employed in this work was GA. 24 angles were generated for various output voltage conditions, with modulation index ranging from 0.6 to 1.1. The ANN was then trained using the LM back propagation technique for all these modulation index-angle combinations. This technique ensures minimum mean square error between the data set results and the practical results. Although, the objective function was set for harmonic elimination, the non-exact behavior of GA and ANN led to retainment of a certain amount, and instead resulted in harmonic mitigation. The converter results were then verified in simulation in MATLAB/Simulink , which were further validated on an experimental setup. The harmonic content of the voltage obtained was within the prescribed limit of IEEE. From 2016 to 2019, he served as an Assistant Professor with the Department of Electrical Engineering, Aligarh Muslim University. He has also worked as a Visiting Researcher at Qatar University, in 2018. He has authored two books chapters, articles in IEEE transactions and IET journals, and several international conference papers. His research interests include AC-AC and DC-AC power converter topologies, their analysis and modulation, and application in renewable energy systems connected to the grid and stand-alone systems.
Dr. Ali is a Life Member of SSI, India. He has delivered various lectures in national and international workshops.
MOHD TARIQ (Member, IEEE) received the bachelor's degree in electrical engineering from Aligarh Muslim University, Aligarh, the master's degree in machine drives and power electronics from the Indian Institute of Technology (IIT)-Kharagpur, and the Ph.D. degree from Nanyang Technological University (NTU), Singapore.
He is currently working as an Assistant Professor with Aligarh Muslim University, where he is leading a team of multiple researchers in the domain of power converters, energy storage devices, and their optimal control for electrified transportation and renewable energy application. Previously, he has worked as a Researcher at the Rolls-Royce at NTU Corporate Laboratory, Singapore, where he has worked on the design and development of power converters for more electric aircraft. Before joining his Ph.D., he has worked as a Scientist with the National Institute of Ocean Technology, Chennai, under the Ministry of Earth Sciences, Government of India, where he has worked on the design and development of BLDC motors for the underwater remotely operated vehicle application. He also served as an Assistant Professor at the Maulana Azad National Institute of Technology (MANIT), Bhopal, India. He has authored more than 100 research papers in international journals/conferences including many articles in IEEE transactions/journals.
Dr. Tariq was a recipient of the 2019 Premium Award for Best Paper in IET Electrical Systems in Transportation journal for his work on more electric aircraft and also the best paper award from the IEEE Industry Applications Society's (IAS) and the Industrial Electronic Society (IES), Malaysia Section-Annual Symposium (ISCAIE-2016) held in Penang, Malaysia. He is also the Founding Chair of IEEE AMU Sb and the Founder Chair of IEEE SIGHT AMU.
MOHAMMAD MERAJ (Member, IEEE) rece ived the bachelor's degree in electrical engineering from Osmania University, Hyderabad, India, in 2012, and the master's degree in machine drives and power electronics from IIT Kharagpur, India, in 2014. He is currently pursuing the Ph.D. degree in electrical engineering with Qatar University, Qatar. He has published more than 15 research articles in reputed IEEE and IET journals. His research interests include power electronics, impedance source-based converters, high gain DC-DC converter, PUC, electric drives, and renewable energy. He is currently a Professor of electrical engineering with Qatar University, Doha, Qatar. Since 1991, he was employed as a Lecturer with the Department of Electrical Engineering, AMU, where he served as a Full Professor, until August 2016. He has published widely in International journals and conferences. His research findings related to power electronics, variable speed drives, and renewable energy sources. He has authored/coauthored more than 390 research articles and two books and three chapters in two other books. He has supervised several large Research and Development projects worth more than eight million USD. He has supervised and co-supervised several Ph.D. students. His principal area of research interests area smart grid, complex energy transition, active distribution networks, electric vehicles drive train, sustainable development and energy security, and distributed energy generation.
RIPON K. CHAKRABORTTY (Member, IEEE) received the B.Sc. and M.Sc. degrees in industrial and production engineering from the Bangladesh University of Engineering and Technology, in 2009 and 2013, respectively, and the Ph.D. degree in computer science from the University of New South Wales (UNSW Australia), Canberra, in 2017. He is currently a Lecturer of system engineering and project management with the School of Engineering and Information Technology, UNSW Australia. He has written two book chapters and over 45 technical journal and conference papers. His research interests include a wide range of topics in operations research, optimization problems, project management, supply chain management, and information systems management.
MICHAEL J. RYAN (Senior Member, IEEE) is currently the Director of the Capability Systems Centre, University of New South Wales, Canberra. He lectures and regularly consults in a range of subjects including communications systems, systems engineering, requirements engineering, and project management. He is a Co-Chair of the Requirements Working Group, International Council on Systems Engineering (INCOSE). He is the author or coauthor of twelve books, three book chapters, and over 250 technical articles and reports. He is a Fellow of Engineers Australia, International Council on Systems Engineering, and Institute of Managers and Leaders. VOLUME 8, 2020