A 17.6-nW 35.7-ppm/°C Temperature Coefficient All-SVT-MOSFET Subthreshold Voltage Reference in Standard 0.18-μm N-Well CMOS

This paper presents a low-power, low-voltage, and low-temperature-coefficient (TC) MOSFET-only subthreshold voltage reference circuit based on a standard 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> n-well CMOS process. The circuit consists of two novel current generators and an I/V conversion circuit with temperature compensation. Under the control of a proposed pMOS-bulk-driven (PBD) temperature compensation circuit, two pMOSFETs operating in a linear region act as resistors with different TCs and can be used for PTAT and CTAT current generation. Owing to the PBD technique and the subthreshold operating method, these two current generators and the I/V conversion circuit can operate at low voltage. The proposed reference circuit is realized with only standard <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {TH}}$ </tex-math></inline-formula> (SVT) MOS devices. The measurement results show that it can operate at a minimum supply voltage of 0.5 V. The line sensitivity is 0.09% for supply voltages between 0.5 and 1.8 V. The PSRR measured at 100 Hz is 51.8 dB. A measurement of 20 samples indicates that the average TC is 35.7 ppm/°C across a temperature range of −40 to 85 °C. The proposed circuit consumes 17.6 nW from a 0.5-V power supply and occupies an active area of 0.0092 mm<sup>2</sup>.


I. INTRODUCTION
In the future, billions of smart devices with sensing and processing capabilities will be connected to the Internet with the continuous development of Internet of Things (IoT). Devices with the above-described functions are called IoT nodes and will preferably be energy efficient, miniaturized, have a long life cycle, and be low cost [1]- [3]. In this scenario, low voltage digital-assisted system-on-chips (SoCs) with MOSFETs operating in the subthreshold region are very attractive. These benefit from a low supply voltage, and the power consumption can be reduced for digital circuits. However, the situation is not the same in analog circuit design. Analog circuits with a lower supply voltage may consume much more power and chip area to achieve competitive noise performance and linearity. More-over, MOS transistors biased in the subthreshold region are more sensitive to variations in the process, voltage, and temperature (PVT) [4].
The associate editor coordinating the review of this manuscript and approving it for publication was Jenny Mahoney. Therefore, it is challenging but urgently needed to develop suitable techniques for low-supply analog circuits.
As one of the key analog circuits, the voltage reference generator is widely used in various applications to generate a DC voltage that is insensitive to PVT variations. Conven-tional bandgap references (BGRs) require relatively high supply voltages (> V BE + V DS ) and consume significant power (at the µW level) [5], [6], where V BE is the base-emitter voltage of the parasitic vertical bipolar junction transistor (BJT), and V DS is the drain-source saturation voltage of a MOSFET. This cannot satisfy the requirement of low-voltage applications. Moreover, a survey of the literature reveals that resistor compensation schemes are typically utilized to realize low-temperature-coefficient (TC) voltage references (VRs) [6]- [11]. However, the usage of resistors can increase the chip area, cost, and noise coupled from the substrate [12]. From the research on the temperature characteristics of MOSFETs in [13], it was found that the gate-source voltage of a MOSFET with a fixed drain current bias can decrease with temperature. VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ Several prior works reduced the supply voltage by using V GS of a diode-connected MOSFET to replace the high V BE of a BJT. A MOSFET-only subthreshold VR with no amplifiers was presented in [14]. It can operate with a minimum supply voltage of 0.45 V and achieves superior line sensitivity by using a special twin-well CMOS process. The subthreshold VR circuit in [15] can operate with a 0.25-V supply voltage. Owing to the usage of an additional low-voltage comparator and charge-pump circuit, the circuit consumes considerable power. The structure in [16] with stacked pMOS transistors reduces the quiescent current of the circuit but does not leave enough headroom for a supply voltage reduction. To achieve low power, small area, and low supply, the two-transistor VR in [17] avoids amplifiers, saturated devices, and resistors, but has both a native device and thick oxide device. This needs trimming to address the process sensitivity of the TC and output voltage. The subthreshold VRs presented in [18] and [19] use switched-capacitor circuits for quiescent current reduc-tion. However, the operating temperature range is restricted owing to the leakage current of the switches [20]. This paper presents a novel all-MOSFET VR generator realized in standard 0.18-µm n-well CMOS. It incorporates both the pMOS-bulk-driven (PBD) temperature compensation technique and the subthreshold operating method, leveraging each other's strength to achieve low TC and low power under a low supply. Two current sources with opposite TCs are generated by controlling the bulk of the pMOS transistor with different temperature compensation circuits. A low-TC output voltage is finally obtained after an I/V conversion with further temperature compensation. Different from [14], the proposed VR with PBD technique does not require any bulk-driven nMOS transistors and can be realized in a standard n-well CMOS process. This paper begins by describing the detailed circuit design of the proposed VR generator in Section II. Design considerations are provided in Section III. Measured results are summar-ized and compared with those of previous works in Section IV. Finally, conclusions are given in Section V. Fig. 1 shows the operation of a pMOS transistor in a weak inversion region. The model assumes that 1) the channel in the MOSFET is so long that the horizontal and vertical electric fields are approximately independent and the channel-length modulation effect is negligible, and 2) the source-drain voltage of the pMOSFET is sufficiently higher than the thermal voltage at room temperature. Under these requirements, the I-V characteristic of a pMOS transistor operating in a weak inversion region can be described as [21]

II. CIRCUIT ARCHITECTURE
For |V DS | > 0.1 V, the drain current I D is almost indepen-dent from |V DS | and can be approximately given by [9] where I 0 is called the pre-exponential factor, K is the aspect ratio (W/L) of the pMOSFET, µ p is the carrier mobility, C OX is the gate-oxide capacitance per area, V T (= kT /q) is the thermal voltage, k is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, and V THP is the threshold voltage of a pMOSFET. η is the subthreshold slope factor. From (3), the gate-source voltage of the MOSFET for a given drain current can be described as In this equation, the threshold voltage of the MOSFET can be described as [22] where P D,poly is the doping concentration of acceptor atoms in the P+ poly gate, and N A is the doping concentration of acceptor atoms in the substrate. n i are the intrinsic carriers, ε si is the relative dielectric constant of silicon, and Q' SS stands for the constant of the surface-state charge. As described in [23], we can substitute (5) in (4) and take the derivative of |V GS | with respect to T . The TC of |V GS | can be approximately written as which indicates that |V GS | decreases with an increase in temperature. In general, P D,poly is much greater than N A . Fig. 2 shows the simulated variation of V SG, M1 vs. temperature at different bias currents. When the drain current is at a nanoampere level, the change rate of V SG with temperature is almost invariable if the drain current experiences a slight change. Therefore, two currents at the nanoampere level that are proportional-to-absolute temperature (PTAT) and complementary-to-absolute temperature (CTAT), respectively, are generated with the temperature performance of the resistance of the pMOSFET controlled by the bulk-driven technique.

A. PTAT CURRENT GENERATOR
The Beta multiplier is a simple bias-current generator [14], [22]. It can achieve relatively good line sensitivity under a standard supply voltage. However, its temperature coeffi-cient is insufficient. The line sensitivity can also deteriorate under low supply voltages because the generated current by the MOSFET in the subthreshold region varies with its V DS . Fig. 3 shows the proposed PTAT current generator. We use a self-cascode pMOS transistor to replace the resistor in the Beta circuit. According to [24], it can achieve small area and is appropriate for low voltage design. A PBD circuit with temperature compensation is proposed as shown in Fig. 3. It can bias the bulk of M5 for threshold voltage reduction. Moreover, the thermal slope of the PTAT drain current of M5 can also be easily adjusted by this circuit.
In Fig.3, the resistance of M5 in linear region can be expressed as [14] where V GS is the gate-source voltage. The drain current of M5 can be written as The threshold voltage V TH is an important parameter that is sensitive to temperature variations. It increases as the tem-perature decreases owing to Fermi-level and bandgap energy shifts. V TH has a linear relationship with the temperature over a wide range of temperatures for long-channel devices. According to [25], if we take body effect into consideration, the expression of V TH can be given by where V TH0 is the threshold voltage without the body effect, γ is the body-effect constant, and V SB is the source-bulk voltage of a MOSFET. Therefore, we have In Fig. 3, V SB,M5 can be expressed as From (5) and (9), regardless of the V SB , we have To determine the current variation of M5 with temperature, we differentiate (8) with respect to T and obtain To generate a current with a positive TC, [x 1 + y 1 + z 1 ] in (16) is expected to be greater than zero. It can be observed that the thermal slope of I P is a function of parameters that are marked using a 1 , b 1 , and c 1 . From (4), (8), and (9), we can express a 1 and b 1 , respectively, as bellow. According to the temperature dependency of the carrier mobility described in [7], [13] and [21], c 1 can be given by where T 0 is the room temperature. The value of m is about 1.5 for an ordinary MOSFET.
In (17), we provide an appropriate overdrive voltage for M5, and we can have We also make K 6 1 and ensure that For (17) and (18), if we provide appropriate aspect ratios for K 1 , K 2 , K 9 , and K 10 , we can get Since c 1 is a negligibly small value, we can change (16) to From (24), it is found that the current flowing through M5 will increase with temperature. Simulations were performed on M5 under a supply voltage of 0.5 V over a temperature range of −40 to 85 • C. The simulation results are shown in Fig. 4. It is indicated that the resistance of M5 in Fig. 3 decreases with an increase in temperature. The variations in V SD,M5 and V SG, M5 -|V TH,M5 | with temp-erature can also match the above theoretical analysis.
From (9), we get To determine the current variation of M5 in Fig. 5 with temperature, we differentiate I C in (25) with respect to T and obtain In a similar manner as that in (16), [x 2 + y 2 + z 2 ] in (29) is expected to be less than zero to obtain a current with a negative TC. The thermal slope of I C can be described as a function of parameters that are marked using a 2 , b 2 , and c 2 . c 2 is same as c 1 in (19) and we express a 2 and b 2 as follows:  − η In the process used, η is about 1.60 for pMOSFETs. We can set an appropriate K 8 to ensure For (30), if we provide appropriate aspect ratios for K 1 , K 2 , K 6 , and K 8 , we can get We provide the overdrive voltage for M5 below: Since c 2 is same as c 1 , we see from (19) that it is a small value. From (28), (29), and (34), if we provide appropriate K 8 , K 6 , K 2 , and K 1 to make then, we can get From (37), it is found that the current flowing through M5 in Fig. 7 decreases with an increase in temperature.
Simulations are also performed to M5 under a supply voltage of 0.5 V over a temperature range of −40 to 85 • C. The simulation results are shown in Fig. 6. It is indicated that the resistance of M5 in Fig. 5 increases with temperature. The variations in V SD,M5 and V SG,M5 −|V TH,M5 | with temperature can also match the theoretical analysis.

C. I/V CONVERSION CIRCUIT WITH TEMPERATURE COMPENSATION
The proposed VR is expected to generate a reference voltage that is almost independent of the temperature. Although we can obtain a low TC current, as shown in Fig. 7, with a combination of the proposed PTAT and CTAT current generators, it is still not possible to directly achieve an expected low-TC reference voltage with this generated current flowing through an active resistance device. Thus, we present an I/V conversion circuit as shown in Fig. 8. It can compensate the variation in the output voltage with temperature. Different from that in [14], the PBD technique enables it operate in a standard n-well CMOS. Moreover, necessary effort was made on matching these two branches in Fig. 8, aiming to reduce the output error caused by process variation as possible.
All of these MOS devices are in the subthreshold region so they can operate at low voltage. From Fig. 8, V B and V SB for M5, M6, and M7 can be given by Using (4), (9), and (39) and assuming that η is a constant value in the process used, the output voltage V REF can be VOLUME 8, 2020 approximately written as By setting the same W /L and current for M4, and M8, and making V SG4 = V SG8 , we have Roughly, assuming that 3µ p = µ n and V TH0,M8 = |V TH0,M5 |, (41) can be approximated as Differentiating (42) with respect to temperature, we can have where φ is the first-order slope of V TH, M1 , equivalent to −8.67 × 10 −4 V/ • C. Because M1 is designed with a large aspect ratio, the first-order slope of |V GS,M1 | is smaller than ô. Solving for ∂V REF /∂V T = 0, we arrive at the expression According to (44), the aspect ratios of M5 and M8 in Fig. 8 can be determined for temperature compensation. Fig. 9 shows the entire circuit of this subthreshold voltage reference. In Table 1, the parameters of the used process and the aspect ratios for all of these MOS devices in this proposed voltage reference circuit are provided.

III. DESIGN CONSIDERATIONS A. CONSIDERATIONS OF SIZE FOR SEVERAL KEY DEVICES
1) The operational amplifier (OA) is realized without a tail current. The structure selected for these two OAs can accommodate the low-supply-voltage requirement.
The structure is also expected to achieve enough gain and a low offset. The area W × L of the devices in these OAs can affect the matching performance. Since long-channel devices have relatively low threshold voltages, we design all these MOS devices with L MAX . The input offset of the OA is reduced as much as possible by using long-channel devices and matching these two branches. 2) M3 and M22 in Fig. 9 operate in the triode region.
They are expected to act as resistors with opposite TCs. The channel length is inversely proportional to the threshold voltage and directly proportional to the impedance. M3 and M22 are both designed with an aspect ratio of W MIN /L MAX to accommodate a low supply voltage and low current. At room temperature, the drain current of M22 is 2 nA, while the corresponding current of M3 is 3.5 nA. The channel widths of M4 and M23 in Fig. 9 are carefully determined for a better temperature compensation effect on the generated currents. 3) For the output stage circuit, temperature compensation is realized by introducing the difference between two temperature-dependent variables, V GS,M30 and V GS,M31 , into the bulk of M36. The presented I/V conversion circuit consists of two current summation circuits. They are not strictly symmetrical. The value of V BS,M36 should not be too small in order to avoid turning on the bulk-source junction. The width of M30 is four times that of M36. The pMOS device in each branch has been split to three devices with same aspect ratio in parallel for matching optimization, output error reduction and to achieve better TC. Taking mismatch and process variation into consideration, 1000-times Monte Carlo simulation results show that about 3 ppm/ • C TC improvement can be achieved by splitting these two pMOS devices in Fig. 8.

B. MINIMUM SUPPLY VOLTAGE
In the proposed voltage reference circuit, except for M3 and M22, which operate in the triode region, all the other devices are operated in the subthreshold region. The supply voltage should not only keep all these transistors in the sub-threshold region but also ensure that the I D of these transistors is almost irrelevant to their V DS . The V DS of each MOS transistor operating in the subthreshold region should be greater than 0.1 V. Hence, we have The 13 items in the brackets of (45) represent the 13 branches of this proposed subthreshold reference. The source-gate voltage of M22, V SG, M22 , should be larger than its |V TH | to make it operate in the triode region. Owing to the superposition of V DS,M28 and |V GS,M27 |, the V BS of M22 is not low enough, and |V TH,M22 | stays at a relatively high value. Since a large |V GS,M22 | is needed to make M22 operate in a triode region, the branch constructed with M22, M23, and M24 mainly restricts the supply-voltage reduction. The simulated value of |V TH,M22 | is 350 mV. The V DS of M24, which operates in the subthreshold region, is about 0.1 V. Therefore, the required minimum supply voltage is 450 mV. Since the threshold voltage can vary with temperature, a supply voltage no less than 500 mV is applied conservatively in our design.

C. SENSITIVITY TO SUPPLY-VOLTAGE VARIATIONS
To determine how the fluctuation of the power supply affects the subthreshold voltage reference, we start with (41). It shows that the relationship between the output voltage and the variation in the power supply depends mainly on V GS,M1 in Fig. 8. According to (4), we can get Then, we evaluate the sensitivity of this proposed VR to the supply voltage by taking the derivative of V REF in (41) with respect to V DD and substituting (47) into it. Thus, we have (48) VOLUME 8, 2020 From (48), the proposed voltage reference will be more robust against the fluctuation in V DD if the currents flowing into the I/V conversion circuit are insensitive to it. Actually, Beta circuits usually have good line sensitivities. Since the proposed circuit operates in the subthreshold region and its line sensitivity can deteriorate under a nanoampere current, we use two simple operational amplifiers in the presented current generators to increase the robustness of the generated currents against the fluctuation in V DD . Fig. 10 shows the simulated current variations of I sum in Fig. 9 when the supply voltage ranges from 0.5 V to 1.8 V. It can be found that the current variation is significantly reduced after using these two operational amplifiers.

D. SENSITIVITY TO PROCESS VARIATIONS
As shown in (42) and (43), the reference voltage and its TC are both η-dependent. η depends on the gate oxide and depletion layer capacitances, so it is determined by the process [26]. The values of η almost vary equally for same type MOSFETs with certain sizes. In [14], two nMOSFETs are connected in series, and the process variation is mainly reduced by changing the threshold voltage of the bulk-driven nMOSFET. This structure can only be used in a special twin-well CMOS process.
In order to reduce the process manufacturing cost and improve the applicability of the proposed circuit, bulk-driven pMOSFETs are used instead of bulk-driven nMOSFETs in the proposed VR. Special twin-well process is no longer needed as we only use pMOSFETs with different bulk voltages. Fig. 9 shows that the reference voltage of the proposed VR is associated with the threshold voltages of M36 and M37, where M36 is a bulk-driven pMOSFET and M37 is a nMOSFET. With their connection shown in Fig. 9, the size of M36 differs greatly from that of M37. Hence, there will be slightly different changes in their threshold voltages with process variations due to different variations of η for M36 and M37. Since the I/V conversion output stage utilizes two types of MOS devices for temperature compensation, its robustness against process variation is degraded to some extent.

IV. MEASUREMENT RESULTS
The proposed subthreshold voltage reference is implement-ed in a standard 0.18-µm CMOS process. A microphoto-graph of the fabricated chip is shown in Fig. 11. The occupied active area for a single chip is 196 µm × 46.6 µm. The post-layout simulation shows that the TC of this proposed VR is 26.7 ppm/ • C at a 0.5-V supply voltage. Twenty chips of the proposed VR were measured. These measured output reference voltages were in the range of 148 mV to 161 mV, as shown in Fig. 12. With the temperature ranging from -40 to 85 • C, the minimum and maximum output variations of these measured chips with a 0.5-V supply were 0.4 mV and 0.9 mV, respectively, which means that the TC ranges from 21 ppm/ • C to 86 ppm/ • C. Fig. 13 shows the TC distribution of 20 tested samples. The average TC of the output reference voltage is 35.7 ppm/ • C.
The average reference voltage of a randomly selected chip measured at 0.5-V supply voltage is 151.91 mV over the temperature range from −40 to 85 • C. This chip was also measured under different supply voltages. Fig. 14 shows the power supply current of the proposed VR vs. the temperature under different supply voltages. Since the threshold voltage of MOSFET decreases with temperature, the current of the reference under a constant supply voltage increases with temperature. Operated at a 0.5-V supply voltage, the measured  current varies from 28.2 nA to 37.6 nA when the temperature ranges from −40 to 85 • C. The power dissipation of the presented voltage reference circuit with a 0.5-V supply voltage is 17.6 nW at room temperature. It varies from 13.6 nW to 19.7 nW when the temperature ranges from −40 to 85 • C. The supply current also increases slightly with the supply voltage. At room temperature, the supply current increases from 35.2 nA to 48.3 nA when the input voltage ranges from 0.5 V to 1.8 V. When the temperature is 85 • C, the measured supply current at V DD = 0.5 V is 41.3 nA, while it is 55.1 nA at V DD = 1.8 V. Fig. 15 shows the measured V REF of four randomly selected samples vs. the power supply at room temperature. With the supply voltages ranging from 0.5 V to 1.8 V, the measured line sensitivities are 0.1%, 0.086%, 0.03%, and 0.15%, respectively. The average line sensitivity of this voltage reference is 0.09%. As shown in Fig. 16, the PSRR is −51.8 dB at 100 Hz, while it is −40.1 dB at 1 kHz.
The performance of this proposed voltage reference is summarized and compared with those of previous works in Table 2. Owing to the proposed temperature compensation technique, the proposed VR achieves a much lower TC than in [4], [14], [17], [18], and [26]- [29]. To avoid deterioration in the temperature characteristic of the output reference, it does not use any additional circuit for trimming its process variation. It should be mentioned that the proposed VR does  not use a resistor, capacitor, BJT, or special active devices. It is realized with only standard V TH (SVT) MOSFETs in standard n-well CMOS process and occupies the smallest area compared to all of the competitors except [17], [27] and [29] in Table 2, while featuring robustness against supply variations. The simple operational amplifier without a tail current source that we used does not obviously increase the circuit complexity and power dissipation. The proposed VR circuit consumes less current than most of the other designs in Table 2. Implemented in a twin-well CMOS process, the design reported in [14] achieves better line sensitivity and consumes less power. The presented circuit with pMOS-bulk-driven technology does not require the twin-well CMOS process. Since it is an all-SVT-MOSFET voltage reference and no special device is utilized, if the model library provided is accurate, it is also very promising to perform well in other standard 0.18-µm CMOS process.
According to [27] and [28], we also use FoM ( Figure-   in this used process vary greatly with temperature, especially at high temperature, the temperature performance of the proposed VR deteriorates when the temperature is over 85 • C. Fig. 17 shows the comparison between the proposed all-SVT-MOS VR with published low power subthreshold voltage references. It has been shown that the proposed VR features very competitive FoM. Although [17], [27], and [29] present higher FoMs, [17] and [29] use both native and thick oxide devices, and [27] utilize both standard and high V TH devices.

V. CONCLUSION
This paper presented a pMOS-bulk-driven temperature compensation technique for a subthreshold voltage reference. Using novel PTAT and CTAT current generators and an I/V conversion circuit with temperature compensation, a voltage reference was implemented with only SVT-MOS devices in a standard 0.18-µm n-well CMOS process. The measurement results showed that the circuit achieves low TC with low power and a miniaturized chip area. The measured results have indicated that a competitive line sensitivity and PSRR were achieved. The circuit is suitable for applications that require low power and small size.