A Multi-Floor Arrayed Waveguide Grating Based Architecture With Grid Topology for Datacenter Networks

This paper proposes a grid topology based passive optical interconnect (POI) architecture that is composed of multiple floors of arrayed waveguide grating routers (AWGRs) to offer high connectivity and scalability for datacenter networks. In the proposed POI signal only needs to pass one AWGR, and thus can avoid the crosstalk accumulation and cascaded filtering effects, which exist in many existing POI architectures based on cascaded AWGRs. Meanwhile, due to high connectivity, the proposed grid topology based POI also has the potential advantage of high reliability. Simulation results validate the network performance. With a proper node degree, the proposed grid topology can achieve acceptable blocking probability. Besides, steady performance is kept when the number of floors increases, indicating good scalability of the proposed POI.

grating AWG) [12]- [17] and has been found to offer better scalability than the latter one [18]- [20] that typically needs high insertion loss devices, like optical power combiners/splitters. LIONS [12] and H-LIONS [13] use cyclic AWGs and wavelength-tunable transmitters to achieve optical interconnection. The cyclic AWGs with multiple input and output ports are also referred to as AWG routers (AWGRs), performing a key role for wavelength routing. [14] proposes a modular scheme to construct the AWG based interconnection network, which possesses a much lower cabling complexity and improved scalability and reliability. In the cascaded AWG-based (CA)-POI [15] and its extended version [16], two cascaded stages of wavelength routing devices/modules are employed to offer multiple connections. [17] proposes a novel WDM ring network by exploring spatial wavelength reuse of 2 × 2 AWGRs for datacenters. However, these architectures have limited connectivity. For instance, in [15], [16] as there is only one wavelength routing module placed at the top stage, the number of directly connected links between any two bottom wavelength routing modules is limited to one. Once such a link is occupied or failed, the connection has to pass the other nodes, resulting in the occupation of extra resources and increasing the risk of blocking the upcoming requests.
To further enhance the connectivity, a POI architecture with the heatsink topology capable of supporting multiple concurrent connections in datacenter networks has been proposed [21]. Both the bottom and top stages in the heatsink based POI architecture contain multiple AWGRs, allowing several directly connected links between any pair of bottom AWGRs. However, a connection between a pair of end nodes that are associated with different bottom AWGRs needs to pass several AWGRs, which may significantly degrade the quality of transmission due to the crosstalk accumulation and cascaded filtering effects.
In this regard, in this paper we propose a novel AWGRbased POI architecture that can offer high connectivity and scalability while maintaining transmission quality by avoiding passing too many AWGRs. The proposed approach is referred to as grid topology based architecture, which is composed of multiple floors and can be extended easily. In this paper, we concentrate on network performance and investigate the blocking probability of the proposed grid topology based architecture. Here the blocking probability is defined as the number of the blocked connection requests over the total number of connection requests. The simulation results show that the blocking probability is determined by many factors, including proper routing and wavelength assignment (RWA) algorithms, node degree, the number of floors, and the size of AWGR. A guideline is provided on how to properly configure the grid topology based POI to optimize the blocking probability.
The remainder of the paper is organized as follow. Section II depicts the architecture of the proposed grid topology based POI and discusses the characteristics of the physical architecture and logical topology. Section III presents the network performance of the grid architecture by exploring the impacts of the implemented RWA algorithms and system configurations. A performance comparison with the heatsink topology is also given in this section. Finally, conclusions are drawn in Section IV.

II. GRID TOPOLOGY BASED POI ARCHITECTURE
In this section, we investigate the grid topology based POI from two aspects: the physical architecture and the logical topology. The physical architecture part depicts the connection rules among the connected nodes, while the logical topology part shows the routing possibilities of the grid topology.

A. PHYSICAL ARCHITECTURE
The proposed architecture can be applied in different tiers in datacenters, which means the end nodes connected can represent server, rack or cluster. To illustrate our idea, in this paper we consider the end node represents the server and each AWGR is used to connect servers within a rack. The grid topology consists of several floors, each of which comprises a group of racks. One rack is composed of an AWGR that interconnects different servers. Fig. 1 shows the overall physical architecture of the grid topology based POI. The three floors are sequentially arranged from bottom to top. There are 2N racks on each floor. Rack(i, j) denotes the jth (1 j 2N ) rack on the ith floor. Each rack has 2N servers. The kth (1 k 2N ) server in Rack(i, j) is denoted as Server(i, j, k). The first half of the servers (i.e., 1 k N ) in every rack on the ith floor are connected to the second half of the servers (i.e., N < k 2N ) in every rack on the (i + 1)th floor by a specifically defined ''interconnection method'', as shown in Fig. 1. In such a way, more floors (i.e., floors of racks) can be easily added either on top or at the bottom of the architecture, thereby providing good scalability for the datacenter networks. Fig. 2 shows a detailed internal structure of Rack(i, j) in Fig. 1. Without loss of generality, Server(i, j, k) in Rack(i, j) is used as an example for a detailed description of the connections in Fig. 2. The server has an optical interface (OI) including two sets of transceivers. The receiver r and transmitter t are responsible for the intra-rack connections (e.g., the red line in Fig. 2), while receiver R and transmitter T are responsible for the inter-rack communications (e.g., the yellow and blue lines in Fig. 2). There are two fourport optical circulators (OCs), denoted as the left OC and right OC, respectively, appended to the OI of the server. For the left OC, the 1st-4th ports are connected to the transmitter t, port k of the AWGR, the 3rd port of the left OC of Server (i , j , k ), and the receiver R, respectively. For the right OC, the 1st-4th ports are connected to the transmitter T , the 2nd port of the right OC of Server(i , j , k ), port k of the AWGR, and the receiver r, respectively. Here the value of i , j , and k can be calculated by using (1) and (2). For the first half servers in the rack (i.e., 1 k N ), an additional fiber Bragg grating (FBG) with a specific reflection wavelength is appended at the 3rd port of the left OC of Server (i, j, k). The ''interconnection method'' in Fig. 1 represents the connection rules between the servers across the floors, which are expressed by (1) and (2) corresponding to the first half (i.e., 1 k N ) and the second half servers of each rack (i.e., N < k 2N ), respectively. where L is the total number of floors of the grid topology, and a equals to j − k + 1.
The intra-rack connection can be established by sending signals from the transmitter t via the left OC at the source server to the receiver r at the destination server through its right OC (e.g., the red line in Fig. 2). The wavelength of the intra-rack connection is determined by the wavelength routing table of the AWGR on the same rack. For inter-rack connections in the architecture, there are six different cases, which are summarized in Table 1. The rack on one floor can be connected to the racks on the same floor or on the adjacent two higher/lower floors. Fig. 3 illustrates the six possible inter-rack optical paths. In the case ''k N '', the source Server(i, j, k) belongs to the first half of the racks at the ith floor, and in the case ''k > N '', the source Server(i, j, k) belongs to the second half of the racks at the ith floor.
For cases I-IV (as shown by the yellow and green lines in Fig. 3.), the signal passes through the right OC of the source Server(i, j, k), the right OC of Server(i , j , k ), the AWGR in the Rack(i , j ), the left OC of Server(i , p , q ), a FBG and the left OC of the destination server Server(i, p, q), sequentially. The signal finally arrives at the receiver R of Server (i, p, q). As shown in Fig. 3, for case I, the signal passes through the right OC of the source Server(i, j, k), the right OC of Server(|i + 1|, j1, k1), the AWGR in the Rack(|i + 1|, j1), the left OC of Server(i , j2 , k2 ), a FBG and the left OC of the destination server Server(i, j2, k2), sequentially. The signal finally arrives at the receiver R of Server (i, j2, k2).
For cases V-VI (as shown by the red lines in Fig. 3), the signal passes through the right OC of the source Server (i, j, k), the right OC of Server(i , j , k ), the AWGR in Rack (i , j ) and the left OC of the destination Server(i , j , q) in Rack(i , j ), sequentially. Then the signal is reflected by a FBG and enters the left OC of the destination server again and is detected by the receiver R. For instance, as shown in Fig. 3, for case V, the signal passes through the right OC of the source Server(i, j, k), the right OC of Server(|i + 1|, j1, k1), the AWGR in Rack(|i + 1|, j1), and the left OC of the destination Server(|i + 1|, j1, k1) in Rack(|i + 1|, j1) sequentially. Then the signal is reflected by a FBG and enters the left OC of the destination server again and is detected by the receiver R. Note that for a specific server, there only exists three possible optical paths for inter-rack connections, which depend on whether the server belongs to the first or the second half of servers in the rack. For the first (second) half of servers in the rack, they can be connected to the first (second) half of servers of other racks in the same floor, servers in the racks that are one floor higher (lower), and the second (first) half of servers in the racks that are two floors higher (lower).
For all cases, the signal passes through the OC four times but the AWGR only once, and then goes through or is reflected by the FBG once. Nevertheless, the wavelength requirement varies for different cases. For cases I-IV, the wavelength that is routed by the AWGR from the ingress port k to the egress port q shall not coincide with the reflected wavelength of the FBG. On the contrary, for the inter-rack connections between two adjacent floors that can be represented by cases V-VI, they require the matching of the reflected wavelength of the FBG and the wavelength that is routed by the AWGR from the ingress port k to the egress port q. The wavelength assignment can be obtained according to the wavelength routing principle listed in Tables 5 and 6 in APPENDIX. Though the constraints on wavelength exist in the proposed architecture, the proposal is still able to provide multiple concurrent connections. The optical paths of any type of interconnects pass one AWG, one FBG and several circulators. With proper design (e.g., athermal packaging, integrated temperature controller, etc.), the off-the-shelf AWG and FBG products can have high wavelength stability against the thermal variation within a large operating temperature range [22], [23]. The reflection passbands of all FBGs are the same as the wavelengths on the diagonal of the wavelength routing table of the AWGR (see Table 5 in APPENDIX). As both the off-the-shelf FBG and AWGR can be made according to the ITU grid with high wavelength accuracy, it is of high feasibility to align their spectrum. With the good matching of the AWGR and FBG passbands [22], [23] and passing the AWGR only once, crosstalk accumulation, which is recognized as a dominating limiting factor in the previous cascaded AWG based schemes (such as that in the heatsink topology [24]), can be avoided without compromising its rich connectivity advantage offered by the multiple concurrent connections. Fig. 4 shows the logical connection of the grid topology on the same floor. The AWGR size is chosen to be 4 as an example. The large dashed circles indicate the racks from Rack(i, 1) to Rack(i, 4), where i (i = 1, 2, 3 . . .) indicates the index of the floor. The small solid circles in the large dashed circles indicate the servers from Server(i, j, 1) to Server(i, j, 4), where j (j = 1, 2, 3, 4) indicates the index of the rack. There are three different colors for the links: blue, red, and black. The color of the links represents the wavelength assigned. The connection inside the large dashed circle shows the intra-rack transmission and the connection between the large dashed circles shows the inter-rack transmission on the same floor. Fig. 5 and Fig. 6 show the logical topology between the different floors of the grid topology.  floor is connected to the first half of the |i − 1|th floor (the blue lines in Fig. 6) and the first half of the |i − 2|th floor (the red lines in Fig. 6), respectively.

B. LOGICAL TOPOLOGY
For the 4 × 4 AWGR, the first half of the ith floor has one connection to the second half of the |i + 1|th floor, and two connections to the second half of |i + 2|th floor. For a general case with N × N AWGRs, the first half of the ith floor has one connection to the second half of the |i + 1|th floor, and N /2 connections to the second half of |i+2|th floor (as shown in Table 2).

III. NETWORK PERFORMANCE EVALUATION
In this section, the discrete event driven simulator using C++ is employed to investigate the network performance. The discrete event driven simulator is a widely adopted approach to simulate the dynamic system of a communication network and evaluate the network performance [25]. The events (e.g. the arrival and end of communication requests, the assignment and release of the network resources, etc.) are inserted into the event queue following the order of time. Then they are processed in the order of event sequence. The arriving connection request is handled by the RWA algorithm, which decides whether the request is served or blocked. The blocking probability, which equals to the number of blocked requests over the number of total requests, can be calculated after simulation with a sufficient amount of requests. In other words, with the discrete event driven simulator and the RWA  algorithm, the dynamic process of the communication network system can be simulated and the blocking probability performance can be assessed. In the discrete event driven simulator, the arrival of requests follows the Poisson process and their holding time is exponentially distributed with a mean value normalized to 1 so that the arrival rate per node directly reflects the network load. Every point shown in result figures is obtained by averaging the outcomes of running 4 simulations with different seeds and each seed processing over 200,000 requests. Different traffic distribution patterns have been investigated to emulate different locality levels of traffic distributed in datacenter networks, which represent different types of applications hosted in the datacenters [26]. They are denoted as ''uniform'' and ''50%''. For the ''uniform'' case, the destination of each request follows the uniform distribution, while the ''50%'' case has a probability of 50% of connection requests staying in the same rack, representing the high traffic locality. In this paper, ''D = a + b'' means that the numbers of transceivers are a and b for intra-rack and inter-rack transmissions, respectively. The number of floors L is set from 2 to 5. The profile used in the simulator including information of network topology, node degree D, number of floors L, traffic distribution pattern, etc. is determined according to the tested scenarios. In this way, the network performance of different topologies in various scenarios is evaluated numerically in terms of blocking probability.
The impacts of the routing and wavelength assignment (RWA) algorithms and system configurations (e.g., the number of floors, the number of transceivers per node, i.e. the node degree D) on network performance in terms of blocking probability are investigated. The performance of the heatsink scheme is also measured for comparison. Based on the numerical results, a guideline is provided on how to properly configure the proposed grid topology based POI to achieve acceptable blocking probability.

A. IMPACT OF THE RWA ALGORITHMS
To understand how the RWA algorithms affect the network performance, two types of RWA algorithms are considered. In the CA-POI architecture, a simple RWA approach is applied, where K -shortest approach is for routing and the first-fit algorithm is for wavelength assignment. VOLUME 8, 2020 As a benchmark, this approach is referred to as A1. The idea of this approach is to find up to Ksp shortest paths for any coming request and choose the first path having available wavelength resource to be assigned. Although this approach performs well for the CA-POI [16], the heatsink and grid topologies have much better connectivity, and hence may not perform efficiently if employing such an algorithm with a fixed routing scheme. Therefore, a wavelength plane approach [27] is implemented, referred to as A2. In A2, a logical plane that takes into account the available wavelength and transceiver information is set up to find the shortest path. The wavelength plane consisting of the available wavelength information is appended to the original logical topology where the routing and wavelength assignment are executed together. Therefore, the size of the logical topology expands, in which the number of nodes becomes the total number of servers (2N × 2N × L) multiplied with the number of wavelengths (2N ). As a result, the complexity of A2 is significantly increased, which can be referred to Table 3. On the other hand, the information of available wavelengths and transceivers is considered in the cost function, i.e. the weight used in the shortest path calculation, which helps to improve the blocking probability. The cost function used in A2 is as follow: If a link is not in use, its cost is set to be equal to initial-cost (1 is applied in the simulation); If a link is used in a specific connection request, its cost is set to be a large value, referred to as COST1 (500 is applied in the simulation); if a link is not able to be used because all the transceivers at the node are occupied, its cost is set to another large value, referred to as COST2 (600 is applied in the simulation to be differentiated from COST1). To illustrate the cost function used in A2, the values of cost(x, y), i.e. the cost of link(x, y) directly connecting the node pair(x, y), under three different conditions are listed in (3). The weight of any path equals to the sum of the costs of all links in the path. The path with the minimum cost is obtained by the Dijkstra shortest path algorithm [28]. If the minimum value of total cost (most of the values ranging from 1 to 7) is obviously less than COST1/COST2, the path is then chosen as the route for the connection request. Otherwise, the connection request is blocked. Once the wavelength is successfully assigned to the request, the costs of the selected links have to be changed from initial-cost to COST1. If all of the transceivers at the nodes that are associated with the selected links are occupied, the costs of the links are set to COST2. In this approach the information of available transceivers and wavelengths is taken into account to find the shortest path. The wavelength assignment is carried out together with the routing. y) is not able to be used because all the transceivers at node x or y are occupied.
(3)   7 shows the blocking probability of the grid topology in two RWA algorithms. The results show the blocking probability as a function of arrival rate per node (i.e., the number of arrival requests per time unit divided by the number of total nodes that are able to be connected to the POI). For the results shown in Fig. 7, the number of shortest paths for A1 is set to 5, which is sufficiently large to get statured performance. The size of AWGR is 16 and the number of transceivers (i.e., node degree D, the maximum number of links established for each node) is 5. The traffic pattern is ''uniform'' in (a) and ''50%'' in (b). ''Two-floor'' and ''Three-floor'' indicate the number of total floors of the grid topology is two and three, respectively.
From Fig. 7 we can see that A2 has obviously lower blocking probability than A1 in most cases. It clearly shows that a proper algorithm needs to be chosen in order to leverage the increased connectivity in the grid topology. Therefore, in the later part of this section, A2 is selected for RWA. Table 3 shows the difference between A1 and A2. In A2, the routing and wavelength assignment algorithms are carried out together, while they are separate in A1. This leads to better utilization of the high connectivity of the grid topology and  better blocking probability performance when employing A2. However, this also results in higher complexity in A2 than in A1. The complexity determines the calculation time, that depends on the key parameters of the RWA algorithm (e.g., Ksp) and POI architecture (e.g., L, N ). The complexity of the Dijkstra routing algorithm is O(V 2 ) where V indicates the number of nodes in the logical plane. With A1 the number of nodes equals the number of servers in the topology. With A2 the logical plane is expanded and the number of nodes in the logical topology equals the number of servers multiplied by the number of wavelengths. The complexity shown in Table 3 is for the grid topology. The complexity of the heatsink topology can be deducted similarly.

B. IMPACT OF THE NUMBER OF FLOORS
The grid topology can achieve cross-floor transmission, and therefore the number of total floors is also a key parameter in the network performance. In this section, we choose four cases: ''Two-floor'', ''Three-floor'', ''Four-floor'' and ''Fivefloor''. Fig. 8 shows the blocking probability of the grid topology as a function of arrival rate per node for the system with the size of AWGR of 16. In Fig. 8, the requests are randomly distributed among different floors. The traffic case is ''uniform'' and the number of transceivers is 5, where a = 2 and b = 3.  From Fig. 8, we can see the blocking probability almost remains the same with the increasing of the number of floors. It is clear that the trend of the network performance is similar regardless of the number of floors, indicating good scalability of the grid topology. Therefore, the number of floors in the grid topology can be added up to request. VOLUME 8, 2020

C. IMPACT OF NODE DEGREE
Because the transceivers are allocated differently for the intrarack and inter-rack connections, the blocking probability for the same number of transceivers is not the same. For every node, here we choose two blocking probability values: MIN and MAX, representing the minimum and maximum values of blocking probability that can be achieved when assigning the different number of transceivers for intra-rack and inter-rack connections, respectively. From Fig. 9 one can see that the blocking probability significantly depends on the node degree. The network performance can be improved by increasing the node degree. The size of AWGR is chosen to be 16 or 32 considering the size of commercially available AWGR products [23]. It is clear that the trend of the network performance is similar regardless of the size of AWGRs. The results can be explained as when the degree becomes larger there are more transceivers per node and more available paths can be found to improve the network performance. Therefore, the blocking probability can be decreased drastically with a larger node degree.

D. COMPARISON OF THE HEATSINK AND GRID
We compare the blocking probability as a function of arrival rate per node of the heatsink topology and grid topology. The number of transceivers is 5 and the traffic distribution pattern is ''uniform''. The size of the AWGR is 16 and 32 in Fig. 10(a) and Fig. 10(b), respectively. Besides, the number of top AWGRs in the heatsink topology K is 1, 2 and 3. Moreover, all the connection requests of the grid topology stay on the same floor. From Fig. 10, we can see the blocking probability of the grid topology is smaller than that in the heatsink topology regardless of the value of K . Furthermore, the simulation results are similar regardless of the size of AWGR. As mentioned in Section I, there are two layers of the AWGRs (i.e., the top and bottom AWGRs) in the heatsink topology. For the nodes associated with the same bottom AWGR, they can communicate with each other with a onehop direct connection via this AWGR. However, the interconnection between a pair of nodes associated with two different bottom AWGRs has to pass several AWGRs in the heatsink topology. K denotes the number of the top AWGRs in the heatsink topology, which allows up to K paths for the connection of a pair of the nodes associated with different bottom AWGRs. It can be seen from Fig. 10 when increasing K to 2, the blocking performance can be significantly improved. However, such an improvement becomes minor when continuing to increase K . Table 4 shows the differences between the heatsink and grid topologies. Here 2N × 2N AWGRs are used in two topologies and the number of top AWGRs is K in the heatsink topology. From Table 4 we can see that the grid topology achieves more connections per AWGR compared with the heatsink topology, especially for inter-rack links. It means the grid topology has higher connectivity, leading to better blocking probability performance as shown in Fig. 10. Moreover, the grid topology can be extended vertically with L floors, showing good scalability. On the other hand, the grid topology has a higher complexity.

IV. CONCLUSION
We have proposed one passive optical interconnect architecture, named as the grid topology. We introduce the physical structure and logical topology of the proposed architecture.
Compared with the heatsink topology, the grid topology can increase connectivity, scalability and reliability, while reducing the number of AWGRs that has to pass through for each connection. The simulation results have demonstrated that the network performance of the grid topology is better than the heatsink topology and the grid topology is more appropriate for the optical interconnection in datacenters. Furthermore, the numerical results show that for the grid topology the network performance almost remains the same when the number of floors increases and can be improved by increasing the node degree.
Moreover, it should be noted that although the required numbers of FBGs and AWGRs of the grid topology increase when the number of servers to be connected grows, the maximum numbers of hops and required wavelengths are not necessarily high. The rich connectivity and high energy and cost efficiency have also made the POI approaches like the grid topology become attractive solutions for datacenter networks [19], [29]. On the other hand, the proposed scheme employs circuit switching, which is more suitable for the high bandwidth application in datacenter networking [30]- [32]. The nodes in the grid topology cannot only represent servers in the edge tier, but also the racks/clusters in the aggregation and core tiers. When the grid topology is used for the inter-rack/cluster interconnections, the advantage of circuit switching of the grid topology makes it more suitable for the datacenter networks. On the other hand, the control signals are sent on the packet basis in the control plane [18] which is separated from the circuit switching in the data plane. Software-defined networking (SDN) as a centralized controller recently is considered as a promising protocol that can be employed for the proposed scheme. We believe the grid topology could be a step forward to show the possibility to have circuit switching to support scalable data transmission but at the same time brings a challenge on control signaling that calls for research efforts.
The advantages of network connectivity and reliability make the grid topology a promising approach for datacenter networks. The advantages are provided by the multiple concurrent connections and passing only one AWGR for any direct optical connections. To be more specific, the topologies with multiple AWGRs that need to be passed for direct connections [21] suffer from the degradation of transmission quality, resulting in the restriction of some connections due to unacceptable transmission quality. The grid topology relieves the restriction and makes more connections available. On the other hand, the grid topology offers rich concurrent connections, especially for the inter-rack communications, with the proper design of architecture. The superiority of the number of connections per AWGR, especially the inter-rack connections, of the grid topology over the heatsink topology is shown in Table 4. This leads to better blocking probability performance of grid topology as shown in Fig. 10. When compared to the POI architectures [15], [16] where the number of directly connected links is limited to one, the advantage of grid topology is expected to be more significant. Moreover, VOLUME 8, 2020 the rich connections not only offer better connectivity but also provide backup solutions once the original links are occupied or failed. This leads to higher reliability and the reduction of failures of the arriving requests. The further analysis of reliability and resilience of the proposed grid topology based datacenter networks will be included in our future research. The problem of reliability analysis can be rather complex, especially when the datacenters become the essential infrastructure to support applications like 5G, Internet of Things (IoT), etc. For future work, we will further analyze the reliability of the proposed datacenter networks in complex dynamic scenarios [33]- [36]. It should be noted that the paper focuses on the architecture design and blocking probability analysis of the grid topology based datacenter networks. Multi-objective optimization [37], [38] will be an important research direction for future work to improve the blocking probability and reliability at the same time, especially when the networks are facing the significant challenge of continuously increasing traffic while satisfying the requirement of low energy consumption.

APPENDIX AWGR ROUTING TABLE AND COMPONENTS IN THE SIX OPTICAL PATHS
The wavelength routing table of N × N AWGR is shown in Table 5, and the components together with ingress and egress ports of the AWGR in the six optical paths are shown in 6. JIAJIA CHEN received the bachelor's degree from Zhejiang University, China, in 2004, and the Ph.D. degree from the KTH Royal Institute of Technology, Sweden, in 2009. She is currently a Professor with the Chalmers University of Technology, Sweden. She and her group have made advances in optical network architecture design along with the supporting transmission techniques and resource allocation strategies, which greatly improve capacity, reliability, energy efficiency, and cost efficiency in access, core, and data center networks. She has been sharing her knowledge with the technical community with many peer-reviewed journal articles, conference papers, invited talks (more than 200 publications todate), and ten patent applications. She has organizing several IEEE international conferences in the field and serving on technical program committees, including OFC (Subcommittee Chair 2019), ECOC, Globecom (Symposium Co-Chair 2020), and ICC. VOLUME 8, 2020