A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power Asynchronous SAR ADC for IEEE 802.15.1 IoT Sensor Based Applications

An energy efﬁcient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented for IEEE 802.15.1 IoT sensor based applications. An improved common mode charge redistribution algorithm is proposed for binary weighted SAR ADC. The proposed method uses available common mode voltage (V CM ) level for SAR ADC conversion, and this method reduces the switching power by more than 12% without any additional DAC driver as compared to merged capacitor switching (MCS). Mathematical analysis of the proposed switching scheme results in the lower or equal power consumption for every digital code as compared to MCS. A two stage dynamic latched comparator with adaptive power control (APC) technique is used to optimize the overall efﬁciency. Furthermore, to minimize the digital part power consumption, a modiﬁed asynchronous SAR logic with digitally controlled delay cells is proposed. High efﬁciency with low power consumption makes it suitable for low power devices especially for IEEE 802.15.1 IoT sensor based applications. The proposed prototype is implemented using 1P6M 55 nm complementary metal-oxide-semiconductor (CMOS) technology. The measurement results that the proposed circuit achieves are 9.3 effective number of bits (ENOB) with signal-to-noise and distortion ratio (SNDR) of 58.05 dB at a sampling rate of 8 MS/s. The power consumption of SAR ADC is 45 µ W when operated at 1 V power supply.

to few nanometers. SAR ADCs are suitable for increasing scale-down technology and also can operate at a very low-power supply voltage. Excellent power efficiency and low analog complexity make the SAR ADC one of the best candidates for low energy applications [4]- [10].
The N-bit SAR structure requires N comparison cycles to complete the ADC conversion because of successive approximation conversion. Therefore, it is quite difficult to perform well in both resolution and throughput for SAR ADCs [11]- [13]. Low/medium resolution application, low to medium speed, low-power and area are the important characteristics of SAR ADCs [14], [15]. The SAR logic performs binary search algorithm through all possible bits to determine each bit successively. An asynchronous control signal is generated according to comparator state rather than the external clock. [16]. Thus, the conversion time (T CONV ) for asynchronous SAR ADC can be calculated as: (1) where, T sample is the sampling time and F S is the sampling frequency. A tri level switching scheme named as reverse V CM based scheme which maintains good linearity without any driving and accuracy requirements on V CM is represented in [6], and charge redistribution digital-to-analog converter (DAC) for the SAR ADC to reduce the area cost and power consumption and to promote the bandwidth is shown in [7]. For low supply voltage, asynchronous SAR assisted time-interleaved SAR ADC is considered in [10]. A dual-mode clock generator generates a low-jitter fixed-width sampling pulse for high-frequency operation while it generates a low-power-butlow-quality clock for low-frequency operation.
In asynchronous SAR ADC, back-to-back execution of each operation after the previous one is finished, makes it faster than the synchronous SAR ADC. This makes the asynchronous SAR ADC as an energy efficient and faster scheme as compared to synchronous SAR ADC. In order to cope-up with the need of high speed and energy efficient, many techniques have been applied [17]. The incomplete settling issues in DAC can be addressed by non-binary SAR ADCs. But to meet the matching requirement, layout cannot be designed properly, which can lead to the degradation in linearity and results in high order harmonics. Furthermore, for non-binary weighted SAR ADC, the digital error correction (DEC) logic is also too complicated [18]. Designing of redundant bit in binary weighted ADC is much easier than the non-binary weighted SAR ADC, but in every comparison cycle the compensation of incomplete settling is difficult for binary weighted SAR ADC [19]. An additional compensation capacitor is not required in binary-scaled recombination weighting method as proposed in [20]. But in high speed ADC case, power consumption cannot be overlooked because of DEC logic. Besides this, a call of an extra comparison cycle is required in the realization of [21] and [22].
This work presents an architecture in which several techniques have been applied which make its operation as an energy efficient and faster as well. The proposed switching architecture achieved a reduction in switching energy and improved linearity by determining whether the recent bit is similar as the first output comparison bit. The first comparison result will be sent to DAC, if the recent bit is same as the first comparison output bit, and if the recent bit is different, then the previous value of DAC will be reset to common mode voltage (V CM ). Asynchronous SAR Logic is implemented with dynamic logic in which sample time for each bit can be adjusted with trimming bits. A 0.5 fF custom designed unit capacitor is used to reduce the power consumption of analog part and modified rail-to-rail comparator with an adaptive power control (APC) control circuit, which results in low power consumption by reducing the active time for the comparator. This paper represents the optimization of power efficiency and area along with the speed of SAR ADC. This paper is organized as follows. Section II discusses the main architecture for asynchronous SAR ADC for an I path and Q path and some of the Sub-blocks. Section III explains the ADC Core and its sub blocks, including design and implementation of improved common mode charge redistribution switching, the 0.5 fF custom designed unit capacitors, dynamic latched comparator with APC control and implementation of power-efficient asynchronous dynamic logic. Complete ADC measurement results are in Section IV and finally, conclusions are in Section V.

II. ASYNCHRONOUS SAR ADC ARCHITECTURE
In the design of BLE transceiver, the target resolution is 10 bits. To keep the low current consumption and faster operation, 10 bit resolution with reduced switching energy is applied to the ADC. The conversion rate is 8MS/s while the input frequency to the ADC can vary from the low frequency up to 2 MHz [2]. In a low power BLE transceiver, the low-noise amplifier (LNA) amplifies the noisy input signal as shown in Fig. 1. Then, through the baseband, the signal is delivered to ADC for modulating the lower frequencies. IIN, IINB, QIN and QINB are the differential input signals of I and Q path ADCs, respectively. The proposed 10-bit 8MS/s asynchronous SAR ADC is composed of DACs with binary-weighted capacitors (CDAC), high speed and low power dynamic latch comparator with APC technique and asynchronous SAR logic with DAC delay control as shown in Fig. 2. The binary architecture for CDAC in SAR ADC is more popular due to its ability to achieve comparatively better matching. The comparator with APC takes the voltages at the bottom plates of the differential CDACs IOUTP and IOUTN as its inputs and determines output bits. Switching of DAC is controlled by the output bits of control logic from MSB to LSB. The differential CDACs are responsible for converting the output bit of control logic to analog values through switching capacitors at different voltages. One conversion is completed after N comparison cycles for N-bit SAR ADC.
The presented asynchronous SAR ADC is operating at 8 MS/s with the clock frequency of 8 MHz. The duty cycle of the clock signal is 75% and the whole conversion process is being done within the duty cycle of the clock. Digitally controllable delays have been added in asynchronous logic to control the conversion speed of each bit, which makes it optimized in the aspect of faster timing. Custom designed metal-oxide-metal (MOM) capacitors are used in CDAC to minimize the power consumption and the area of analog part. APC circuit has been used to reduce the overall power consumption of comparator. It controls the comparator's operation by turning it off when the outputs of the comparator are determined. For faster operation and reduction in overall size, 0.5 fF custom designed MOM unit capacitor is used in CDAC which also results in minimizing the overall power consumption of analog part of the ADC by reducing the switching current in CDAC.
Four CDACs and two comparators have been used for I/Q signals as shown in Fig. 2. Timing diagram of the proposed architecture is shown in Fig. 3. Reference voltage generator is common for I and Q path and provides voltages IV REFB / QV REFB of 0.2 V, IV CM /QV CM of 0.5 V and IV REFT /QV REFT of 0.8 V. For I path SAR ADC receives the differential input signals IIN and IINB. The reference voltage generator generates V REFT , V REFB , and V CM of values 0.8 V, 0.2 V and 0.5 V, respectively. A 10-bit CDAC provides the reference input signals IOUTP and IOUTN to the comparator. The Track-and-hold operation is done by the sampling switch and capacitors in the CDAC. Control signals D_I<9:1>, S_I<8:0>, D_Q<9:1> and S_Q<8:0> from asynchronous SAR logic with digital control delay block, controls the switching sequence of CDAC's and generates the comparator's clock signal ICCLK and QCCLK. Dynamic latched comparator generates control bits for asynchronous SAR logic after determining the signs of the voltage at the CDAC's output. On the completion of the successive approximation process, asynchronous SAR logic creates an End-of-Conversion (EOC) signal. In the proposed ADC architecture, we use the on-chip reference generator. To ensure the stability and low power, decoupling capacitors are used as on-chip and off-chip in the voltage reference circuit. On-chip decoupling results in better stability as compared to the off-chip decoupling. To minimize the number of pins, a fully integrated voltage reference is implemented. Besides, on-chip decoupling capacitors act as the AC driver for low power. The proposed on-chip reference voltage, which is similar to [9], with no extra pins. The switching noise at high frequency is suppressed by the on-chip decoupling capacitor effectively and it also helps in minimizing the settling time of the disturbed signals.

III. CIRCUIT IMPLEMENTATION A. CAPACITIVE DAC
Many SAR ADC switching algorithms are presented for binary weighted CDAC architecture, but the voltage common mode based charge redistribution technique has been the most energy efficient nowadays. The CDAC is implemented with charge-redistribution topology [23]- [25]. The proposed scheme shows that the improved voltage common mode based charge redistribution algorithm in which static linearity and switching energy efficiency are improved by efficient selection of the time that individual binary capacitor is reset. Fig. 4 shows a 3-bit CDAC switching sequence. The improved switching technique is explained as follows: The top plates of all the capacitors are sampled at the common mode voltage (V CM ). At the same time, the bottom plates of the capacitors are initially sampled with the VIP and VIN for the positive and negative CDAC respectively. The total charge at the positive and negative input of the comparator where, C T is the total capacitance, C MSB is the MSB capacitor size and C is the LSB capacitor and the larger capacitors are composed of multiples of C.
The negative plates of all the capacitors are connected to the V CM . The total charge at the comparator's positive input and at the comparator's negative input is Q A = 4C(V A −V CM ) and Q B = 4C(V B −V CM ), respectively. According to the law of conservation of charge, the total charge in both modes is the same, so the voltage levels at both sides is shown in Fig. 4.
In the next phase, if V A > V B , the comparator's output becomes high resulting in most significant bit (MSB) equal to '0' then the positive CDAC is charged at V REFB and the negative CDAC is charged at V REFT . The charge at the comparator's input is If V A < V B , the comparator's output goes to low, resulting in MSB equals to '1' then the positive CDAC charged at V REFT and negative CDAC charged at V REFB . The charge at the comparator's input is Significantly less energy is consumed by the same direction switching in comparison to the opposite direction switching. To correct the previous voltage in opposite direction switching, required reference voltage should be generated, which is generated by overshoot. However, this is not the only option. Another solution is shown in Fig. 4 by resetting the previous capacitor to the V CM and switching the recent capacitor to the opposite polarity. By this method, the capacitance connected with the reference voltage is minimized. Hence, the total supply reference capacitance is minimized before changing in the reference node voltage and additional charge is introduced from the supply. The energy at {1, 0} conversion is shown as: There is no additional energy required while previous capacitor is switched to the V CM because it is switching in reset phase and all previous charges are differential and cancelled on the capacitors across the shared V CM node. Furthermore, in early stages, energy reduction will continue in the referenced capacitance due to the movement of virtual references in further stages. If the recent bit has opposite polarity from the previous bit, then the previous capacitor will be reset and a recent capacitor will be charged to the given positive and negative DAC to the opposite charge as proposed in this paper. To represent the code digitally, the reference voltage capacitance related to the current bit depends upon the previous bit and the next bit. The energy per code is shown as: where, N is the given stage, B P is the previous stage bit and B C is the current bit. The behavioral simulation of per code energy is plotted in MATLAB as shown in Fig. 5. 10-bit SAR operation assigned to (C * V 2 REF ) and reduction in energy can be observed for each code. The Unit capacitor is represented as C and supply voltage to the DAC is represented as Vref. For 10-bit case, monotonic switching energy [26]  The proposed common mode charge redistribution switching architecture results 12.5% reduction in average switching energy for uniform input probability density function (PDF) and 18.4% reduction for Gaussian PDF input. In MCS architecture, common mode redistribution technique reduces the switching energy from central codes by reducing the power of alternating codes. The proposed technique achieves 41.5% reduction in average switching energy as compared to [26]. To check the sensitivity due to capacitor mismatch, static performance of the proposed switching scheme based on behavioral simulation in MATLAB is shown in Fig. 6. The simulation is done without and with mismatch by considering 1 % unit capacitor mismatch [27], [28]. The simulation result for proposed CDAC is shown in Fig. 7.  In CDAC, the value of capacitor is doubled every time from LSB to MSB. The settling time of each interval for CDAC is based on τ = RC, where R represents the sample switch resistance and capacitance in each bit is represented by C, which is controlled by adjusting the resistor's value to allow settling for a limited time. This can be done by adjusting the switch size resulting in different conversion time and switch size for each cycle. MOM capacitor layout is implemented by using metal 4 and metal 5 and verified by using electromagnetic extraction (EMX) simulation. Inner metals 4 and 5 are used with minimum spacing and width to minimize the unwanted parasitics between each terminal and ground as shown in Fig. 8. To minimize the mismatch, dummy capacitor array is added in the layout. CDAC layout is done with rectangular layout and dummy capacitor layout. Binary scaling is verified in top layout parasitics extraction with the capacitance of 0.514 fF and 130.3 fF for C and 256C, respectively.

IV. DYNAMIC LATCH COMPARATOR WITH APC
For fast operation and high resolution, a rail-to-rail comparator is used in ADC core of the proposed architecture, VOLUME 8, 2020  which contains the dynamic latch and pre-amplifier as shown in Fig. 9. VIN and VINB are the differential input reference signals for the comparator, CCLK is the clock signal and OUT and OUTB are the output of the comparator. For railto-rail input the pre-amplifier has differential input pair as N-type and P-type. Due to static current after the comparison operation the power efficiency is poor in conventional dynamic latched comparator. In the proposed architecture, the pre-amplifiers static current can be blocked through the APC logic after pre-amplifying and output decision, hence power efficiency of ADC is improved.
As dynamic latch architecture can introduce large input referred offset, which is not suitable for medium and high resolution ADCs, we have reduced its effects by increasing the sizes of the input transistors in differential pair [29]- [32]. In addition to this, we have used an APC circuit which reduces the overall power consumption of the comparator. When CCLK is changed from low to high, APC signal changes to high and turns on the preamplifier. When the comparison is finished, OUT goes to high and OUTB goes to low and output of XOR_A goes to high. Now both input terminals of XOR_B are high, APC signal changes to low and DC supply of the preamplifier is turned-off.

V. ASYNCHRONOUS SAR LOGIC
In the proposed architecture, the implementation of digital logic is to minimize the complexity from current dynamic logic. Combinational logics are implemented with transistors. Asynchronous logic is comprised of main control, DAC control and a comparator clock generation block. Fig. 10 shows the simplified block diagram of the logic for the SAR ADC. Fig. 11 shows the timing diagram of the proposed  asynchronous logic. DAC control, and a comparator clock generator are implemented after main control and delays for DAC control. The comparator clock generator needs to generate a high-level at the input of the comparator clock when comparator-state is shown in one of the cycle of main control. Thus, the comparator clock generator is a logic operation for the all cycle's states, and the complementary logic functionality is used to implement it: Leakage current is the most prominent in consuming power at low sampling frequencies and leakage current is directly dependent on the implemented logic state of the statemachine. In this design, when the CLK is 0, then the SAR logic is in a standby state and then the leakage current is minimized.
To minimize the power consumption in digital part, asynchronous SAR logic is used. With asynchronous SAR logic, instead of a high reference clock, a sampling rate of 8 MHz can be implemented with only one clock resulting in reduced current consumption. It generates internal control signals and eliminates the need of global synchronization at each bit cycle as shown in Fig. 12. Furthermore, a modified asynchronous SAR control logic is proposed to optimize the delay between comparator's operation and DAC switching. In case of a general asynchronous controller, there is a specific delay for each cycle when the comparison is made, but in the proposed modified logic control there is a scalable delay for different comparison from LSB to MSB. Delay cell, which can be externally controlled by A<1:0> is shown in Fig. 13. To reduce the complexity and current consumption,   dynamic logic is used for implementation. The same function can be done with fewer transistors than the complementary logic [25].

VI. MEASUREMENT RESULTS
The proposed prototype of SAR ADC is implemented and tested with 55 nm CMOS process. The die photograph of the whole structure is shown in Fig. 14 and the measurement setup for the ADC test board is shown in Fig. 15. The area  of the proposed ADC is 362 x 524 µm 2 and it operates at 1V power supply at 8MS/s sampling speed.
The FFT spectrum of the proposed ADC operated in differential operation is presented in Fig. 16. It achieves an ENOB of 9.35 bits, SNDR of 58.053 dB and SFDR of 65.992 dB at VOLUME 8, 2020   the nyquist input signal frequency at a sampling rate of 8 MS/s and a full-scale input range of 600 mVp-p.
The measured DNL and INL of the proposed ADC are shown in Fig. 17, which represents peak DNL error and the  INL in the proposed ADC are −0.91 to 0.89 and −1 to 0.84, respectively. The power breakdown of ADC is represented in Fig. 18. Fig. 19 shows the SNDR and SFDR levels trend and Fig. 20 depicts the ENOB trend of the proposed ADC with different input frequencies at 8MS/s sampling rate. Table 1 shows the measured performance summary and comparison with other ADC structures. To compare the presented 10-bit 8MS/s ADC with resolution, different sampling rates and figure-of-merit (FOM) of other ADCs works are essential. FOM is calculated as given [34]: where, Power and F S represent the power consumption of ADC and the sampling frequency, respectively and ERBW is the effective resolution bandwidth. The current ADC core shows a FOM of 8 fJ/step, while for a whole structure it is 75.3 fJ/step. The FOM of whole structure includes the reference generator and two ADC cores for I and Q paths. Table 1 shows the comparison with other stateof-the-art SAR ADC [10], [23], [33]- [36] and summarizes the performance of proposed asynchronous SAR ADC.

VII. CONCLUSION
This paper presents a 10-bit low power asynchronous SAR ADC for IEEE 802.15.1 IoT sensor based applications. The proposed prototype of ADC is implemented in 55-nm CMOS process. To minimize the power consumption in analog part, very small size custom designed 0.5 fF MOM capacitors are used in CDAC. The proposed switching technique reduces the switching power consumption by 12 % as compared to MCS. The employed switching strategy improves or equalizes the energy efficiency requirements for each code by utilizing the common mode reference in DAC. It guarantees the consequently improved linearity and common-mode voltage level of the comparator unchanged. A modified two-stage dynamic latch comparator is used for the fast operation and high resolution. APC circuit is used along with the comparator to control its operation resulting in enhancing overall energy efficiency. Compact control logic and high-speed dynamic latched are implemented, to enhance energy efficiency and the operation of proposed SAR ADC. Furthermore, modified asynchronous SAR logic is implemented with adjustable delays for different comparison from LSB to MSB. The proposed prototype achieved a FoM of 8 fJ/conversion-step. The proposed structure occupied an area of 362 µm × 524 µm. The measurement results show that it achieved an ENOB of 9.3 bits and SNDR of 58.05 dB at a sampling rate of 8 MS/s with 1 V power supply.