Mitigation of Decoherence-Induced Quantum-Bit Errors and Quantum-Gate Errors Using Steane’s Code

Quantum processors require Quantum Error Correction Codes (QECC’s) for improving the fidelity of quantum logic gates. Fault tolerant QECC’s are capable of providing error rate improvements in quantum processors as long as the components are operating below a certain gate error probability. In this contribution, we quantify the depolarization probability bound, below which transversal QECC’s would give a better error probability than an uncoded gate. Both a low-complexity repetition code and Steane’s 7-bit QECC are characterized.

qubit errors at the output of the circuit block [1]. Under this idealistic assumption a physical qubit error introduced by a single gate cannot escalate to an uncorrectable number of errors, given the [n, k, d] QECC considered. However, if a single gate error exhausts the [n, k, d] code's error correction capability, encountering a second gate error will result in error proliferation. Let us assume that the probability of a single gate error is p. Hence the probability of two simultaneous gate errors is O(p 2 ), provided that the error events are independent of each other, while p 1 and p 2 < p. Unfortunately, a bit-flip error on the control qubit in a controlled-NOT (CNOT) gate will result in a deleteriously applied NOT operation imposed on the target qubit, hence resulting in two erroneous qubits, rather than one. Therefore an originally correctable number of individual qubit errors escalates to an uncorrectable number of correlated qubit errors even if no additional component failure has occurred.
A fault tolerant implementation of the CNOT gate relies on a so-called transversal architecture, as seen in Figure 1 [2]. The CNOT gate will be discussed in Section II-A and Transversal Gates in Section V. To elaborate, the left hand side of Figure 1 shows the uncoded circuit, whilst the right hand side portrays the fault tolerantly encoded circuitry, where the represents a NOT gate and S is a syndrome decoder. For the convenience of our discussions, here we initially portray a simple R = 1 3 -rate repetition code which is capable of correcting one error in each 3-qubit code word. Hence it has a 33% error correction capability. Both the upper and lower syndrome decoders of Figure 1 are only capable of correcting a maximum of t errors. We arrange for the logical connection of the ith physical qubit in the control state with the ith qubit in the encoded target state, as observed in Figure 1. For example, a bit-flip error on the second control qubit of the upper syndrome decoder would only interact with the second target qubit seen at the output of the lower syndrome decoder in Figure 1. This circuit design limits the propagation of qubit errors, since an error that is corrected by the top syndrome decoder can only propagate to a single error input to the lower syndrome decoder. Since the control and target qubits are encoded separately, the error that has proliferated through the transversal CNOT connection can always be corrected.
Under the fault tolerant premise, it is assumed furthermore that no adjacent qubit failures occur either spatially or temporally, since they are independent at each segment of the circuit. However, repeated applications of an imperfect gate would be more accurately represented by an error model that includes temporal and/or spatial correlation in the gate failure, since environmental perturbations may affect a group of components in each others vicinity. Therefore assuming independence of the component errors constitutes another idealized simplifying assumption.
Furthermore, a common fault tolerant [n, k, d] encoding technique relies on fault tolerant stabilizer measurements used for preparing the encoded information [1]. However, this requires knowledge of the state that we wish to encode. More explicitly, in order to prepare an arbitrary state |ψ = α|0 +β|1 , the coefficients α and β must be known to us [3]. This has the drawback that unknown information cannot be encoded. However, encoding unknown information is necessary because in many practical schemes QECC decoding and re-encoding are applied mid-way through the computation, as demonstrated in [4].
Fortunately, there exist unitary encoding circuits, which have the capability of encoding unknown information, but regretfully again these are not fault tolerant by the above definition. Having said that, these unitary encoding circuits are still appealing, since they do not require additional ancilla to encode the state. Unfortunately, fault tolerant state preparation techniques impose a substantial qubit overhead, since the stabilizer must be repeated multiple times to guarantee that a single error-free outcome can be obtained. In addition to the above complications, the ancilla must be prepared without error, hence potentially requiring the distillation of the errorfree states from a larger number of states. Therefore, since the encoding circuit requires only (n − 1) qubits in addition to the unknown information qubit, it is desirable to find a solution for mitigating the error proliferation inherent in nonfault tolerant circuits.
A fault tolerant quantum circuit must be able to cope with both gate errors as well as proliferated errors. Gate error may impose a qubit error on the circuit, while a perfect gate may still propagate a qubit error. Another scenario is that a poorly located and inaccurate gate will be subjected to both qubit error and error proliferation at the same time. The invention of fault tolerant QECCs in [8]- [11] addressed this issue by re-thinking the construction of the traditional quantum coding circuits so that single gate errors do not overwhelm the QECC. The work of Aharonov and Kitaev prove that a gate error rate threshold can be found [8], [9], [12], [13] below which the QECC provides improvements to the logical accuracy of a quantum computation. Moreover, when the components of a quantum processor operate below the gate error threshold, fault tolerant quantum computation is indeed achievable.
The seminal conception of fault tolerant QECC's by Shor [7] combined with the threshold theorem of Aharonov and Ben-Or [12] provided a proof of concept that quantum computers may execute a quantum algorithm to a reasonable accuracy despite imperfect components. However, such schemes were still impractical because the circuit construction relies on the assumption that there is no restrictions on qubit interactions. Unfortunately, this makes such schemes impractical to implement in hardware. This gave rise first to the Toric code of Kitaev [14] and later to Topologcial codes [17]. These schemes assume a lattice configuration of the qubits, which have interactions amongst the nearest neighbour qubits only. This makes the design of the hardware straightforward and therefore topological constructions have become the most popular methods of practical QECC implementations [23], [24]. The Gottesman-Knill theorem [25] shows that the Clifford gates can be simulated classically [26]. Moreover, there is no code relying on a universal transversal gate set [27], [28]. Magic state distillation is an efficient way of implementing gates within a full gate set [18]. Raussendorf and Harrington [19] also proposed a universal gate set for topological codes by using CNOT gates with Magic state distillation [20].
Against the aforementioned background, our novel contributions are:

3)
We present a channel model capable of characterizing both gate errors and individual qubit errors. Finally, the attainable FER improvements are quantified for the transversal CNOT gate using Steane's [7,1,3] code. The structure of the paper is portrayed in Figure 2.

II. QUANTUM GATES
The unit of quantum computing is the quantum bit (qubit). A qubit can reside in a superposition of the unit vectors |0 and |1 corresponding to the classical bit values 0 and 1 [3], [29], [30]. The information stored in a qubit is processed by quantum logic gates. These are introduced in the following section, starting with the most common two-qubit gate, namely the CNOT gate.

A. THE CNOT GATE
The controlled-NOT gate (CNOT gate) is a two-qubit gate that prepares entanglement between two quantum states. If the control qubit is in state |1 , the CNOT gate applies an X gate (denoted ⊕) to the target qubit. The transformation carried out by the CNOT gate is given by the following equations |AB → |CD |10 → |11 |11 → |10 |00 → |00 |01 → |01 , where A and B represent the control and target qubit before the CNOT gate, while C and D represent those after the CNOT gate. Figure 3 shows the CNOT gate associated with the control qubit |φ 1 and target qubit |φ 2 . The equivalent of an OR gate is applied to the target qubit. The arbitrary twoqubit state |φ 1 |φ 2 , shown in Figure 3, can be described by where the complex coefficients have the property that |a| 2 + |b| 2 +|c| 2 +|d| 2 = 1. The action of the CNOT gate in Figure Then the action of the CNOT gate is shown to swap the coefficients in the superposition state in Eq. (1) such that |10 ↔ |11 . This is shown by which is in accordance with the transformations listed in Eq. (1).

B. THE PAULI GROUP
Quantum gates can be classified into three groups, namely the Pauli (C 1 ), Clifford (C 2 ) and the C 3 group, together known as the Gottesman-Chuang hierarchy [15]. The Pauli group is the most common one, which consists of the following gates The X gate has the effect of a bit-flip or a NOT gate on the qubit. For example, Notice that the bit-flip swaps the coefficients α and β. Similarly, the Z gate has the effect of a phase-flip on the state Z |ψ = α|0 − β|1 , which introduces a negative relative phase difference between the basis states. The Y gate acts like both a bit and a phase-flip, since we have Y = XZ . Therefore Y |ψ = i(β|0 − α|1 ). Finally, the identity operator leaves the qubit unchanged I |ψ = |ψ . Then let us define the Pauli group as [3] Let us also define the group G N as all N -qubit tensor products 1 of the Pauli operators X , Y , Z , I .
For example, the set G 5 permutes a five-qubit register with 4 5 possible combinations. This contains the operator XZZXI , which has the effect of applying a bit-flip to the first and fourth qubit as well as a phase-flip to the second and third qubit.

C. OTHER GATE SETS
When an element of the Pauli group is conjugated by a Clifford gate, it is mapped back to a Pauli gate. This defines the Clifford Group as follows [31] For example, the Clifford group includes the Hadamard, S and CNOT gates These gates are defined by There is another set of quantum gates exhibiting the property that when a Pauli operator is conjugated by a C 2 Clifford gate, it is mapped back to the Clifford group. The set of gates that have this property belong to what is called the C 3 group [32] defined as: The T gate, the Toffoli gate and the controlled-Z gate belong to the C 3 group [3]. For example, where the T gate is defined by

III. STABILIZER CODES
A [n, k, d] stabilizer code maps k logical qubits to n physical qubits. Then the code space is a 2 k -dimensional sub-space of a 2 n -dimensional Hilbert space. The stabilizer set S ∈ {K i } is the n-qubit sub-group of G n that fixes the code space, when the stabilizers are measured. In this paper we use the subscript i of K i to refer to a specific stabilizer operator in S, while K is used without a subscript, when the stabilizer operator is arbitrary. The legitimate code space is the simultaneous +1 eigenspace of S defined as A stabilizer group S is a subgroup of G N that is closed under multiplication. The set also has the property that −I ∈ S, since we have (−I )|ψ = |ψ only when |ψ = 0. All elements of S commute, 2 so there is a simultaneous eigenstate that can be measured for multiple operators. This can then be chosen as the code space and is defined by the set of l = n−k independent generators of S.
A correctable error E anti-commutes with the stabilizer, which means that KE = −EK [33]. For example, if |ψ is a legitimate code-word, then the stabilizer has the effect [33]: Applying the stabilizer operator incurs a −1 phase difference in the data. This is then passed onto the ancilla qubit by a series of CNOT gates, shown in Fig. 7. A Hadamard gate is then applied to the ancilla qubit so that when it is measured, this returns the bit value of 1. The measurement outcome 1 triggers an error recovery operation, which corrects the error E in the data returning it to the valid codeword state |ψ , i.e back to a +1 eigenstate of K . This allows the stabilizer to detect an error without the need for the data qubits |ψ to be measured directly [34].

A. REPETITION CODE
This section describes the [3, 1, 3] repetition code as introduced in [3], [29], [35]. This is a d = 3 code and can correct only a single bit or phase-flip error on a single qubit, depending on the design. In this section the specific version that corrects a single qubit bit-flip error is described. However, the 2 Commuting operators satisfy results for the phase-flip error are equivalent. The full circuit of implementing the repetition code is shown in Figure 4. The traditional n = 3 qubit unitary encoding circuit V is applied to the unknown state |ψ = α|0 + β|1 and (n − k) auxiliary qubits in the |0 state as follows [29] |ψ = V(|ψ ⊗ |0 ⊗(n−k) ). (15) This results in the encoded state The encoded data is corrupted by the bit-flip channel ε(ρ). If |ψ is corrupted by a single bit-flip error with probability P e then we have: where each error position is equiprobable. This is input to the stabilizers K 1 = ZZI and K 2 = ZIZ . The outcome of the stabilizer measurements is shown in Table 2 alongside the required recovery operation R. Since this is a d = 3 code, if there are more than a single qubit error then the error recovery may in fact carry out a flawed recovery, hence introduce additional error. Nevertheless, each error recovery operator R in Table 2 corrects a single bit flip error inflicted upon the state |ψ in Eq. (16). Finally, the inverse encoder V † in Figure 4 maps the recovered encoded state to an estimate of the initial code word |ψ . This is the reverse operation of the encoder V, hence n encoded qubits are mapped back to k information qubits.

B. STEANE CODE
There are many substantially more powerful QECC's, including the original 9-qubit Shor code [36] and the so-called perfect, 5-qubit code of [37]. This is referred to as being 'perfect' 3 in [37] because it is the highest-rate known code capable of correcting a bit-flip and phase-flip error at a code rate of 1 5 . In this section the [7, 1, 3] Steane code is described, which is a common QECC that can correct any arbitrary single-qubit error [39]. It's circuit implementation is shown in Figure 6.  The encoded states can be prepared by the traditional Steane encoding circuit V shown in Figure 5. This is applied to the unknown state |ψ = α|0 + β|1 and (n − k) auxiliary qubits as follows The full (n − k)-bit Steane code stabilizer set S = {K i } is defined as follows The operation of each stabilizer effectively reduces the 2 7dimensional space to the 2-dimensional valid code space spanned by the {|0 , |1 } states. The stabilizer set K i ∈ S defines k = 1 logical qubit encoded into n = 7 physical qubits, and it is applied to the qubit register after the channel, as shown in Figure 5. The inverse encoder V † returns the n-qubit code word state based on the recovered k-qubit information state, denoted as |ψ .
It can be shown that the logical encoded states are and see [3], [40] for the full derivation.

C. NON-DESTRUCTIVE OPERATOR MEASUREMENT
This section describes how any error information hidden in the data can be extracted with the aid of a stabilizer measurements [33]. Let us now discuss how this is possible without measuring the data qubits directly 4 [3]. Figure 7 shows the general circuit construction of the measurement of a general single-qubit operator K . A single-qubit operator is considered for the ease of our discussion. However, in the context of a syndrome decoder this may extend to a many-qubit operator such as the K 1 = ZZI stabilizer in the repetition code [3]. The stabilizer is implemented by two Hadamard gates on either side of the control qubit of a controlled-K gate. If the control qubit is in the |1 state, then a K gate is applied to the target qubits. This circuit entangles the ancilla and data  qubits in such a way that the measurement of the ancilla qubit projects the data into the ±1 eigenstates of K .
Let us now consider this concept in more detail. Explicitly, consider that the K gate has eigenvectors of |v ± with corresponding eigenvalues of λ ± = ±1. Assuming that the input data qubits |ψ are in superposition of the ±1 eigenstates, we arrive at: where α and β are arbitrary probability amplitudes 5 satisfying |α| 2 + |β| 2 = 1. Let us describe the evolution of the system at each timestep of the circuit. First, the first Hadamard gate on the ancilla qubit will have the effect of Remembering that H |0 = |+ and |± = 1 is the state of the system before the controlled-K gate.
Next, the K gate is only applied to the data when the ancilla is in the |1 state, since this is the control qubit for the 5 Note that |ψ is the general case of a superposition of both legitimate and illegitimate code word states, i.e a superposition of ±1 eigenstates of K . The specific case where the state is error free is given by β = 0 where |ψ = |v + . In this case the outcome of the ancilla is always 0. controlled-K gate. This has the following effect on Eq. (23): Substituting Eq. (22) into the right hand side of Eq. (24) and bearing in mind that K |v ± = λ ± |v ± , then which describes the system after the controlled-K gate and before the final Hadamard gate. The final Hadamard gate again takes the ancilla qubit |0 → |+ and |1 → |− , therefore we have: Multiplying this out and simplifying it gives the system before the ancilla measurement formulated as Eq. (27) shows that a |0 is measured in the ancilla qubit with probability 6 |α| 2 . In this case the data qubits are in the |v + eigenvector. Relating this to a stabilizer code, this would indicate that the data resides in a valid code word state [34]. The |1 state is measured in the ancilla qubit with probability |β| 2 , indicating that the data qubits have been projected to the |v − eigenvector. The −1 eigenstates of a stabilizer operator constitute the subspace orthogonal to the code space, which means that it is an error that can be corrected [33]. Therefore if a |1 is measured in the ancilla qubit, it indicates that the data contains an error and a recovery operation is required to put the data back into the code space. This is how the quantum stabilizer measurement detects an error without directly measuring the data qubits.

IV. QUANTUM GATE ERROR AND FAULT TOLERANT CIRCUITS A. SINGLE QUBIT GATE ERROR
First, let us introduce the density matrix notation. The density matrix ρ of the pure state |ψ = α|0 + β|1 is given by 6 If the same calculation is repeated with the initial state as |v + , it can be seen that the outcome of the ancilla qubit is always 0. VOLUME 8, 2020 The density matrix is mathematically equivalent to the state vector notation |ψ , but gives an alternative way of describing the qubit that allows us to apply an error probability to the channel.
The bit-flip channel affecting a single qubit state ρ applies the X gate with probability p as follows which is analogous to a classical Binary Symmetric Channel (BSC) channel. The event of a gate error can be modelled by first applying perfect transformation of the gate U followed by the application of the bit-flip X [41]. This is shown in Figure 8 and described by In general, where any arbitrary single-qubit gate has a gate error probability of P g , any arbitrary single-qubit error can be encapsulated by the depolarizing channel [42]. This has the following transformation of a single-qubit state [30] where the initial state ρ is left unchanged with probability 1 − p and either the X , Y or Z gates are applied with a probability of p 3 [43]. The single-qubit gate error in the depolarizing channel is modelled with the aid of the same methodology as that of a gate error in the bit-flip channel characterized by Eq. (30).

B. CNOT GATE ERROR
A CNOT gate subjected to the bit-flip channel having a gate error probability P g may suffer from the error effects of IX , XI and XX with equal probability of Let us now assume that ρ = CNOT |ψ φ ψ φ |CNOT † is a two-qubit state evolved by the CNOT gate described by Eq. (2). Then a CNOT gate having a gate error probability of P g in the bit-flip channel is given by Given an N = 2-qubit gate, there are 2 N − 1 tensor products of the operators I and X . In general, with J individual operators in the channel and N qubits sent over the channel, there are J N − 1 channel operators excluding the operator associated with N identities. 7 In the case considered here, we have N = 2 and J = 2, hence there are 3 combinations of I and X in the bit-flip channel, excluding the operator II . These are applied with a probability of P g J N −1 , except in the case of no errors (i.e II ), which occurs with a probability of 1 − P g . Therefore the probability of a single error on the control or target qubit is identical to that of a simultaneous error on both the control and target qubit. A CNOT gate error in the two qubit depolarizing channel is the same as that in Eq. (33) except that 4 2 − 1 combinations of the J = 4 operators {I , X , Y , Z } are applied, each with probability P g 15 .

C. ERROR PROLIFERATION
Classical circuits are less susceptible to error propagation than quantum circuits. Error propagation is defined as the event where an error is passed on without increasing the number of errors. Let us consider the example of the classical OR gate in Figure 10. This is an irreversible operation, because it has two input bits and one output bit [44]. More explicitly, this gate takes input bits a and b and outputs c ≡ (a OR b). The input bits a and b are effectively forgotten, when the output is computed and cannot be recovered at the output of the gate. For example, the output bit c = 1 may arise from any of the inputs 01, 10, 11. Therefore the input is not uniquely recoverable after the gate has been applied to the information. This particular feature of irreversible gates is advantageous, when the input bits suffer from a bit-flip error. Consider for example that the binary input string 'ab' contains an error with Hamming weight wt(ab) ≥ 1. The output bit c that follows must have an error with wt(c) = 1, since it is a single bit. Therefore the overall number of errors in the circuit either remains the same or it is reduced even when the gate computes an erroneous input.
Unfortunately, this is not the case for the quantum Controlled-NOT (CNOT) gate, as seen in Figure 11. The dynamics of the quantum world are described by   transformations, which preserve the dimensions of the system. Therefore quantum gates are reversible, which means that the number of input qubits is the same as the number of output qubits [45]. For example, the quantum CNOT gate takes the two-qubit state |ab as its input and outputs the two-qubit state |ac , where again we have c ≡ (a OR b). Therefore, if the control qubit contains a bit-flip error, the output state has two bit-flip errors, for example |10 → |11 , as demonstrated in Figure 11. Explicitly, underlining indicates the erroneous positions.
Let us now consider this example in more detail, since the data in the control qubit a is erroneous, this means that the outcome of c = (a OR b) contains an error. This outcome is stored in the target qubit and carried forward to the next gate in the circuit, therefore future gates will further propagate this error. Additionally, the erroneous control qubit |a is not absorbed by the OR gate. Instead it is preserved in the control qubit, which may impose further degradation at a later time step. In effect, the CNOT gate has proliferated the control bit error to the target qubit and then failed to absorb the error it started with. Hence, a qubit error propagates throughout the circuit, wherever two-qubit gate connections are present. Specifically, an increase in the weight 8 of the error from the input to the output state implies that an error has been proliferated by the gate, potentially giving rise to avalanchelike error proliferation.
Note that error proliferation may increase the qubit error ratio even when the CNOT gate itself is perfect. A perfect gate has a gate error probability of P g = 0. Let us now consider the example of the [3,1,3] repetition encoder circuit shown in Figure 12. Assuming that the CNOT gates in this circuit are perfect, but a bit-flip error that occurred before the first CNOT gate is proliferated by the subsequent gates results in 8 The weight wt(S) of a quantum operator S is defined as the number of qubits that differ from the identity operator. Therefore wt(XIZ ) = 2. three individual qubit errors at the circuit's output. Therefore the circuit has increased the qubit error ratio with respect to the input, despite the application of perfect CNOT gates.

D. ERROR PROLIFERATION BY CNOT GATES
In addition to their own intrinsic gate errors, a CNOT gate may increase the error ratio in a circuit by proliferating preexisting qubit errors. If an X error corrupted the control qubit before the CNOT gate, then the gate has the effect of copying the control error to the target qubit, as seen in Figure 13 (a), which can be represented as [35] CNOT (XI )CNOT † = XX .
Similarly, the CNOT gate copies an existing phase error (Z ) on the target qubit, upwards to the control qubit, as seen in Figure 13 (b) and represented by:

E. DEFINITION OF FAULT TOLERANT QECC
A fault tolerant circuit construction mitigates both the gate error and proliferation error probability. Formally, a quantum circuit protected by an [n, k, d] QECC is said to be fault tolerant, if a single gate error occurring with probability P g results in less than t = (d − 1)/2 individual qubit errors at the output of the circuit [1], [34]. In other words, for a circuit to be fault tolerant the propagation of a single gate error must not overwhelm the QECC used for protecting the quantum circuit. For example, the repetition code's encoding circuit of Figure 12 is not fault tolerant, because a single qubit error may proliferate to t = 3 errors. Another example of a nonfault tolerant circuit is constituted by the Steane encoding circuit, of Figure 5, because a single CNOT gate error is proliferated to t = 3 qubit errors. Since the Steane code is VOLUME 8, 2020 a d = 3 code, this means that there exist single gate errors that cannot be corrected, as exemplified in [29]. The benefit of a fault tolerant circuit is that it guarantees that the QECC-protected scheme succeeds in achieving an error rate improvement compared to the unprotected scheme. For example, suppose that a component with error probability of P g is encoded by a circuit having x components. All x components may also be assumed to have an error probability equivalent to that of the uncoded gate, namely P g . To achieve fault tolerance, the QECC must be able to correct the qubit error probability for a total of x single gate error scenarios. This guarantees that the final error rate will be upper bounded by O(P 2 g ), which is the probability of two gates simultaneously incurring independent errors. Then the inequality characterizing the coded and uncoded scheme by O(P 2 g ) < P g is satisfied, showing that if the qubit error that results from a single gate error can be corrected, it is guaranteed that the QECC scheme will achieve a coded error rate improvement. If any single gate error is left uncorrected, then the coded error rate will be upper bounded by O(P g ) and the QECC protected scheme cannot offer better error rates than the uncoded scheme, namely we have O(P g ) > P g .

V. QECC IMPROVES QUANTUM GATE ERROR A. TRANSVERSAL GATES
The circuits that implement a QECC, such as the encoding circuit, must be themselves fault tolerant [7]. However we also wish to implement logical gates in order for our quantum processor to be more useful than just a quantum memory [24]. A fault tolerant method of improving the error rate of a realistic imperfect quantum gate is the scheme popularly referred to as the transversal gate [2], [33]. More explicitly, a transversal gate allows a logical gate to be applied to an encoded state. This scheme is characterized by the bit-wise application of the gate to an encoded state [11]. More specifically, to implement a single-qubit gate U transversely it is applied separately to each physical qubit in the n-qubit encoded state, as demonstrated in Figure 14 [33]. The left hand side of Figure 14 represents an single-qubit gate U applied to an arbitrary uncoded state. The right hand side shows that the transversal gate implementation U results in the same logical evolution of the encoded state, as U results in for an uncoded state. The bar above U (giving U ) indicates that this is a transversal gate. Explicitly, the application of U to a n-qubit encoded state |ψ has the same logical effect of applying the uncoded gate U to a k-qubit uncoded state |ψ . For example, the X gate applies a bit-flip to |ψ and X applies a bit-flip to |ψ . This can be views as X representing the k-qubit uncoded gate, while X is the n-qubit 'encoded' version.
You might wonder, why single-qubit transversal gates are fault tolerant? If the components introduce errors independently and the information is encoded in a d = 3 QECC, then an uncorrectable error may only occur when two independent components fail simultaneously. This happens with the probability of O(P 2 g ), therefore achieving a beneficial error-rate improvement compared to the uncoded single gate.
Error proliferation may hence be circumvented by a fault tolerant gate construction, as shown in Figure 1. Specifically, a transversal CNOT gate is applied on a bit-wise basis from the ith qubit in the encoded control state to the ith qubit in the encoded target state. Figure 1 shows that the CNOT gates are specifically arranged in a way so that the qubits are coupled with no more than a single CNOT gate connection. This means that a single error in an encoded block may propagate to no more than a single error in the other. This erroneous scenario can always be corrected by the syndrome decoder, since both the control and target qubits are encoded independently by an [n, k, d] QECC. Therefore an uncorrectable error may only occur when two CNOT gates simultaneously incur an error with probability O(P 2 g ), which satisfies the conditions of fault tolerance.

B. PROCESSING QECC-INFORMATION BY LOGIC GATES
Logic gates can be applied to QECC-protected data, because the QECC does not treat any permutation of a code word by a legitimate logical gate as an error. Instead, the logical gate has the effect of transforming the data from one legitimate code word to another, provided that the transversal gate is carefully matched to a certain QECC, as described in this section.
Firstly, what kind of error is detectable by a general stabilizer code? A correctable error E for a stabilizer code S is constituted by the sub-group of G n defined in Eq. (7) that anticommutes with S, where we have KE = −EK . For example, if K ∈ S and |ψ is a legitimate defined code word, then we have: where E ∈ E. The error has the effect of shifting the logical qubit out of the legitimate code space. The negative phase value can be measured by the syndrome measurement and a subsequent recovery operation can be applied to reverse the effect of E.
If the measurement of the stabilizer operator results in an +1 eigenvalue, it is assumed that state |ψ is a legitimate code word satisfying that K |ψ = |ψ . However, if an errorcorrupted state |ψ = E|ψ is inserted into this equation, then we arrive at K |ψ = |ψ indicating that the error E cannot be detected by the QECC. If an error commutes with the stabilizer, it has the property of KE = EK . Then we have which gives the definition of an error that cannot be corrected by a stabilizer code [33]. This is because the stabilizer measurement results in an +1 eigenvalue, which is interpreted as being in the legitimate code space. More formally, the set of elements in G n in Eq. (7) that commute with the stabilizer EKE † ∈ K ∀ K ∈ S are the normalizer 9 of S in G n , denoted by N ( S) [34]. If an error commutes with the stabilizer, it is undetectable, therefore this has the effect of an uncorrectable error E. More formally, E ∈ N ( S) − S.
A transversal gate U has the same properties as an uncorrectable error, because when a valid encoded gate is applied to an encoded state, it will return another legitimate encoded state [31]. In other words, the code will not detect an error, when the gate is applied to the encoded qubits. This reveals the set of transformations that act non-trivially on the code word, yet do not shift the information outside the legitimate code space.
Let us look at this idea from the perspective of applying quantum gates to encoded qubits. A general encoded gate U evolves the encoded data according to |ψ 2 = U |ψ . This state would be stabilized by an updated stabilizer U K U † , which has the intended effect This is reminiscent of the ordinary stabilizer K |ψ = |ψ , which leaves a legitimate code word unchanged. Then a 9 The set U such that U G n U † = G n is the normalizer of G n , denoted by N (G n ). transversal gate U is chosen for ensuring that where the encoded gate conveniently has no effect on the stabilizer set. How is it justified that certain transversal gates have this property? When S and U commute, then SU = U S. This means that remembering that U U † = I . Therefore the transformations U carried out by legitimate transversal gates for a given code S are those, which commute with the stabilizer.
For example, a transversal bit-flip gate corresponds to the bit-wise application of the X gate to each physical qubit, denoted as X = X ⊗n . For the Steane code, X is implemented by applying n = 7 X gates directly to the physical qubits of the encoded data. To check that X has the intended logical transformation, X can be applied to Eq. (20) and Eq. (21). Then to transform |0 to |1 we get X |0 = |1 and vice versa. Similarly, Z = Z ⊗7 has the effect of the logical phaseflip, where Z |0 = |0 and Z |1 = −|1 can be used for distinguishing whether the logical qubit is either |0 or |1 . Since we have XZX † = −X and ZXZ † = −Z , the stabilizer set in Eq. (19) remains unchanged. For example,

VI. SYSTEM MODEL
The scheme seen in Figure 15 encodes a pair of unknown qubits |φ 1 and |φ 2 using the unitary encoding circuit V. The encoding at the top left corner of Figure 15 can be described as The state |φ 1 can be stabilized by S = {K i }, which is expressed as VOLUME 8, 2020 In this model S = {K i } corresponds to the n − k stabilizer operators. By measuring the stabilizers S the location of an error in the data qubits can be determined. If there is an error, the recovery operation R is applied to the data for returning it to a legitimate code word state. The encoded control and target qubit are input to the transversal CNOT gate labelled by U f , as seen in Figure 15. This block represents the logical action of a CNOT gate applied to the encoded qubits. The transversal CNOT gate U f evolves the encoded state |ψ 1 = |φ 1 |φ 2 to |ψ 2 as follows: This is stabilized by U f SU † f . Assuming that the transversal CNOT gate represents a legitimate logical transformation for the chosen code, the stabilizer set remains invariant to the application of U f , so that This allows the intended logical evolution of the encoded information to be preserved and any single qubit error occurring within the data to be corrected.

1) FRAME-ERROR-RATE
Let us now consider the example of a transversal CNOT gate protected by the 1 3 -rate repetition code of [29]. If more than one qubits in the 6-qubit frame have a bit-flip error at time step |ψ 3 this will be counted as one frame error. A single qubit error occurring within the top or bottom n = 3 qubits after U f , i.e. in |ψ 2 seen in Figure 15, can be corrected because in this scheme the control and target qubits are encoded individually. For example, two qubit errors, one on qubit 2 and the other on qubit 5, can be fully corrected, hence no frame error is encountered at |ψ 3 . This is because qubit 2 is corrected by the upper syndrome decoder and qubit 5 by the lower syndrome decoder. However, a qubit error on the first and second qubit cannot be corrected by the upper decoder, since both qubit errors are processed by the same d = 3 syndrome decoder. Therefore this scenario incurs a frame error at |ψ 3 .
The frame-error-rate (FER) is defined by considering all operations involved in the calculation of |ψ 3 , yielding The FER 3 is a useful metric because it characterizes the integrity of the transversal CNOT gate.

A. QUANTUM CHANNEL MODEL
In this model seen in Fig. 16 each gate of the circuit is assumed to be an independent potential error location with a probability of P g . Then an independent individual qubit channel is applied after this. The motivation for this hybrid model is that qubit errors may not occur at the gate output as independent events [41], hence the gate errors must also be modelled individually with a probability of P g . This is because error proliferation results in correlated qubit errors, which systematically spread through the two-qubit gates, as detailed further in Section IV-C. In this hybrid channel model, we assume that each CNOT gate has a gate error rate probability P g . In addition to gate errors, the qubits may also suffer from decoherence with a probability P e , which encapsulates the effects of all other circuit errors. Under these assumptions the uncoded circuit has the following FER as shown in Figure 16. This channel model can also be applied to the coded system model of Figure 15. In this case the blocks V and U f have independent gate errors, which may however have a similar P g . Hence, gate errors occur at gate locations specific to the circuit construction for the particular QECC chosen. Then an independent qubit flip channel is applied at position |ψ 2 of Fig. 15. Note that it is assumed that the circuits of S and R are fault tolerant and therefore the gate error probability in these circuits is negligible [1].

B. SIMULATION ASSUMPTIONS
This section makes clear the assumptions made in this simulation: • It is assumed that FER ≤ 1 for a given combination of P g and P e . Hence, for this simulation P g and P e are considered to be 0.1 or smaller [46]- [48].
• In this simulation each of the gate errors and qubit errors are simulated independently. Therefore, all combinations of component errors are encompassed by this simulation, which is run 10 6 times for each data point. The most common scenario is a single-component error, namely a gate error with a probability of P g or a single qubit error with a probability of P e .
• The circuit gate error events are modelled by an independent random variable, which determines the qubit error incurred by each gate error. It is necessary to simulate each gate separately in order to encapsulate the effects of error proliferation in subsequent circuit components. Error proliferation within the circuit outputs a pattern of qubit errors specific to the circuit architecture. The simulation results reflect this and the effect of error proliferation on the FER.

VII. RESULTS
In this section we will derive various FER bounds, which are then verified by simulations.

A. A 1 3 -RATE REPETITION CODE
Let us first consider the frame error events imposed by pure gate errors in the absence of bit-flip errors. For a circuit block having a total of D components and identical gate error probabilities P g , we can compute the upper bound of the FER before error correction as where η i is given by the binomial coefficient defined by icombinations of D circuit components. The coefficients η i is then reduced to η i by the number of i-component failures, resulting in an error pattern corrected by syndrome recovery. As for the frame error events caused by the pure bit-flip channel having a flip probability of P e , at the right of Fig. 16 the state of having no qubit errors at the output of either the control or the target sub-block occurs with probability (1 − P e ) 3 . A correctable single-qubit error in any position occurs with probability 3P e (1−P e ) 2 . Any uncorrectable error in either sub-block incurs a frame error, therefore the FER after the recovery operation can be calculated as Let us now combine the FER contributions of both the gate errors and bit-flip errors of Eq. (5). However, for simplicity, we consider only the dominant term of i = 1 in the gate error bound of Eq. (46), explicitly this is the dominant term, because having several instantaneous gate errors has a lower probability. Upon computing the decoded FER, we arrive at: Since the term of 6P 2 e in Eq. (48) can be deemed negligible, for the coded scheme to offer a FER improvement it is required that P g ≤ 2P e . In Figure 17 we have plotted the FER vs. the gate error probability for both an uncoded CNOT gate as well as for its 1 3 -rate repetition-coded counterpart using dashed and continuous lines, respectively. The FER results are parameterized by the bit-flip probability of our quantum channel model of Figure 16. The circles in the figure indicate the specific P g values, below which the 1 3 -rate repetition code provides FER reductions. The curves are parameterized by the bit-flip probability P e defined in Figure 16. To elaborate further, Figure 18 shows that when P g is smaller, the coded scheme provides more rapid FER improvements, achieving FER ≈ 2P g , where 6P 2 e is negligible. However,when we have P e P g , the coded scheme's FER is dominated by the correlated gate error patterns encountered before recovery. Therefore the FER floor is determined by 2P g . The repetition coding scheme has D = 7 components, so we have η 1 = 7 in Eq. (46), meaning that η 1 = 2, as detailed in the next section.

B. FURTHER EVALUATION OF REPETITION CODING
In this section the method of finding the analytical FER = η 1 P g = 2P g is discussed in detail. We commence by considering the accumulated error probability before error correction at |ψ 2 and determine how much this is reduced by with the aid of syndrome decoding. VOLUME 8, 2020 First, let us find the total accumulated error probability before syndrome decoding, as represented by the FER at |ψ 2 in Figure 19. The circuit has D = 7 CNOT gates, each having gate error probability of P g . Assuming that the gate errors are independent, the FER at |ψ 2 (FER 2 ) is dominated by the sum of all the single CNOT gate error probabilities. Note that in this example the combinations of two, three, . . . gate errors occurring with probability O(P 2 g ), O(P 3 g ) . . . are ignored, since the probability of these scenarios in this channel model is low. Therefore, we have Naturally, we expect that some error patterns after a single CNOT gate error can be corrected by the syndrome decoders. This means that the final error rate at |ψ 3 will obey: where η is a scaling coefficient that we have to find by exhaustively considering every error pattern occurring at |ψ 2 . If a pattern can be corrected by the syndrome decoders, its probability of occurrence is subtracted from Eq. (49) for determining the experimental gate error probability, yielding the final FER 3 . Then the natural question arises, how many different error patterns are accumulated at |ψ 2 in Figure 19 after the occurrence of specific single CNOT gate errors? Each CNOT gate in the circuit may suffer from any of the three possible bitflip error patterns of IX , XI , XX shown in Figure 9 with a  Fortunately, we do not have to consider all 21 error patterns individually. Quantitatively, we will demonstrate later in this section that we only have to analyze 6 patterns. Let us commence by considering the gate error in the transversal CNOT gate section U f of Figure 19. This section is constructed from 3 CNOT gates and therefore contributes a total of 3P g to FER 2 in Eq. (49). Since the control and target qubit of each CNOT gate is finally input into separate syndrome decoders, any bitflip error combination IX , XI or XX imposed on the control and target qubit of these gates can be corrected before |ψ 3 . This is a benefit of the transversal gate being constructed fault tolerantly and therefore no error proliferation takes place in this section. Hence we do not have an error event that cannot be corrected [33]. Therefore, Eq. (49) may initially be reduced by 3P g so that we have: since any individual error patterns resulting from these gate errors will be corrected. Now, only the gate error in the top and bottom encoder of Figure 19 has to be considered individually. There are four CNOT gates in total, which accounts for FER of 4P g in Eq. (51). Let us commence by only considering the top encoder in Figure 19, which has two CNOT gates to consider (2P g ). This encoder has 6 possible error scenarios in the bitflip channel. Table 3 shows a comprehensive assessment of the error pattern on the n = 3 qubits at the output of the encoder for each bit-flip scenario. Inspection of Table 3 shows that 3 out of the 6 error patterns contain only a single bitflip error. Then the operation of U f in Figure 19 copies the same error pattern to the bottom three qubits, which is then entered into the lower syndrome decoder. So a single error entered into the top syndrome decoder will lead to a single error input to the bottom one, both of which can be corrected. Therefore error proliferation in the subsequent CNOT gates can be avoided. Each scenario occurs with probability P g 3 , therefore 3 × P g 3 = P g is the probability of frame error after any gate error in the top encoder.
Hence, Eq. (51) can be reduced by P g , giving ηP g < 3P g . The only CNOT gates left to consider are those in the lower encoder V lower . This has the same circuit structure as the upper encoder. Therefore, Table 3 also describes the probability that the gate error occurring in the lower encoder will lead to an error that can be corrected. Hence the final FER 3 at |ψ 3 of Figure 19 after all possible CNOT gate errors will be which yields η = 2 in Eq. (50).

C. TRANSVERAL CNOT GATE PROTECTED BY STEANE's CODE
Since Steane's encoding circuit V is not fault tolerant, its FER is upper bounded by The constant η 1 is determined by the specific error patterns produced by single gate errors that cannot be corrected. This process is demonstrated in Fig. 5, where the error imposed on the first CNOT gate leads to a larger number of errors at the circuit output, causing error proliferation. Subsequent CNOT gates copy this error throughout the circuit. Therefore the proliferation of the error resulting from the initial single gate failure results in multiple qubit errors that cannot be corrected at the circuit output. Since the initial CNOT gate failure occurred with probability P g , this error event will add a term of O(P g ) to the FER. The independent gate error is modelled by assuming an error location at each two-qubit CNOT connection in the circuit. Each gate failure is simulated as a perfect gate followed by Pauli operators acting on the individual qubits defined by the statistics corresponding to the depolarizing channel [41]. All other component errors are modelled by a single-qubit depolarizing channel after the block labelled U f , as seen in Figure 15. This incurs a frame error rate of where η 2 is the number of two qubit error combinations in the block that cannot be corrected by the upper and lower syndrome decoder of Figure 19.
The coded scheme provides frame error rate improvements, when the resultant error rate is lower than that of the uncoded scheme, namely when FER (1) + FER (2) < P g + 2P e . Rearranging this gives the gate error threshold P g < P th , which is the gate error rate below which coded improvements are possible. This is defined by a condition for P g and P e in conjunction with one another. Therefore the gate error threshold is given by which is the point at which the coded scheme starts to have a better FER than the uncoded scheme. A drawback of this scheme is that the FER is improved in line with a reduction of P g < P th , as indicated in Fig. 21. Fig.5 shows that the proliferation of qubit errors by CNOT gates in Steanes code leads to the correlation of qubit errors at the output of the Steane encoding circuit. Therefore a set of error patterns occurring with probability O(P g ) consisting of t > 1 individual qubit errors accumulate before the transversal CNOT gate. Hence, the application of Steane's code introduces more errors than the uncoded scheme has, when the gate error probability is high. The effects of error proliferation overloading the decoder are seen in Figure 22, where the resultant FER is lower-bounded at ≈ 20P g .
However, our results demonstrate that coding is indeed beneficial, when the statistically independent qubit decoherence probability P e is approximately an order of magnitude higher than P g for counteracting the effects of correlated VOLUME 8, 2020 errors. This is due to the fact that Steane's code is capable of correcting statistically independent individual qubit errors, since it has a minimum distance of d = 3. More specifically, Figure 21 shows that an uncoded system would suffer from an FER floor at 2 × 10 −3 , when the qubit decoherence error probability is P e = 10 −3 . However, a Steane code assisted system is capable of reducing the FER below 2 × 10 −3 , provided that the gate error probability is lower than P th = 1.1 × 10 −4 .

VIII. CONCLUSION
Fault-tolerant QECCs are capable of encoding unknown states [1]. This is because the traditional unitary encoding circuits are not fault tolerant. Practical quantum circuits experience both gate-induced qubit errors with a probability of P g as well as qubit errors imposed by the decoherence probability of P e . We found that improved logical qubit reliability can be attained using non-fault tolerant QECC's when P e is an order of magnitude higher than P g . However, this imposes a strict condition on our quantum channel model, where the channel parameters have to obey the specific conditions unveiled in this treatise. In our future work, we will design fault tolerant schemes for encoding unknown states in the face of realistic quantum impairments using bespoke QECCs. Another direction for this simulation is to consider circuits, which have more transversal gates. A single transversal gate can be implemented in each error correction step. Therefore, multiple transversal gates can be constructed by repeatedly implementing the scheme presented here in succession for a certain circuit depth. This can be tested by simulations for determining the effect of circuit depth on the gate error rate thresholds.