Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications

The Coordinate Rotation Digital Computer algorithm (CORDIC) is a simple mechanism to compute a set of elementary functions, such as trigonometric functions, using fixed-point devices. It is widely adopted, also in applications running in harsh environments such as space, where radiation is a cause of errors in nanoelectronic devices. A single event upset in a configuration bit of a Field Programmable Gate Array (FPGA) can completely change the behavior of the implemented circuit, so it is important to detect and reconfigure the FPGA when this happens. Dual modular redundancy is the typical method to detect errors in electronic circuits, but it has an important overhead in area and power consumption and it does not provide any additional functionality apart from the activation of the FPGA reconfiguration trigger in presence of error. This paper presents two ad-hoc techniques to protect the Digital Direct Synthesizer with CORDIC when it is implemented into an FPGA, with limited overhead in terms of area and power consumption when compared with the traditional solution. The first solution slightly increases the percentage of undetected errors, about 11%, reducing to almost half the area overhead of the circuit. The second solution introduces a trade-off between the percentage of error detection and the precision of the trigonometric output of the CORDIC by means of a polymorphic structure with lower area resources than the existing solutions. This last proposal allows the system to increase the precision of the digital synthesis signal under absence of errors or to activate the error protection in scenarios with external disturbances such as radiation.


I. INTRODUCTION
The Coordinate Rotation Digital Computer (CORDIC) algorithm [1] is a hardware efficient algorithm that can compute a set of elementary functions [2] including trigonometric and logarithmic functions, complex number multiplication and division, or matrix inversion. The power of the CORDIC algorithm relies on the fact that it can be easily implemented in fixed-point devices such as Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) [3].
The CORDIC algorithm is present in digital modulation [4] or the robotics field [5], and can be used to compute the discrete cosine transform [6], the Hartley transform [7], or the singular value decomposition [8]. Moreover, the CORDIC algorithm is also used in space applications where sin(ωt) and cos(ωt) signals need to be digitally generated.
The associate editor coordinating the review of this manuscript and approving it for publication was Jenny Mahoney. This process is called Digital Direct Synthesis (DDS) [9]- [11]. For instance, digital Quadrature Amplitude Modulation (QAM) transceivers require a CORDIC module to digitally down-convert the received signals to intermediate frequencies or base-band (i.e. digital mixer), and heterodyne receivers, which are extensively used in satellites, use it for the frequency synthesizers. Another example of the current and future use of the CORDIC algorithm is the Laser Interferometer Space Antenna (LISA) gravitational wave interferometer that will use a CORDIC-based phase-meter to compute the optical path length differences [12], [13].
In harsh environments such as space, the electronic devices may fail due to the elevated radiation level if they are not properly protected. This means that the previously mentioned systems may stop working or start behaving in an erroneous way. An inexpensive alternative to traditional radiation-hardened integrated circuits is the implementation of customized hardware designs in Commercial Of-The-Shelf (COTS) devices that take into account the radiation effects. VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ These protected designs are used to mitigate or prevent errors caused by the environment such as Single Event Upsets (SEUs) or cumulative errors. In digital architectures implemented on FPGAs, a method to detect the misbehaviour of the circuit is required. The typical method used to detect errors is called Dual Modular Redundancy (DMR) or duplication with comparison (DWC) [14], [15], and consists in using a redundant copy of the circuit and extra voting logic. If an error affects one of the two copies, it will be detected by comparing the output of both copies [16]. However, critical space applications have severe power and area restrictions that in some cases are not possible to achieve with classical protection approaches such as the DMR.
Apart from the actual constraints, there are also some kinds of applications that can tolerate a certain error rate, or in other words, they do not need that 100% of the samples are correct. An example of this is video or audio transmission, in which a certain number of wrong samples would degrade the quality of the output, but it could be acceptable if the error rate is reasonable. The bottom line is that using exhaustive protection techniques like DMR increases the area and power overheads considerably, in exchange for a full protection that may not be needed.
This leads to the concept of ''adaptive protection'', by which a system would adopt a weaker protection technique if the application requirements and the environment allow to do so, thus reducing the overheads. In this way, there can be a wide set of ''intermediate'' protection techniques (ranging from the unprotected circuit to the DMR-like full protection case), that designers should explore in order to choose the most appropriate for each application, and therefore produce a custom-tailored solution. Note that this adaptive protection approach fits very well the FPGA implementation, since being able to dynamically reconfigure the device provides the ability to change the protection level when needed.
In this context, several customized protection techniques will be analyzed and developed in this paper to either reduce the overhead of the protection circuits and by hence the area and the power consumption of the global system [17], [18], or to take advantage of the overhead to provide a new or an improved functionality. These ad-hoc techniques can be divided into Algorithmic-Based Fault-Tolerance Techniques (ABFT), in which the error detection is achieved by exploiting arithmetic properties of the algorithm [19], [20], and techniques based on exploiting structural properties of the design to create a protection scheme [16]. Other approaches, which are out of the scope of this paper, are based on analog circuits that give support to digital designs to detect faulty behaviors [21] and powerful error correction codes to protect the FPGA hardware from soft errors, which involve iterative processes at a larger timing cost [22], [23].
In this paper we present two protection techniques as an alternative to the DMR protection approach. As previously pointed out, the idea is that DMR would still be used whenever strong fault-tolerant restrictions apply for the specific application, while the proposed techniques can be set in place in scenarios where the application can trade a slight increase on error rate in exchange for some area and power savings (i.e. in Cubesats where there are important power restrictions).
The first technique is an ABFT technique based on using the trigonometric properties of the CORDIC algorithm. A circuit that performs the operation sin 2 (ωt)+cos 2 (ωt) over the In Quadrature (IQ) output components of the CORDIC has been included. The output of this circuit must be a low amplitude oscillation (due to the limited precision of the CORDIC) around a mean value of 1. Errors can be detected by setting an appropriate threshold in the output comparison logic. The objective of this technique is just to keep area resources as low as possible.
The second one is a polymorphic protection that exploits the structure of the CORDIC algorithm. Basically it consists of two cascade CORDICs that can be configured as a Digital Direct Synthesizer with more precision, when no faults are expected, or as two CORDICs where the inputs of the second one are reversed to generate a signal for error detection. It will be shown how the outputs of the second CORDIC, in the error detection mode, have to be constant in the absence of errors, matching with the input constant of the first CORDIC. In the paper, it is concluded that, with these two approaches, acceptable results can be obtained with a fraction of the resources needed for the implementation of a full DMR.
This paper is structured as follows: in Section II the CORDIC algorithm and the architecture that has been implemented for DDS are explained. In Section III the circuits designed to detect the errors in the architecture are shown. The error injection setup is detailed in Section IV and in Section V the error injection results of the customized circuits are presented. Area and detection rate are analyzed and compared between the different architectures. In Section V the main conclusions of the paper are summarized.

II. CORDIC ALGORITHM FOR SIN AND COS GENERATION
In this Section, the CORDIC algorithm and the particular architecture implemented for DDS are explained in detail.

A. CORDIC ALGORITHM
The basic operation of the CORDIC algorithm is to rotate vectors. Given a vector in Cartesian coordinates, v = [x 0 , y 0 ], where x 0 and y 0 are the abscissa and ordinate respectively, the CORDIC algorithm rotates it an angle ϕ to obtain a new vector v = [x n , y n ].
The rotation is performed iteratively by small angles as: Therefore, the total rotated angle is: where d i can be either +1 or −1 depending on the direction of the rotation. Every rotation is called pseudo-rotation, and their equations are given by: where, z i is called angle accumulator and includes all the rotations made in the previous iterations. The pseudo-rotation for the i th iteration alters the magnitude of the rotated vector, so it must be scaled by a factor K i : where, K n is the scaling factor for n stages. Its value is given by the following equation: For the rotation of the angle ϕ, the small angles α i that must be added or subtracted during each rotation can be stored in a Look-Up Table (LUT). Their values are shown in Table 1. Equations (3) to (5) can be implemented in an FPGA or in an ASIC using the parallel architecture shown on Fig. 1. However, this architecture is only capable of rotating a maximum angle of ±α = 1.7401 rad for 10 stages. Given the values of Table 1 for 10 stages the relative error in the sin and cos waves would be of 3.15 · 10 −4 .
This issue can be easily solved by adding an initial stage that makes a first iteration of ±π as follows:

B. DDS FOR SIN AND COS GENERATION
Based on the parallel architecture given on Fig. 1 and the angle extension described in Equations (8) to (10), the 10 stage CORDIC algorithm shown on Fig. 2 has been designed to generate digitally sin (ωt) and cos (ωt) signals. The input to x 0 is 1/K 9 , where K 9 is the scaling factor for 10 stages, 1/K 9 = 0.607253. The input to z 0 is a saw-tooth signal generated using the integrator shown on Fig. 2  This circuit is used in heterodyne systems, where the signals are down-converted to base-band by multiplying them by cos (2π · P · f min ) and sin (2π · P · f min ) that depend on constant P.
As it was mentioned in Section I, the CORDIC algorithm is extensively used in all digital QAM transceivers and in heterodyne interferometry. For instance, in the LISA gravitational interferometer it will be used to down-convert the optical frequencies to base-band (∼40 MHz).
The detailed pipeline is shown on Fig. 3. This is the golden design that has been used to evaluate the different protection circuits proposed in this paper.

III. PROPOSED PROTECTION TECHNIQUES
In the next subsection two protection techniques are proposed: an ABFT technique based on trigonometric properties of the CORDIC algorithm, and another one based on structural properties of the hardware design that extends the functionality in addition to the error detection.
It is important to remark, before explaining the techniques, that an error in an ASIC device would temporarily affect the behavior of the circuit. Once the error is flushed out, the circuit would continue its normal operation [24]. The error model in an FPGA is more complicated: a persistent error can change the configuration of the FPGA and therefore the behavior of the circuit will be erroneous requiring the reconfiguration of the device to restore its normal operation [25], [26]. This means that the fault caused by a soft error in the configuration memory of the FPGA would not VOLUME 8, 2020  be acceptable for the CORDIC (or the application using it) as the change in the circuit makes the error persist indefinitely.
One last comment is that the proposed techniques have been oriented to the single event mode in FPGAs, i.e., it is assumed that only one error will be present in the system at any time. This is a common assumption in the literature, since single errors represent the majority of events in space applications. In [27], it can be seen that for FPGAs using the 28nm technology node, Multiple Bit Upsets (MBUs) are less frequent than Single Event Upsets (SEUs). Despite that, the following techniques would reach a higher error detection rate in the presence of MBUs, as they look for divergences from two constant values. With MBUs, a higher number of errors will increase the probability of larger differences to be produced in the outputs. Note that each error in one iteration has a greater impact in the next one. For example, when a single bit event happens in the first iteration, that error increases to a more significant one in the next iteration due to the shift of bits in the following stage, having greater impact (see Fig. 1).

A. TRIGONOMETRIC PROTECTION
This first technique demonstrates how an ABFT approach can be followed to protect a circuit with algorithmic properties. An interesting and simple protection technique that can be applied to this particular case (generation of cos (2π · P · f min ) and sin (2π · P · f min )) is the following trigonometric property: In order to implement the previous equation in hardware, a circuit that adds the squared outputs has been included in the system (see Fig. 4). If the sum of the outputs verifies the property given in Eq. (11) it is assumed that there are no errors in the CORDIC. If it does not, then it is implied that an error has occurred.
However, the protection is not as simple as a straight comparison due to the precision of the circuit. In other words, the output of the circuit will have a small oscillation with amplitude γ , due to the finite precision of the CORDIC, around a mean value equal to one, 1 ± γ , i.e. for a 10-stage CORDIC and 8-bit inputs γ = 0.0036. To handle this, the protection will compare if the output is in the [1 − γ , 1 + γ ] range. In the event that there is an error, the output of the protection circuit will be most of the times out of the [1 − γ , 1 + γ ] boundary. However, it may happen that an error with a magnitude lower than γ happens, and in this case the technique would not detect it, as will be seen later in the results of the conducted experiments. Finally, regarding the timing, it should be mentioned that two extra cycles are required, one to register the output of the multipliers and another one to register the output of the comparator logic.

B. INVERSE CORDIC POLYMORPHIC PROTECTION
In certain cases, some ad-hoc protection schemes that occupy less area than a DMR can also be found by exploiting the structural properties of the algorithm when implemented in hardware. The technique used in this paper consists in using a second CORDIC that inverts the effects of the first one. In other words, the outputs of the CORDIC are fed into another one that reverses the process, and therefore the output of the latter should match the original input, if no errors are present.
Structural-based protection circuits can still achieve a high error detection rate. In the case of the CORDIC setup shown on Fig. 5, the outputs of the first CORDIC are fed into the second one in reverse order. The outputs of the second CORDIC are the inputs of the first one with small oscillations: where β is the amplitude of the oscillation. In the absence of error both outputs will be bounded in the following intervals: In the event that there is an error, the output of the protection circuit will be out of the bounds given in Equations (14) and (15). Therefore, an error could be easily detected and flagged by setting a threshold, i.e. for 9 stages and 8-bit inputs β = 0.0016 and for 4 stages and 8-bit inputs β = 0.0139. The thresholds have been established in all the examples and experiments provided in the paper according to the measures of the outputs of real FPGA's implementations. The margin of error was set comparing the outputs of the cycles of the DDS and the output of a Matlab and a System Generator golden model.
In Fig. 5, a 10-stage CORDIC pipeline is shown. It should be mentioned that the second CORDIC, the one used to detect the errors, does not necessarily need to have the same number of stages as the first one (see Fig. 6). A lower number of stages can be used to still achieve a high error detection rate, while reducing the area overhead introduced by the protection technique.
The precision of the CORDIC depends on the number of stages i used. Therefore, the fractional bit-widths of the different CORDIC taps must be increased accordingly to achieve the given precision. As a suggested methodology, once the number of stages and the CORDIC bit precision required by the application are fixed, a target detection rate should be defined and then, via experimentation, the number of bit-precision required for the different inputs and constant VOLUME 8, 2020 can be fixed to the minimum, to reduce consumption and area, i.e. in the next section, for comparison proposals, the 8-bit input was selected and data width grow through the different iterations until an 18-bit output, to avoid precision loss. At that point, increasing the number of bits will not improve the error rate detection and the overhead will be optimized. The overhead for the inverse CORDIC polymorphic protection is always proportional to the number of stages added to the original design.
On the other hand, it is important to remark that the detection-related CORDIC does not generate an output 1/K j , being j the number of stages of the detection-related CORDIC. The output in detection mode is always equal to the input of the CORDIC that is going to be protected, i.e. in this example 1/K 9 . Note that in the detection mode, the inputs of the CORDIC are not constant. They are sine/cosine signals, and the angle accumulator is equal to the first CORDIC, so the unit is not working as a DDS [3]. Hence the vector that is obtained at the output is related with the input that was applied in the first CORDIC. Then the number of stages of the additional CORDIC will only influence in the precision of x 9 and y 9 , in other words, in the amplitude of the threshold β. The implementation of the proposed structural protection technique in this manner offers two advantages. On the one hand, as described before, it can be used as an error detection system. On the other hand, it could also be used to extend the number of stages of the original CORDIC and by hence to increase its precision if needed, in absence of error. Therefore, the hardware required for this protection techniques is, at the same time, creating a polymorphic circuit that can work in two different modes: 1) In environments or missions with low radiation, it can be used as an extended resolution CORDIC. 2) In environments or missions with high radiation, it can be split into a lower resolution CORDIC and an inverse CORDIC for error detection purposes. In Fig. 6, the two mentioned modes or functionalities are selected by using a multiplexer where the select signal is labeled as ''Function''. In fact, we could go one step further and create a design that adaptively selects the number of stages used for the protection depending on the radiation level of the environment. In order to provide some insight about that, the effect of the inverse CORDIC stage variations in the error detection rate and the area resources has been studied in Section V. One additional consideration that has to be taken into account is that the injected errors can also affect the final comparator of the protection techniques. However, if a configuration memory error affects the mentioned comparator, a false positive may occur. These detected errors do not modify the outcome of the design but have to be corrected by reconfiguring the FPGA to restore the error detection capabilities of the protection technique itself.
Finally, regarding the timing, it should be mentioned that only the first, middle and final stages have pipeline registers. Therefore, the delay added to the unprotected CORDIC with this design will be equal to 4, three registers for the protection circuit and one to register the output of the comparison logic.
For the sake of comparison with traditional protection techniques, a DMR scheme has also been implemented. DMR is the usual approach followed in FPGA designs when error detection is needed. This is due to the previously mentioned FPGA error model, in which configuration errors have to be removed by rewriting the correct bit in the configuration memory, typically by reconfiguring the device. A DMR consists of using an identical redundant system that uses the same inputs as the first one (see Fig. 7).
In this context, the outputs of both copies should be identical. In the event that they are different, it means that an error has occurred in either one of the copies or in the extra voting logic. The area overhead for this type of architectures is typically higher than 100% because extra logic is required to compare the outputs. In FPGAs, the error detection rate obtained with a DMR scheme is slightly lower than 100% because there are also errors that the technique cannot detect, which are those affecting the input/output routing and the extra logic. Additionally, routing errors such as the generation of open/bridges between redundant branches (e.g. when sharing a multiplexer) can produce undetected errors [28]. Finally, and in order to register the output data, an extra clock cycle is required.

IV. EXPERIMENTAL SETUP
The protection circuits described in the previous section (trigonometric protection, inverse polymorphic protection, and DMR), as well as the unprotected CORDIC parallel architecture shown in Fig. 2 with 10 stages (which will serve as the reference design) have been designed using VHDL and implemented in an Digilent Nexys 4 DDR Artix-7 FPGA. The fault injection process has been conducted by using the Xilinx Soft Error Mitigation (SEM) IP Controller [29]. With this module, and using a MATLAB script running in a computer to control the IP, exhaustive fault injection campaigns 1 have been performed for each design in which every design-related configuration memory bit is tested. In particular, single-error fault injection campaigns have been carried out. The procedure is as follows: 1) An error is injected using the SEM IP in one of the essential bits of the design. An essential bit is a configuration bit that may produce an error. The injection addresses of the DUT have been obtained with the ACME tool [30]. 2) The circuit is exercised and the output is compared with the previously calculated golden (error-free) output during 10 3 periods of the sine/cosine generated signal. The golden output is the output of the unprotected CORDIC parallel architecture of Fig. 2. The behavior of the circuit is logged (the results of the simulation are stored in a file) and the previously injected error is removed. 3) A new error is injected in a different essential bit of the design, and the process is repeated.
The campaign ends when all the essential bits of the design are injected and tested, performing an exhaustive fault injection campaign. Since all the essential bits are targeted, each one of the implementations receives a different number of injections, being the circuits that occupy more area the ones that receive more errors. This is consistent with the fact that larger circuits offer a larger cross-section to radiation.
As mentioned at the beginning of this section, the trigonometric, the inverse polymorphic, the DMR, and the unprotected CORDIC designs have been fully characterized following the described procedure. In addition, and in order to test the advantages of the polymorphic design, six different inverse CORDIC designs (with stages ranging from 4 to 9) have been characterized. The results are presented and discussed in the next section.

V. RESULTS
In Table 3 the area occupied, the error detection rate, defined as the number of errors that are detected by our proposal respect to all the error injections, and the area overhead of the different algorithms, are shown. It is very important to highlight that any divergence from the golden model is considered an error, regardless of the error affecting the most significant bit or the less significant bit, or its impact in the final application. So, with the applied error detection rate we are considering the worst-case scenario. It can be seen in this table that the best area/detection rate trade-off from the two techniques presented is obtained with the trigonometric protection one, with an area overhead of 49% with respect to the parallel CORDIC architecture of 10 stages and a detection rate of nearly 88%. A 100% error detection rate is not reached because the output of the protection circuit is limited by the VOLUME 8, 2020 precision of the CORDIC and is not a constant but rather a small oscillation. In other words, since the technique does not do a straight comparison but it compares within a range, it may happen that an error with a small magnitude (within the threshold) is not detected and accepted as fine. Nevertheless, if this happens, the error magnitude would be limited to the aforementioned threshold.
Regarding the inverse CORDIC polymorphic protection, there is a direct relation between the detection rate and the number of stages used in the secondary structure. For a increasing number of stages the detection rate also increases. However, as it can be seen on Table 2, for n = 9 the detection rate is actually worse than for n = 7. This is because for a 10 stage CORDIC the final angle is so small that the extra stage not only does not improve the detection rate but it rather worsens it. The latter is because the cross-section is increased, and so is the number of errors that the circuit suffers. As can be seen in Fig.6, the z 0 input in the protection mode has the same precision as the first stage of the CORDIC under protection and this precision should be equivalent to a 10th stage. This loss of precision is not enough to reverse the process and makes that with more than 7 stages the absolute number of detected events does not increase and the area in which an error can produce a fault grows, so the final detection rate is worse. Note that with each step data width grows and this affects to the total area, speed and power consumption, oscillating in these implementations between 517 and 959 LUTs (Table 2), reducing frequency from 183MHz to 100MHz and with a difference in power consumption of at most 5mW (Table 3). After analyzing the different error patterns in both protection techniques, it can be claimed that the undetected errors (around 20%) affect the least significant bits of the output, causing a negligible impact in the the output generated. This error is within a range that can be tolerated by the following steps/blocks of the transceivers and metering instruments that use the CORDIC. When more than one error is generated, the spectrum of the output signal changes significantly and the percentage of detection increases. All the protection techniques presented in this paper occupy less area than the full DMR (which introduces an overhead higher than 105% and 100.2% for LUTs and FFs respectively) at the expense of reducing slightly the error detection rate while keeping the error within a margin (corresponding to the threshold). In the case of the full DMR the detection rate is below 99.7%. The 100% error detection rate is not reached because errors can fall in the input/output routing or other routing errors such as open/bridge faults due to shared multiplexers may interconnect the branches [28].
Regarding the timing, the trigonometric protection introduces a latency of 2 clock cycles, the inverse polymorphic CORDIC introduces 4 clock cycles in all the six different implementations, and the DMR introduces 1 clock cycle. A summary of speed and power consumption is included in Table 3. It is important to remark that other solutions for correction such as SEM IP are discarded as they require milliseconds to detect errors in the FPGA configuration, while our proposed solutions detect the errors in tens of nanoseconds, being a real-time solution and allowing faster reconfiguration [31].
Inspired by the work of Fujimori and Watanabe in [32] and [33], we used as an upper bound a CORDIC with 40-bit precision, which is used as an address generator for holographic memory systems in radiation environments such as the Fukushima Daiichi nuclear power plant. The conclusions that we obtained after implementing the unprotected and the protected versions of the architecture are similar, with a detection of more than 84% with our proposed method and an area overhead of less than 50% (1249 LUTs for the unprotected version and 1891 LUTs for the protected one).

VI. CONCLUSION
In this paper, two ad-hoc protection techniques have been presented as an alternative to the classic DMR scheme. An ABFT technique based on the trigonometric properties of the CORDIC and a structural-based technique. Regarding the latter, its detection rate depends highly on the number of stages used. It ranges from 72%, for 4 stages to 81.4% for 10 stages, but it provides more precision in the computation of the synthesized signals in absence of error. The area overhead ranges from 33.7/0.5 (% LUTS/FFs) to 85.4/2.6 (% LUTS/FFs). On the other hand, the trigonometric protection has a better trade-off detection rate against area overhead. It exhibits a detection rate of 88% with an overhead of 49/8 (LUTS/FFs %). The latency introduced by the inverse CORDIC protection is equal to 4 clock cycles whereas the latency introduced by the trigonometric protection is of 2 clock cycles, one to register the outputs of the multipliers and another one to register the output of the adder (see Fig. 4). The figures of merit, area and detection rate, of the trigonometric protection are better than those of the inverse CORDIC protection. However, the inverse CORDIC one can be used as a polymorphic structure with double functionality. In environments with low radiation it can be used as an extended resolution CORDIC and in environments with high radiation it can be split into a lower resolution CORDIC and an inverse CORDIC for error detection purposes.
It can be concluded that all the protection techniques proposed introduce an area overhead lower than that of the DMR and in the case of the inverse polymorphic CORDIC it even adds extra functionality to the CORDIC. Despite the fact that the error detection rate is lower than DMR, high error detection rates can still be obtained. As stated in the Introduction, applications that do not require a 100% protection can benefit from the overhead reduction provided by these techniques, especially if an adaptive approach is followed based on the FPGA reconfiguration capability. He worked as a Project Engineer with Zeus Creative Technologies, S.L., developing various computer vision projects, from 2013 to 2014. He was responsible for both hardware and software design and implementation. He is currently with the ARIES Research Center, Universidad Antonio de Nebrija. He is the author of several technical publications, both in journals and international conferences. His research interests include reconfigurable computing for space applications, computer vision, and robotics. He has worked as a Lecturer and Researcher at several universities and research centers such as the University of Liverpool, U.K., the University of California at Berkeley, USA, the Universidad Politécnica de Madrid, Spain, Ciemat, Spain, and CSIC, Spain. His research interest is focused on the implementation of digital signal processing and artificial intelligence algorithms in ASICs and FPGAs for space and scientific applications. Furthermore, the evaluation of the implementation issues in digital-and mixed-signal systems and the use of rapid prototyping techniques are also the fields that he is interested in pursuing. He has worked as a Lecturer and a Researcher at several universities such as the Universidad Politécnica de Madrid, the IT Innovation Centre, University of Southampton, Southampton, U.K., and the Universidad Antonio de Nebrija, Madrid, where he is currently a part of the ARIES Research Center. He previously worked in numerous national and multinational companies as a project manager and senior consultant for IT projects. His current research interests include fault-tolerance and reliability, the performance evaluation of communication networks, and knowledge representation and reasoning in distributed systems. He has been the Director of the Electronic Design and Space Technology Research Group, Universidad Antonio de Nebrija, Madrid, since 2004, where he has also recently founded the ARIES Research Center (www.nebrija.es/aries), devoted to the aerospace research and innovation in electronic systems. His current activities are oriented to the space industry, with several projects on the protection of digital circuits against the effects of radiation, including microprocessors, memories, and auxiliary systems. He also collaborates with institutions such as the European Space Agency, Stanford University, University College Dublin, or the Harbin Institute of Technology, among others. He is the author of numerous technical publications in journals and international conferences. His areas of interest include computer architecture, digital design, fault-tolerance, reliability, small satellites, and space applications.