A Low Power Pre-Setting Based Sub-Radix-2 Approximation for Multi-bit/cycle SAR ADCs

A pre-setting based sub-radix-2 approximation technique for multi-bit/cycle successive-approximation-register (SAR) analog to digital converters (ADCs) is proposed in this paper. The proposed approximation technique enhances the conversion speed and relieves the power hungry reference voltage buffer. The sub-radix-2 approximation only adjusts the weights of original binary DAC array without introducing additional unit capacitors and leading to reduced silicon area and power consumption. An adder based backend encoding circuit is proposed, with negligible power and silicon area overhead. Furthermore, the non-ideal DNL/INL, which are caused by incomplete DAC settling, are characterized and analysed in this paper. The peak DNL/INL values are symmetrically located at 1/4 and 3/4 of full scale. With the presence of sub-radix-2 approximation, the peak INL/DNL could be significantly reduced. The simulation results show the better performance of sub-radix-2 approximation than binary approximation. Designed in CMOS 40nm technology, it could keep a higher (>9.5-bit) effective number of bits (ENOB) with short settling time of DAC buffer, and boost the sampling rate equivalently.


I. INTRODUCTION
The development of high-speed communication and data acquisition requires the ADCs to obtain higher resolution and higher speed while keeping low power consumption. The trend of 802.11 standards is towards higher bandwidth (80∼160MHz for 802.11ac) and higher SNR requirement. It has been proven that successive approximation register (SAR) ADCs have better power efficiency for certain ADC resolutions [1]- [6]. However, the state-of-the-art single channel 10-bit SAR ADC [6] is approaching the speed limitation, which operates at 240MS/s with speed-enhanced redundant conversion in 28nm CMOS. To achieve higher sampling rate in SAR ADCs, 2-bit/cycle structure are widely used [8]- [10]. For the conventional binary approximation 2b/cycle ADCs [8], the conversion rate is limited by accuracy, without error tolerant scheme. A non-binary 2b/cycle solution is reported in [9], resulting in 1GS/s 7-bit singlechannel ADC without interleaving. However, an extra redundant range of 10 LSBs was added into the entire DAC.
The associate editor coordinating the review of this manuscript and approving it for publication was Jenny Mahoney.
A similar redundancy technique could be found in a 1bit/cycle SAR ADC in [2]. Another redundancy technique for 2b/cycle SAR ADC with time domain quantization was presented in [14].
This paper proposes a sub-radix-2 approximation technique for 2b/cycle SAR ADCs, which needs no extra redundant unit capacitors. The DAC size is maintained as same as the binary approximation scheme, only the weights of each branch are changed with redundancy embedded. The non-binary digital outputs are converted to binary code by adders based low power encoding circuit. The remainder of the paper is divided into four sections. Section II briefly introduces the first-order model of incomplete settling of 2b/cycle SAR ADC. In Section III, the sub-radix-2 approximation of 2b/cycle SAR ADC is described. The simulation results are given in Section IV. Finally the conclusion is drawn in Section V.

II. MODELLING OF INCOMPLETE DAC SETTLING
For conventional binary-weighted SAR ADCs, the DAC settling of each cycle must satisfy the accuracy requirement. Otherwise, the conversion error occurs. For a 10-bit 2b/cycle SAR ADC, shown in Fig. 1. The DAC settling of i-th branch should meet the condition.
By adopting sub-radix-2 searching algorithm, the settling accuracy requirement could be reduced substantially. Suppose that the settling redundant ratio of i-th comparison is r i , then if no settling error occurs [11]. Then, the t set needs to satisfy where r i is the redundant ratio of i-th conversion. In addition, since the settling accuracy requirement is much reduced. Therefore, the bandwidth of the reference voltage buffer could be smaller, resulting in lower power consumption.

III. SUB-RADIX-2 APPROXIMATION FOR A 2B/CYCLE SAR ADC
The block diagram of the proposed 2b/cycle SAR ADC with sub-radix-2 DAC arrays is shown in Fig. 2. Only two capacitive DACs (CDACs) array are adopted due to first-stage interpolated pre-amplifier A2. Further, there is a secondstage interpolated comparator (C2 or C4) between every two adjacent pre-amplifiers (A1, A2 or A2, A3) to increase the resolution by 2 bits. During the first five conversion cycles, the dynamic comparators Co2 and Co4 are powered down, and only activated in the last cycle. Similarly, the comparators Co1, Co3, Co5 are powered down at last cycle. Therefore, only 3 dynamic comparators are activated  in each cycle without extra power wasted. The two-stage interpolation reduces the resolution of the CDACs by 2 bits. Compared to binary approximation [12], one more conversion cycle is required. In Fig. 2, the branch ratio of the DAC array is C 1 :C 1r :C 2 :C 2r :C 3 :C 3r :C 4 :C 4r :C 5 = 64: 56: 20: 18: 6: 5: 2: 1: 1. Basically, C i (i = 1, 2, 3, 4, 5) is used for threshold pre-setting, while C ir (i = 1, 2, 3, 4) contributes the redundant values. To describe the operation of the proposed sub-radix-2 approximation scheme, one example with an input of 550.5 LSBs is illustrated in Fig. 3. The threshold values indicated in blue are generated by CDACs, while the threshold values in red at the last cycle are generated by interpolation of dynamic comparators Co2 and Co4 (Fig. 2). From Fig. 3, it also can be seen that the redundant value from MSB to LSB conversion are 64 LSBs, 16 LSBs, 8 LSBs, 8 LSBs, 0 LSBs and 0 LSBs, respectively. The redundant values are generated by the switching of the DAC array, which will be illustrated in Fig. 4. Overall, one conversion includes six cycles with 2 bits solved in each cycle. Therefore, a set of 12-bit sub-radix-2 code is produced in one data conversion. The illustration of DAC settling and equivalent weights of sub-radix-2 DAC are shown in Table 1. It shows the connection of DAC capacitors with different output codes. The corresponding weights could be calculated with the CDAC shown in Fig. 2 where S i and S i+1 are the scale of i-th and i +   defined as Therefore, the redundant ratios of the first four non-binary cycles are 25%, 20%, 33.3%, 50%, respectively. To elaborate the sub-radix-2 switching operation further, Fig. 4 shows the single-ended switching procedure of one conversion. The sampling phase is illustrated in Fig. 4(a). All the bottom plates of CDACs are connected to input during the sampling. Before the MSB comparison ( Fig. 4(b)), the threshold of CDAC1 is set to 3/4V FS (by connecting one C 1 to 0 and others reset to 1), while the threshold of CDAC2 is set to 1/4V FS (by connecting one C 1 to 1 and others reset to 0). Briefly, the CDAC1 searches from the top 1024 LSB 10−bit , while the CDAC2 searches from the bottom 0 LSB 10−bit . Both CDACs approximate the targeted input (550.5 LSB 10−bit ). According to the MSB comparison results ''011'' (D 11 D 10 = 10), one C 1 and C 1r are connected to 1 and the other C 1r connected to 0 as described in Table 1. To create a redundant range, the C 1 in CDAC1 is switched back to 1 and one C 1r is switched to 0. Also in CDAC2, one C 1r is connected to 1. Simultaneously, the C 2 is set to 0 in CDAC1 (1 in CDAC2) to create thresholds for MSB-1 comparison (Fig. 4(c)). The comparisons are repeated in similar ways (Fig. 4(d), Fig. 4(e), Fig. 4(f)) until LSB comparison. Fig. 4(g) shows the operation of LSB comparison, where the last two bits are generated by interpolated comparators. In Fig. 4(g), voltage difference settled between CDAC1 and CDAC2 is one LSB 8−bit (1/256V FS ). At the output of pre-amplifiers, the thresholds of interpolated dynamic comparator Co2 and Co4 are 3/1024V FS and 1/1024V FS within one LSB 8−bit respectively. All of the offsets of pre-amplifiers and comparators are calibrated separately in the background to prevent the deterioration of system linearity [12].

IV. LOW-COST ENCODING CIRCUIT FOR SUB-RADIX-2 APPROXIMATION
To map the redundant output codes to binary codes, a low-cost sub-radix-2 encoding circuit for multi-bit/cycle conversion is proposed. The corresponding encoding mapping is listed in Table 2, where each non-binary weight is represented as a sum of binary weights. Different from [9], [10], no offset is required for the redundant digital output. Since most of the redundant values are set as a power of 2, it is straightforward to realize encoder by only adders instead of complex arithmetical units [13]. Fig. 5 shows the schematic of encoding circuit, which converts the redundant 12 bits raw data (D 12 to D 0 ) to 10 bits binary code (B 9 to B 0 ). The bits C i ' and C i '' are the carry bits of bit-i (i = 0∼9), and they are connected by labels in Fig. 5. The encoder is built with only 13 full adders (FA), 12 half adders (HF) and 1 OR gate. Overall, the proposed non-binary searching technique for 2b/cycle SAR ADC consumes less power and has low silicon area overhead. At a sampling rate of 400MS/s, the simulated power consumption is less than 0.15mW. And the propagation delay is less than 1 ns. Moreover, the redundant weight in VOLUME 8, 2020  each cycle could be flexibly configured according to different design considerations.

A. BEHAVIOURAL MODEL SIMULATIONS
To demonstrate the proposed sub-radix-2 approximation algorithm, the model of the approximation is built with DAC settling behaviour included. The incomplete DAC settling of binary 2b/cycle SAR ADC is also presented for comparison. By setting time t set = 7τ and t set = 3τ respectively, the DNL/INL of traditional 2b/cycle SAR ADC are plotted in Fig. 6. The settling requirement of 10-bit  resolution is met by setting t set as 7τ , therefore, the DNL/INL show acceptable peak values of 0.24/0.24 LSBs. However, the DNL/INL degrade to 12.7/12.7 LSBs with t set reduced to be 3τ . Fig. 7 shows the DNL/INL of proposed sub-radix-2 2b/cycle SAR ADC. It can be seen that the peak DNL maintains a low value of 0.26/0.26 LSBs with t set = 3τ , which proves the settling error tolerance capability of subradix-2 approximation. In addition, with different number  of τ , the peak DNL and INL are shown in Fig. 8. Within the tolerable error range of sub-radix-2 approximation algorithm, the peak DNL/INL only has a slightly drop. Regarding the effect of incomplete settling on dynamic performances, the SFDR and SNDR of traditional 2b/cycle SAR ADC are only 64.9 dB and 49.9 dB with t set = 3τ , respectively, which are shown Fig. 9 (a). On the contrary, Fig. 9 (b) shows that for sub-radix-2 2b/cycle SAR ADC the SFDR and SNDR are 85.1 dB and 61.6 dB, respectively, which achieves an ENOB of 9.94-bit. The SFDR and SNDR versus different number of time constant are depicted in Fig. 10. The   sub-radix-2 approximation could keep the ENOB above 9.59-bit with settling time t set > 2 τ . However, for binary approximation the t set needs to be larger than 5τ to keep the ENOB above 9.9-bit.

B. TRANSISTOR LEVEL LAYOUT SIMULATIONS
A fabricated design example of binary 2b/cycle SAR ADC was reported in [12], where the interpolated pre-amplifiers and comparators have been verified except the proposed VOLUME 8, 2020   sub-radix-2 approximation algorithm in this work. To evaluate the conversion rate improvement, the post-layout simulation based comparison between traditional and the subradix-2 2b/cycle SAR ADCs is depicted. The layout of the proposed SAR ADC is shown in Fig. 11, which is revised from [12]. The Cal_cap is the capacitors for offset calibration. Comp is the pre-amplifiers and dynamic comparators. Logic is the SAR control logic. The layout occupies 210 µm × 110 µm (0.023 µm 2 ). The power consumption of the ADC core is 6 mW (pre-amplifier 2.5 mW, digital logic 3.15 mW, DAC array 0.35 mW). The ENOB versus sampling frequency is shown in Fig. 12. It can be seen that the ENOB of subradix-2 approximation SAR ADC keeps larger than 9.5-bit till 400MS/s. At the case of SS corner and 125 degree, the ENOB is around 9-bit at 400MS/s. However, the ENOB of traditional binary approximation SAR ADC starts to fall at 300MS/s. To verify the linearity, the SFDR versus input frequency at different corners and temperatures at 400MS/s is shown in Fig. 13. In addition, the ENOB versus 10 Monte-Carlo (MC) simulations, which includes local mismatch of transistors, resistors and capacitors, are shown in Fig. 14. In the above MC simulations, TRAN noise option is turned on. The ENOB versus supply voltage VDD variation is shown in Fig. 15. The performance summary and comparison between the state-of-the-art 2b/cycle SAR ADCs and the proposed sub-radix-2 SAR ADC is listed in Table 3.

VI. CONCLUSION
A sub-radix-2 approximation algorithm for 2b/cycle SAR ADC is proposed in this paper. The sub-radix-2 approximation only introduces one more DAC branch and adders based encoding circuit. The additional power consumption and silicon area of the hardware overhead are negligible. The non-ideal DNL and INL curves are characterized with the presence of incomplete DAC settling. It is proved that the sub-radix-2 could tolerate the incomplete DAC settling error and improve the DNL and INL significantly. Equivalently, the sub-radix-2 approximation could boost the conversion speed by 33% for a 300MS/s 10-bit 2b/cycle SAR ADC. , and developed the low power, low noise oscillators, synthesizers, and sensors interfaces using piezoelectric MEMS resonators. Since Jan 2017, he has been an Associate Professor with Southeast University, China. He has authored or coauthored over 40 international journal and conference papers, including three patents filed and one book chapter. His research interests include future wireless bio-electrical interfaces, body-area-networks, automotive and home monitoring, and implantable devices demand wireless technology well beyond the state-of-the-art. He serves as a guest editors for several international journals. He has been organizing several conferences as a session chair.
CHUANSHI YANG received the B.Sc. degree from Shandong University, China, in 2012, and the M.Eng. degree from Southeast University, China, in 2015. He is currently pursuing the Ph.D. degree with Nanyang Technological University, Singapore.
His current research interests include the high-resolution low-power ADC and interface circuits for ultrasound sensors. Manager. Since then, he has leaded in developing various wireless systems and CMOS integrated circuits, such as Bluetooth, WLAN, WCDMA, UWB, RF SAW/MEMS Radar, and wireless capsule imager. Most of projects were collaborated with industries. Since July 2009, he has been with Nanyang Technological University as an Assistant Professor, working on various radar system development and hybrid circuit and device (GaN, SAW, and MEMS) designs. He has authored or coauthored over 220 international journal and conference papers, 22 patents filed, and five book chapters. He has conducted and completed projects with total funding over $18 Million. He received the best graduate student thesis award from Xian Jiaotong University. He has been organizing several conferences as a TPC chair and a session chair. He serves as a guest editor and an associate editor. VOLUME 8, 2020