Improved Multi-Core Real-Time Task Scheduling of Reconfigurable Systems With Energy Constraints

This paper deals with the scheduling of real-time periodic tasks executed on heterogeneous multicore platforms. Each processor is composed of a set of multi-speed cores with limited energy resources. A reconfigurable system is sensible to unpredictable reconfiguration events from related environment, such as the activation, removal or update of tasks. The problem is to handle feasible reconfiguration scenarios under energy constraints. Since any task can finish execution before achieving its worst-case execution time (WCET), the idea is to distribute this execution on different processor cores for meeting related deadlines and reducing energy consumption. The methodology consists in using lower processor speeds first to consume less energy. If the system is still non-feasible after reconfiguration, then we adjust the task periods as a flexible solution or migrate some of them to the least loaded processors. Accordingly, an integer linear program (ILP) is formulated to encode the execution model that assigns tasks to different cores with optimal energy consumption, thereby realizing energy-efficient computing/green computing. The potency and effectiveness of the proposed approach are rated through simulation studies. By measuring the energy consumption cost, our solution offers better than 11% of gain than recently published methods and improves by 85% the overall number of adjusted periods.

ABSTRACT This paper deals with the scheduling of real-time periodic tasks executed on heterogeneous multicore platforms. Each processor is composed of a set of multi-speed cores with limited energy resources. A reconfigurable system is sensible to unpredictable reconfiguration events from related environment, such as the activation, removal or update of tasks. The problem is to handle feasible reconfiguration scenarios under energy constraints. Since any task can finish execution before achieving its worst-case execution time (WCET), the idea is to distribute this execution on different processor cores for meeting related deadlines and reducing energy consumption. The methodology consists in using lower processor speeds first to consume less energy. If the system is still non-feasible after reconfiguration, then we adjust the task periods as a flexible solution or migrate some of them to the least loaded processors. Accordingly, an integer linear program (ILP) is formulated to encode the execution model that assigns tasks to different cores with optimal energy consumption, thereby realizing energy-efficient computing/green computing. The potency and effectiveness of the proposed approach are rated through simulation studies. By measuring the energy consumption cost, our solution offers better than 11% of gain than recently published methods and improves by 85% the overall number of adjusted periods. Real-time applications are conditioned by temporal requirements and need to be executed before their deadlines. In some systems under hard real-time constraints, disastrous consequences can occur if any timing requirement is violated [1]. Reconfigurable real-time systems have the ability to fully meet the simultaneous performance and flexibility demands [2]. A reconfiguration scenario is usually performed in response to user requirements and dynamic changes in their environment during execution such as unpredictable activation-deactivation-update of some tasks [1], [3], [4]. A scenario of reconfiguration can also be considered as an activation/deactivation of one or more devices when a multi-processor architecture is adopted. Applying a reconfiguration scenario can grow the energy consumption or lead to the violation of some task deadlines. During the last decade, real-time applications became hugely complex and needed more processing power to meet the requirements of such intensive processing applications [5]- [7].

INDEX TERMS
Dynamic voltage and frequency scaling (DVFS) is considered as the most adopted way to implement an efficacious low-power system [8]- [10]. Depending on the actual amount of work, this technology enables the processor to change its execution frequency of tasks with the aim of reducing power consumption cost. However, changing frequently a processor's operating frequency at run-time to execute each system's task can cause problems for hardware components, and subsequently some instability problems can arise [4], [11]. In recent years, multi-core technologies have become a fundamental design choice because of their low power consumption and cost-effectiveness [12]- [16]. This growth has moved the scaling trends from processor clock frequencies to the number of cores per processor.
A multi-core processor is made up of homogeneous processing units that can vary by their clock frequency [17]. Multi-core platforms continue to crawl and make a nice way for implementing complicated and real-time computation tasks.
Practically, most tasks can finish execution before reaching their worst case execution time (WCET). Hence we can improve the energy consumption by reducing execution speeds in some processor cores, thus fullfiling the goal of energy-efficient and green computing. The trick is based on multi-speed cores and using lower core speed first when executing tasks to consume less energy. If a system is nonfeasible, then we adjust the task period as a flexible solution or migrate some of them to the least loaded processors to handle the situation.
The considered system in this paper is composed of a set of networked devices under limited hardware resources [18]. A local processor is considered for each device to execute local tasks. Each processor is composed of a set of multi-speed cores allowing the execution of tasks in parallel. The treated tasks are independent, synchronous, nonpreemptive, periodic, and with implicit deadline [19].
Various approaches scheduling real-time tasks under multi-core architectures have been proposed in recents years [11], [20], [21]. However, ensuring an efficient planning while all tasks run into their deadlines remains a complicated issue. The authors in [12] propose an advanced task scheduler that divides multimedia and non-multimedia applications between small and big cores. The work [11] proposes a proactive thermal management design on a multi-core architecture to avoid suffering from high temperature of the system. The studies [22], [23] present two scheduling solutions to effectively reconfigure and assign the tasks to cores while decreasing the global makespan under adaptive multi-core architectures. A hardware implementation of a dynamic communication-aware scheduler is proposed in [24]. This solution exploits the reconfigurable dominant sequence clustering algorithm to dynamically assign tasks to reconfigurable cores. A power-aware scheduling solution based on a multi-objective evolutionary algorithm is proposed in [6] to optimize a set of criteria such as temperature, energy cost and effectiveness. The authors in [25] present the formalization of an allocation problem with the aim to control the system behavior.
Each of the related works in Table 1 has advantages and limitations. Some related studies do not target reconfigurable systems ( [7], [10], [38]) and cannot be generalized as the number of tasks increases. Some ( [1], [10], [38]) do not deal with multicore architectures. Such architectures represent an advantage in terms of sharing and synchronizing OS tasks, which directly influences the amount of energy consumed by the system. Some ( [28], [38]) are just based on DVFS tech- nologies which can affect the stability of the processors [8]. This is due to the problem of switching processors between different power consumption modes and scaling the speed of the processor according to the workload in a system. Some studies ( [1], [28]) integrate multi-agent architectures requiring fairly good communications among agents, which can increase computational cost. Thus, some [29]- [32] propose models which are linked to a set of precise criteria to an explicit application framework, well-defined input parameters and predetermined environmental constraints which make its improvement difficult.
The developed solution presents an optimization mechanism that affects all the levels, such as partitioning tasks on different cores, and adjusting periods and migrating tasks from one processor to another. This makes the system more flexible and able to handle run-time reconfigurations. Moreover, the produced solutions are optimal. It allows engineers to determine, after each reconfiguration, the assignment of the tasks to different cores by acting on multi-speed cores and specifies their scenarios of migration among processors. Migrating tasks from an over-loaded processor to a less loaded one not only allows engineers to find a schedule that guarantees the feasibility of the system, but also balances the workload among all processors.
An assignment strategy consists in finding an optimal hard real-time workload split among the existing cores. Finding an optimal solution for this problem is NP-hard [20]. We adopt a mathematical formulation based on integer linear program (ILP) to define the execution model that deals with assignment. Since the objective function is rational, it is not possible to solve the initial developed program directly and efficiently by any solver. The non-linearity of the developed program stems from the fact that the execution time of tasks is proportional to the weight of cores whereas energy consumption is inversely proportional to the weight of cores.
We propose an approach that includes two stages to solve it. First we transform it into a quadratic program [26]. Then, we transform the quadratic program into a linear one.
The proposed approach is compared with a set of methods reported in [1], [7], [10], [27], [28], and [38] (Table 1). Some of them are not considered to operate in reconfigurable systems. In addition, a few of them do not take into account an energy consumption constraint, which mostly requires more computation time to produce a correct solution. Multicore technology is also absent in some studies, which can have significant influence on job execution performance.
The solution gives the advantage of reducing energy consumption in each processor and then in the whole system. It offers more than 8% of gain compared with the approach in [27] and 15% of gain compared with the work in [1] when 20% of tasks finish execution in WCETs. The proposed approach also decreases by 80% the number of adjusted task periods compared with the work in [27] and by 93% compared with the approach in [1].
The contributions of this paper can be summarized as follows: We propose a scheduling scheme based on multi-speed cores, which consists of three cascading solutions depending on configuration scenarios: 1) We assign each task to different cores with different speeds while wishing to finish them as soon as possible with low-cost cores to save energy and cost, 2) If the first solution is not feasible, we adjust the periods of tasks with a new application of this solution, and 3) We migrate tasks to other lightly-loaded devices. The rest of this paper is arranged as follows: We present in Section II a formalization of the hardware and software architecture of a system. In Section III, a solution for improving energy consumption in distributed multi-core reconfigurable architectures through integer programming is presented in detail. Finally, we display and discuss the experimental results and compare the proposed contribution with related ones.

II. FORMALIZATION AND PRELIMINARIES
In this section, we formalize a system, hardware architecture, real-time tasks and energy models targeted in this work by using ILP formalization. The produced solution is a set of variables that indicate the task partitioning on different cores and processors. Preliminaries used in a linearization step are also presented. Used notations and their meanings are summarized in the nomenclature. We assume that a system's tasks are independent.

A. HARDWARE ARCHITECTURE
We consider a distributed hardware platform with m networked devices. Each device incorporates a multi-core processor composed of a set of multi-speed processing units called cores [12]. We denote by Proc p (p = 1 . . . m) the processor embedded in Device p . We denote by Core kp the k-th core of where f kp is the frequency of Core kp in Proc p . We attribute to each core a relative weight (W kp ) according to its frequency. The allocation is defined as follows:

B. REAL-TIME TASKS
We denote by T = {T 1 , T 2 , . . . , T n } the set of n periodic tasks to be executed upon a multi-core platform. T i is defined by the following parameters: i) Absolute deadline d i , i.e. T i must finish before d i , ii) Computation time ζ ip at the normalized frequency on Proc p , iii) Period π i , and iv) Upper bound of each task's period π M i . A reconfigurable real-time system is composed of a set of n tasks and m devices. It is feasible if all the tasks meet their corresponding deadlines and no battery exceeds its capacity. Then, we assume a reconfiguration scenario to add a set of l new tasks to the current feasible system. Some problems can arise in the extended system (n + l), such as the violation of some task deadlines. Thus, the batteries may not support the required energy consumption that exceeds their capacities; and, subsequently, become weak. This can also disrupt the feasibility in the related processor's cores and consequently affects the feasibility of the entire system.

C. ENERGY MODEL
The total energy consumed is the sum of the dynamic and static components. Static energy is approximately constant while dynamic power consumption depends on the clock frequency. For this reason, we have targeted the modeling and calculation of dynamic energy in this paper.
The actual execution time of a task is prolonged when voltage is decreased to save the energy. The reason is that the frequency of a processor is approximately linearly proportional to supply voltage. Reducing voltage cuts down energy dissipation, but decreases the operating frequency accordingly. Hence, task execution time is inversely proportional to voltage. In order to provide the required system performance, the supply voltage should be scaled as low as possible to minimize energy consumption, while guaranteeing the timely completion of tasks.
LetV kp andV kp be respectively the normalized frequency and voltage of Core kp [28]. We suppose that task T i is executed at frequency F ikp and voltage V ikp in Core kp . When Core kp is running at frequency F kp and voltage V kp , the power consumption is given by P kp = RV kp 2 F kp , where R is a constant that depends on a hardware circuit [33]. Power P ikp consumed by task T i in Core kp of Proc p is given by Each device is powered by an assigned battery and each one has its predefined capacity denoted by B M p . The energy consumption in Device p should not exceed this capacity. Thus, the energy consumption in Device p is defined as follows:

D. THEORETICAL FOUNDATION
Many approaches have been proposed to solve rational optimization problems. The work [34] proposes a polynomial time algorithm to solve a class of optimization problems using rational objective functions as long as there is a performant algorithm to solve the problem with a linear objective function. Unfortunately, this does not cover our initially developed program ( Fig. 1) since it is a mixed integer program with a quadratic rational objective. The work [35] proposes an approximation approach to optimize special cases of linear rational functions. A general scheme is proposed in [36] to approximate a linear rational function in a binary polyhedron. Since the problem is NP-complete, we develop an approximate solution based on linearization and convexification techniques. In this work, the extended model cannot be directly solved by any solver since it contains a rational constraint. The non-linearity of the model stems from the fact that the execution time of tasks is inversely proportional to the deadline adjustment. We propose a two-stage based approach (Fig. 1). First, we transform our model into a quadratic equivalent program, and then a linear one.

III. NEW SOLUTION FOR IMPROVING ENERGY CONSUMPTION
In this section, we detail the developed contribution that deals with three cascading solutions depending on reconfiguration scenarios. It consists in partitioning tasks on different cores, VOLUME 8, 2020 adjusting tasks periods or migrating some of them from one processor to another. A mathematical formulation based on ILP is set up to define an execution model.

A. MOTIVATION
The problem can be treated locally or globally depending on reconfiguration scenarios and feasibility tests (Fig. 2). The local treatment assigns each task to different cores while wishing to use as much as possible low-cost cores in terms of energy consumption. We start by executing the first slot of a task by the core with the lowest frequency while respecting deadlines. If ever the available core speeds are not able to guarantee the system feasibility, we adjust the periods of tasks as a flexible solution. Then we repeat the computing of assignment to different cores. This solution keeps a perfect system operation provided that the maximum values of periods are not overtaken. The solution must not exceed the capacities of batteries in devices.
When a local processor cannot support the reconfiguration with the period adjustment, we perform task migration and re-calculate the same assignment until reaching the feasibility of the system. This step consists in selecting the task set to be moved on the one hand and specifying the destination (the least loaded processors that are able to host tasks) on the other hand while keeping an eye on the system feasibility.

B. PARTITIONING OF TASKS ON MULTI-CORE ARCHITECTURES
Reaching an efficient schedule that keeps the system feasible after a considered reconfiguration scenario requires significant task planning and relevant assignment of segments to the available cores.

1) EXECUTION MODEL
The main objective of this step is to define an execution model that uses low-speed cores for reducing the energy consumption. The execution model deals with the assignment of tasks to different cores by acting on multi-speed cores.
In multi-core architectures, an application's tasks can potentially run in parallel. Each task is divided into a set of segments, each of which can be executed on a processor's core. Task segments are considered as independent of each other. Thus, they can run in parallel and out-of-order. This parallel execution exploits the advantage of the multi-speed technology with multiple processing cores to decrease the completion time of a task and the related energy consumption especially when a large number of tasks are able to finish their execution before their WCETs.
Before the assignment procedure, the execution time Cn ip of task T i is split into h segments for execution. Let T s i be the s th segment of task T i and C sikp (s = 1 . . . h, i = 1 . . . n, k = 1 . . . c, p = 1 . . . m.) be the s th segment of task T i assigned to Core kp . The number of all segments is given by Cn ip = C 1ikp + C 2ikp + · · · + C sikp . Thus, C sikp of task T i allocated to Core kp can be determined as Example: We consider a set of five real-time tasks to be executed upon a multi-core platform as depicted in Table 2. It consists of a set of four multi-core processors. Each processor is composed of four cores each of which has its own speed. T i is split into four segments The considered core speeds for the case study are 1.8Ghz, 2.4Ghz, 2.8Ghz, and 3.2Ghz. To explain a task splitting scheme, we introduce a task set example. To calculate the weights attributed to processor cores, we use the following formula: Then we have W 1 = 0.2, W 2 = 0.23, W 3 = 0.27, and W 4 = 0.3. The split of WCET of task T i is given by The segments of C i attributed to each core are described as follows:  where X sikp is a binary variable that characterizes the allocation constraint between segments and cores.
X sikp = 1 if segment T s i is assigned to Core kp of Proc p 0 otherwise (7) By considering task segmentation, the energy consumed by T s i on Core kp is given as E sikp = P sikp C sikp . The energy consumption in Device p becomes: To have effective planning, each task's segment must be assigned to a single core during its execution. Thus, we have the following constraint: To avoid multiple-segment execution in a time, T s j cannot start before T s i completes, which means that the difference between the starting times of T s i and T s j must necessarily be greater than the execution time of T s i or in reverse if T s j starts before T s i . We must ensure that t sjkp − t sikp − C sikp ≥ 0 or t sikp − t sjkp − C sjkp ≥ 0 for each segment pair T s i and T s j , and a binary variable α ij is used to guarantee both inequalities at the same time, i.e., α ij = 1 ensures that T s i is executed before T s j . Therefore, if T s i gets started before T s j in Core kp , T s j cannot begin execution if T s i is running. The previously added constraints avoid multiple active segments on any core and at any time. The related constraints are: To assure the fulfillment of (12) and (13), the starting time of each task should be less than or equal to a big constant M .
In the case where task T s i is executed before T s j , (14) keeps (12) valid. In fact, in this case, we have α ij = 1 and subsequently t sjkp − t sikp ≤ 0. Therefore ζ jp W kp X sjkp − M must also be negative and less than t sjkp − t sikp . Hence, t sjkp − t and t sikp − t must necessarily be less than M .
Among the assignment steps, we aim to execute as much as possible the first slot of a task by the core with the lowest frequency to consume less energy. According to this, we look for a feasible solution to ensure that the cores with lowest frequencies are more lightly-loaded than those with the highest frequencies. To reach this objective, the load U kp of Core kp should increase as their frequency f kp decreases since f kp < f (k+1)p ∀ k ∈ {1, 2, . . . , c}. Thus, achieving this goal is tantamount to performing: The previous maximization function can be transformed to a minimization function since maximizing f (x) equates minimizing −f (x). At this level the objective becomes multiple, i.e., minimizing the consumed energy and assigning the segments to the processor that has the lowest speed.
To ensure a compromise between the weight of an assignment strategy and the energy in the objective function, we add two weight factors σ and λ such that the objective becomes Since in a mathematical model, multiplying the objective function by a constant has no effect on the solution, we multiply (15) by 1 σ to obtain: Let γ = λ σ . This factor is used in order to favor an objective function against the other as required. To give more importance to energy consumption in the objective function, γ must have a small value. Reversely, γ must be big. The correspondent objective function becomes: Timing Constraints: The timing constraints present a decisive factor when the reliability of a system is constrained by time. Each segment should begin execution next to its release date, i.e., t sikp ≥ r sikp (18) and each task should end execution without violating its related deadline, i.e., By modeling the previous constraints, we establish the main mathematical program called PI. It is linear since all constraints are so.

2) EXTENDED EXECUTION MODEL WITH DEADLINE ADJUSTMENT
For more flexibility in a system, we introduce a mechanism of period adjustment. It keeps the system functional even if the available cores speeds are not able to guarantee the system feasibility. We denote by β i the fractional increase of the period of task T i . To guarantee the stretching of its deadline, we add the constraint: By including the period amendment constraint, we ensure that all tasks are completed before their deadlines, i.e., To monitor the period modification at run-time, we append parameter π M i that represents the upper bounds of period π i . We have: We also append constant θ to characterize a trade-off weight between deepening coefficient β i and energy. The objective function is given as: By bringing together all these constraints, we obtain an extended model called PE.

3) EXECUTION MODEL LINEARIZATION
Since PE is non-linear, we propose an approach that includes two stages to solve it. First, we transform it into a quadratic equivalent program called PQ. Then, we transform PQ into a linear one.
Stage 1: We proceed in two steps to transform PE into a convex equivalent program [36]. (i) First, we replace 1 β i with a positive continuous variable z i in PI and add the following constraints: The related constraint is given as: We obtain the equivalent quadratic program.
However PQ is also difficult to solve since its constraint (24) is non-linear as it contains the product of two variables β i and z i . So is (26) because of X sikp z i .
Stage 2: In this stage, we linearize (24) and (26) by using a linearization technique. Typically, the linearization [26] is based on the principle that each product is replaced by a new variable and then a set of new linear constraints is added to guarantee the equality between a new variable and the product. In PQ, we replace β i z i by y i . Let U Z be an upper bound on z i . The following inequalities are added to guarantee that β i z i = y i : In a similar way, we linearize (24). We replace X sikp z i by x i and we add the corresponding constraints: Program PX can be solved by mixed integer program solvers such as CPLEX. 1

C. MIGRATION OF RECONFIGURABLE TASKS
PI and PE models are designed to be applied if a reconfiguration has occurred in a particular device. They try to find the right segment partitioning on different cores. In the case where the assignment of tasks to different cores is inapplicable, and the modification of the task periods on the corresponding processor cannot guarantee the system's feasibility, we resume the allocation step while giving tasks the opportunity of migrating among processors in order to meet the system's feasibility without having to touch the whole tasks in the system.
We need specify a way to migrate tasks from one processor to another. Migrating tasks consists in finding a new combination between tasks and processors to ensure the system's reliability. This step is not interested in assigning segments to cores. Therefore, we replace variable X sikp with Y ip to characterize the allocation between tasks and processors.
Y ip = 1 if task T i is assigned to Proc p 0 otherwise (27) To ensure the correct migration of a task, we should guarantee that a task is not allocated to two different processors, i.e., We update the starting and release dates of a task in a processor to be denoted by t ip and r ip , respectively. Minimizing the number of tasks for migration is adopted in this step in order to reduce the related cost. After updating the previous constraints, we obtain the program called PM:

IV. EXPERIMENTATION
In this paper, we use the AMPL language and ILOG CPLEX 11.0 solver to model and solve mathematical programs. They provide an analytical decision tool that allows the rapid deployment of optimization models by using mathematical and constraint programming [37].

A. CASE STUDY
We consider a real-time reconfigurable system. A local processor supporting the multi-core technology is considered for each device. Each processor has a set of multi-speed cores allowing the execution of implicit-periodic OS tasks. Each task is described by a period, worst acceptable period, deadline, release date, and completion time.

Scenario 1 (Related Processors Can Support a New Reconfiguration):
We consider an initial assignment of tasks to different processors (respectively cores) presented in Table 5. The task set in Table 4 is ready to be executed in a parallel way on the four cores of each processor. The schedulability  constraint is satisfied at this stage. The utilization is less than or equal to the number of cores in each processor (U ≤ 4).
We assume a run-time reconfiguration scenario in Device p that adds two new tasks T 11 and T 12 to the queue for execution on CPU 2 ( Table 6).  Table 7 shows the allocation of the different segments of tasks to the cores of CPU 2 after applying the execution model PI. Fig. 3 presents the related scheduling plan. We note that U 21 = 0.998 ≤ 1, U 22 = 0.964 ≤ 1, U 23 = 0.997 ≤ 1, and U 24 = 0.32 ≤ 1. Hence the system is feasible. The consumed energy in CPU 2 is computed 848.73 Joules. We assume now a new reconfiguration scenario that occurs in CPU 2 and requests adding two new tasks T 13 and T 14 to be executed as depicted in Table 8. After  PI, we note that U 21 = 1.285 > 1, U 22 = 1.118 > 1, U 23 = 1.261 > 1, and U 24 = 0.773 < 1. Then the system is infeasible since CPU 2 cannot support the new reconfiguration where some tasks may violate their deadlines (Fig. 4). The consumed energy in CPU 2 is equal to 1085.76 Joules.

Scenario 2 (Necessity to Adjust Periods):
The CPU 2 load exceeds its capacity. At this level, a local solution consists in adjusting the periods of few tasks to meet the system's feasibility without migrating to other processors. By applying PE, we get the following result with the new adjusted periods (Table 9 and Fig. 5) and the allocation table (Table 10) which fixes for each core the related set of tasks to execute.    Table 11 shows the parameters of task T 15 to be added to CPU 2 for execution as a new run-time reconfiguration request. After applying PE, we observe that U 21 = 1.496 > 1, U 22 = 1.187 > 1, U 23 = 1.336 > 1, and U 24 = 1.023 > 1. Thus, the timing constraints of tasks may be violated under this condition and the processor is overloaded. Changing the periods can be a flexible and efficient solution. Yet the adjustment is always limited by a maximum acceptable value. If the modification of the periods of some tasks could not give the desired result, task migration must be conducted to overcome the problem by applying PM (Table 12).

B. PERFORMANCE EVALUATION
To evaluate the performance of the proposed approaches in this paper, we take a random test games by generating 80 instances of implicit-deadline real-time tasks that represent reconfiguration scenarios. We consider a multi-processor system with multi-speed core capability. The WCET of each task is randomly generated by using a uniform distribution [38]. Other task parameters such as release time and deadline are also randomly generated. The experiments are performed by using Intel Core TM i3-2670QM processors with 4 GB of RAM.
In order to compare the contribution of the proposed solution with the recent approaches in [1], [27] according to the cost of periods adjustment, we try to implement the same case study. Fig. 6 confirms the clear gain of this contribution (bars in red) compared with those reported in [27] (bars in green) and [1] (bars in blue). The cost of period amendment is considered as the sum of the gaps between the basic periods values and those after reconfiguration. We see that the cost of period modification produced by our solution is estimated respectively on the three cores to be 74, 35 and 46. For the same metric, the cost is estimated to 955,840 and 500 when applying the solution in [1] and to 196, 349 and 250 by the solution in [27]. Indeed, the proposed solution is based on a multi-objective mathematical model that allows one to determine the optimal value by minimizing the gap between old and new periods as much as possible to make the system functional after reconfiguration. The proposed approach also improves by 80% the overall number of adjusted task periods compared with the work in [27] and by 93% compared with the approach in [1].

FIGURE 6.
Comparison between the proposed solution and those in [27] and [1] according to the cost of deadline adjustment. Fig. 7 shows a comparison of the proposed approach with those reported in [1], [27], and [28] based on the energy cost.
The energy consumption ratio confirms the efficiency of using multi-core technology. This technology exploits parallelism in task execution, resulting in more significant power consumption performance with 70% of reduction over a non-multi-core system (Fig. 7). By applying the suggested strategy, the system can save 9% of power. It is obvious that in the case that the multi-core technology is not used, the energy consumption is practically very high because processors operate at their maximum frequency and require the maximum power. Figs. 8-12 describe the power consumption of the proposed solution and those in [27] and [1] for a 2-core, 4-core, 6-core and 8-core processor architecture. Comparison between the proposed solution and those in [1], [27], and [28] based on energy consumption. The proposed solution offers better than 4% of gain than the approach in [27] and 6.7% of gain than that in [1] when 100% of tasks finish execution in WCETs, and 8% of gain over the approach in [27] and 15% of gain over that in [1] when 20% of tasks finish execution in WCETs.
The particularity of this work is based on multi-speed cores and lies in using lower core speed first when executing tasks and reducing execution speeds in some processor cores to consume less energy. Migrating tasks from an over-loaded processor to a less loaded one allows to find a schedule that guarantees the feasibility of the system and balance the workload among all processors.   [1] and [27] when 60% of tasks finish execution in WCETs.

FIGURE 11
. Energy evolution of the proposed solution and those in [1], [27] when 40% of tasks finish execution in WCETs. Table 13 and Fig. 13 show that the proposed approach produces better results than those in [10] and [28] in terms of computational time for instances of 10 to 25 tasks with a multi-processor platform composed of 10 and 15 processors. It offers more than 70% of gain over the approach in [10] and a gain of 60% over the approach in [28]. These approaches fail to address the context of reconfigurable systems and multi-core architectures which can act directly on the quality of generated result and how long.
The proposed approach is also compared with [7], [38], and [28] in terms of computational time and makespan. The numerical results are described in Table 14. The first VOLUME 8, 2020  Comparison between the proposed solution and those in [28], [38], and [7].  column shows the problem sizes i.e., the number of tasks and processors. The sub-column labelled ''Computational time'' indicates the running time in milliseconds for each method. The next one labelled ''Makespan'' describes the makespan which is defined as the completion time of the last task in schedule sequence [39], [40].
The comparison produces better solutions either in computational time (Fig. 14) or makespan (Fig. 15) and confirms FIGURE 14. Comparison between the proposed solution and those in [7], [28], and [38] based on computational time.
the advantage of the proposed solution over existing methods. It presents more than 75% of gain over that in [38] and a gain of 80% than that in [7] according to computational time. Observing makespan, the proposed approach can improve results by 61% over that in [38] and 49% against that in [7]. It gives also a gain more than 35% over that in [28]. The integer programming model represents a useful and optimal method but it can be computationally intensive to be used for large instances. However, it is gainful to produce a lower amount of energy consumed by a given system. Our solution combines a kind of constraints such as energy, makespan and computational time to generate a well-balanced solution that respects all constraints and may be more appropriate for reconfigurable systems.

C. DISCUSSION
The proposed solution offers better than 4% of gain over that in [27], 6.7% of gain over that in [1] when 100% of tasks finish execution in WCETs, 8% of gain over that in [27], and 15% of gain over that in [1] when 20% of tasks finish execution in WCETs. It also improves by 80% the overall FIGURE 15. Comparison between the proposed solution and those in [7], [28], and [38] based on makespan.
number of adjusted task periods over that in [27] and by 93% over that in [1].
The proposed solution also offers great gain that can reach 60% over those in [10], [28] and 75% over those in [7], [38] according to the computational time. Makespan comparison further validate its superiority to those in [7], [38], and [28] with an improvement of 35% to 49%.
Using lower core speed first when executing tasks, reducing execution speeds in some processor cores to consume less energy and migrating tasks from an over-loaded processor to a less loaded one after reconfiguration scenarios is the most significant contribution of this research. It allows to find a schedule that guarantees the feasibility of the system, reduce energy cost and yield more opportunity to the load balancing among processing cores. Note that some issues like task dependency and resource sharing [41] should be considered in the model development.

V. CONCLUSION
Energy consumption is a decisive metric in the phase of evaluating the performance of a real-time system. Better management of the power sources of a system to reduce this metric requires effective solutions. These solutions depend on task models and considered architectures. In addition, a realtime task scheduling problem on a multi-core architecture is known to be NP-hard and remains difficult to solve.
We propose a scheduling strategy that acts on multi-speed cores and consists of three solutions (Partitioning tasks on different cores, period adjustment and task migration) depending on configuration scenarios. An ILP is formulated to define an execution model that deals with the assignment of tasks to different cores with the optimal energy consumption.
From the experimental results, we conclude that the proposed solution improves the energy consumption in the whole system while keeping its feasibility. In the future work, we plan to focus on an extended execution model that considers mixed categories of tasks (aperiodic and sporadic) related by dependency constraints. Communication and migration costs should also be considered since they are often present in real-time applications. We can transform dependent tasks to independent by using a virtual processor. We intend to implement real-time middleware that embeds the proposed contribution and some intelligent optimization methods [40], [42]. In the future, we plan to use the developed method to the social networks [43], [44] and discret event systems [45]- [47].