An Efficient Reconfigurable RF-DC Converter With Wide Input Power Range for RF Energy Harvesting

This paper presents a reconfigurable radio frequency to direct current (RF-DC) converter operating at 902 MHz frequency designed to efficiently harvest RF signals and convert into useable DC voltages for RF energy harvesting applications. The proposed scheme employs a dual-path, a series (low-power) path and a parallel (high-power) path, to maintain high power conversion efficiency (PCE) over wide input power range. The dual-path is composed of two identical rectifier blocks utilizing internal threshold voltage cancellation (IVC) technique to efficiently compensate the threshold voltage of the transistors used as rectifying devices. An adaptive control circuit (ACC) consisting of a comparator, an inverter and three switches is used in the proposed scheme. The ACC activates the series path or the parallel path to maximize the harvested power based on the input power range. The proposed scheme is designed and fabricated in a 180 nm complementary metal-oxide semiconductor (CMOS) technology. The measurement results show that PCE of the proposed circuit is above 20% from −18 dBm to −5 dBm, maintaining 13-dB input power range with peak PCE of 33% at −8 dBm for 200 $\text{k}\Omega $ load resistance. The proposed circuit demonstrates −20.2 dBm sensitivity across 1 $\text{M}\Omega $ load resistance while producing 1 V output DC voltage.


I. INTRODUCTION
In recent years, radio frequency (RF) energy harvesting has become an intensive area of research for remote power supply of wireless sensors/devices in the Internet of Things (IoT), radio frequency identification (RFID) systems and biomedical implanted devices by eliminating the need for battery and its limited lifetime [1]- [4]. Depending upon batteries as reliable energy source for wireless sensors/devices impose several constraints including regular charging and maintenance of the batteries due to their limited lifetime and their The associate editor coordinating the review of this manuscript and approving it for publication was Vincenzo Conti . replacement in harsh environments. An RF-DC converter in an RF energy harvesting system scavenges the electromagnetic energy from ambient sources and converts into DC voltage for power supply of wireless sensor/devices [5]. Fig. 1 shows a block diagram of an entire far-field wireless power transfer (WPT) system which consists of a RF power source connected to a transmitting antenna, a radio channel, and a receiving antenna connected to an RF energy harvester [6]- [9]. The receiving antenna receives the incoming RF energy and forwards it to an impedance matching circuit which ensures the maximum power transfer from the receiving antenna to an RF-DC power converter. The RF-DC converter rectifies the incoming RF energy and converts into the output DC power. Finally, an energy storage component (capacitor or battery) is used to store the output DC voltage. The performance of the RF-DC converter, being the main component in RF energy harvesting system, can be evaluated by its power conversion efficiency (PCE) and sensitivity. The PCE is the ratio of power, harvested by the RF-DC converter, delivered to the load to the RF input power while sensitivity is the minimum input power required to generate DC voltage at the output. The PCE of the RF-DC converter can be expressed as [20]: where P in is the input power applied to the RF-DC converter, V OUT is the output DC voltage across the resistive load R L . In a far-field WPT system, the performance of an RF energy harvester is strongly affected by several factors. For example, limited signal strength received at the input of the RF energy harvester due to path loss, the unpredictable attenuations in the signal strength over distance from the power source [10], presence of hurdles/obstacles between the RF energy harvester and the power source, antenna orientation, and transmission medium in which the RF energy harvester is utilized. As a result, the overdrive voltages generated by the RF voltage levels are not large enough for the rectifying devices to have low conduction losses even after boosted by the impedance matching circuit. Consequently, the RF energy harvester fails to harvest the maximum possible energy and its performance degrades. Therefore, designing a high performance RF energy harvester over a wide input power range is a major challenge, especially at low input power levels.
A number of threshold voltage compensation techniques for the rectifying devices have been proposed in order to increase the efficiency of the RF energy harvesters. Technology-based techniques use Schotty diodes [11] or HSMS diodes [12] to implement the rectifier circuit. The drawbacks of these techniques are high production cost that is caused by the additional fabrication steps and integration with the standard CMOS integrated circuits. Circuit-based techniques including active/passive circuits are alternatively used for threshold voltage (V th ) compensation of transistors used as rectifying devices [13]- [27]. The active circuit reported in [13] requires external battery that results in increased cost and maintenance. On contrary, passive techniques generally do compensation of threshold voltage of the rectifying devices by using additional circuitry. An adaptive threshold voltage compensated scheme proposed in [14] uses auxiliary transistors to control gate-source voltage of the rectifying devices. A differential dual-path CMOS rectifier described in [15] employs an adaptive control circuit to control both high-power path and low-power path over extending input power range. However, high-power is always connected to antenna which increases the parasitic capacitances once the low-power path is activated to harvest the RF energy. Authors in [16], [17] implement maximum power point tracking (MPPT) technique selecting optimum number of rectifier stages to maintain high PCE over wide input power range. A differential CMOS rectifier used in [18] implements a reconfigurable circuit that reconfigure the stages from parallel to series and vice versa based on the RF power level. A hybrid threshold voltage compensated scheme used in [19] employs PMOS transistors as rectifying devices in all rectifier's stages except in first stage in order to eliminate the need of NMOS triple-well transistors. Author in [20] reports a dual-band rectifier implementing an internal threshold voltage compensation technique. A differential crosscoupled rectifier reported in [21] compensates the threshold voltage of the rectifying devices and minimizes their leakage current. A self-compensation scheme used in [22] consists of triple-will NMOS transistors in order to provide individual body biasing. A self-biasing circuit described in [23] provides DC biasing voltage by using off-chip impedance resistive network. Author in [24] presents a threshold voltage compensation circuit where passively generated compensated voltage stored on the capacitor is applied to gate-source terminal of the rectifying devices. A differential cross-coupled rectifier reported in [25] reduces the reverse-leakage current problem occurred in the conventional cross-coupled rectifier. However, differential circuits require a PCB balun for conversion of single-ended to differential or differential antenna which result in additional cost and large area on the PCB board. Authors in [26], [27] report a cascaded rectifier using dynamic threshold voltage cancellation (DVC) technique in combination with the internal threshold voltage cancellation (IVC) technique to efficiently compensate threshold voltages of the rectifying devices.
Most of the circuit solutions proposed in the literature have been designed to produce maximum PCE at a specific input power level and failed to harvest RF energy at wide low input power range. This paper presents a reconfigurable RF-DC converter that harvests the maximum possible RF energy and maintains high PCE over wide low input power range. The proposed circuit demonstrates superior performance to the published state-of-the-art work.
This paper is organized as follows. Section II describes the working principle of the proposed reconfigurable RF-DC converter. Section III explains the circuit description of the sub-blocks of the proposed architecture. Sections IV depicts the measurement results. Section V finally concludes the paper. VOLUME 8, 2020   Fig. 2 presents the conceptual idea applied in the proposed reconfigurable circuit. Fig. 2(a) and (b) display the PCE of a conventional single-path power converter that is optimized to operate efficiently at low input power and high input power, respectively. It is clear that the high-PCE can only be achieved over a narrow input power range for the single-path rectifier. On the contrary, Fig. 2(c) depicts a high PCE graph of the reconfigurable circuit. This high PCE, over wide input power range, is achieved by combining both graphs of Fig. 2(a) and (b). Fig. 3 shows block diagram of the proposed reconfigurable RF-DC converter. The proposed scheme is composed of two identical rectifier blocks, three MOSFET switches (SW 1 , SW 2 and SW 3 ), a comparator, and an inverter. The switches are used to reconfigure the proposed circuit and are controlled by the output of the comparator and the inverter. The transistors used in the proposed architecture are low threshold voltage (LVT) of general purpose (GP). Fig. 4 presents the working principle of the proposed circuit. Fig. 4(a) shows the series-path operation of the proposed circuit for low input power range. The comparator compares output voltage (V OUT ) of the proposed circuit to a reference voltage (V REF ).

II. PROPOSED RECONFIGURABLE RF-DC CONVERTER
As long as the V OUT is lower than the V REF , the comparator gives low-voltage ''VCMP = L'' and the inverter gives highoutput ''H''. This mechanism turns-on the switch SW 1 and turns-off the switches SW 2 and SW 3 to allow the two identical rectifier blocks to operate in series with each other. This increases the harvested power at the output and eventually increases the PCE of the proposed scheme at the low input power range. Fig. 4(b) represents parallel-path operation of the proposed circuit for high input power range. When V OUT becomes higher than the V REF , the comparator produces high-voltage ''VCMP = H'' and inverter produces low voltage ''L''. This process turns-off the switch SW 1 and turns-on the switches SW 2 and SW 3 to allow the two identical rectifier blocks to operate in parallel with each other. This increases the PCE of the proposed scheme at high input power level. Consequently, the overall PCE of the proposed reconfigurable circuit is extended and improved over extended input power range.  Fig. 5(b), the rectifying devices M p1 and M p2 are reversed-biased, and V sg of M b is larger than its V th to turn it on. This reduces source-gate voltages (V sg1 and V sg2 ) of transistors (M p1 and M p2 ) to zero, respectively, and consequently minimizes the leakage current in the rectification chain. The auxiliary capacitor, C aux , stores some charge which is lost during reversed-biased condition. Indeed, the voltage drop (V aux ) across capacitor C aux is obtained from both forward and reverse conduction and can be written as:

III. CIRCUIT DESCRIPTION
By applying the Kirchhoff Voltage Law (KVL) in Fig. 5.   where V in is the peak RF input amplitude. The output DC voltage (V RECT ) of the rectifier can be written as: where V sd1 is the source-drain voltage of the M p1 . By replacing V in of Eq. (3) in Eq. (4), V RECT can be written as: Similarly, By subtracting (6) from (5), it can be written as: The V sg2 of the M p2 increases as long as the output voltage (V RECT ) of the rectifier increases. When the V sg2 is equal to the threshold voltage of the M p2 , the M p1 enters the saturation region. As a result, the proposed circuit compensates the effect of threshold voltage and improves the PCE and output DC voltage V RECT .

B. ADAPTIVE CONTROL CIRCUIT DESIGN
Due to limited harvested power from ambient environment, power consumption must be taken into account when design low-power adaptive control circuit (ACC). The ACC consists of a common-gate input comparator, an inverter and three switches (SW 1 , SW 2 and SW 3 ). The common-gate input VOLUME 8, 2020  comparator is the key circuit of the ACC. Fig. 6 displays the circuit diagram of the common-gate input comparator having same structure as described in [15]. The comparator compares the output voltage (V OUT ) of the proposed circuit to the reference voltage (V REF ) and controls the switches (SW 1 , SW 2 and SW 3 ) in order to reconfigure the proposed circuit depending upon the input power level. At low input power conditions, the current consumption of the comparator is exponential and is negligible. Moreover, high voltage devices with low-current conduction are used in the comparator to avoid extra current consumption at high input power conditions.

A. CHIP MICROPHOTOGRAPH AND MEASUREMENT SETUP
The proposed reconfigurable RF-DC converter is fabricated in a standard 180 nm CMOS technology. Fig. 7(a) presents the chip microphotograph of the proposed circuit having an active die area of 340 µm × 310 µm, excluding the pads. Fig. 7(b) depicts the measurement setup to check the performance of the proposed circuit. The fabricated chip is wire-bonded on a PCE board. A single-tone sinusoidal signal operating at 902 MHz is generated by Agilent E4438C signal generator to test the chip. An Oscilloscope, Tektronix TDS 2024B, and a digital voltmeter are used to record the output DC voltage. An off-chip pi-matching circuit is implemented onto the PCB board to match the input impedance of the proposed circuit to 50 and reflection co-efficient |S 11 | is calculated. The net input power that is given to the chip is calculated after excluding the transmission losses and the reflection losses.

B. PERFORMANCE MEASUREMENT
The performance of the proposed circuit is determined by the PCE and the output DC voltage versus input RF power. The measured reflection co-efficient |S 11 | at 902 MHz of the proposed circuit is −27.5 dB. To check the performance of the series path and parallel path separately, two off-chip control pins can be used to enable/disable the series and the parallel path. When both pins are connected to a high voltage, the proposed circuit operates in the adaptive selection mode. Fig. 8(a) shows measured PCE of the proposed circuit versus input power range for an optimum load resistance of 200 k . Measurement results show that more than 20% PCE is achieved from −18 dBm to −8 dBm for series (lowpower) path with peak PCE of 34% at −13 dBm. Similarly, PCE is above 20% from −12 dBm to −5 dBm for parallel (high-power) path with peak PCE of 35% at −8 dBm. When the adaptive control circuit automatically selects the  dual-path depending upon the value of V OUT and V REF , the PCE of the proposed circuit is above 20% from −18 dBm to −5 dBm with peak PCE of 33% at −8 dBm and maintains 13-dB input power range. Even though the switches used to reconfigure the proposed circuit are not ideal switches due to process variations, the PCE of the proposed scheme with adaptive path control circuit is still improved. Fig. 8(b) depicts the measured output DC voltage versus input power range for load resistance of 200 k . The output DC voltage of the series (low-power) path is higher than the parallel (high-power) path from −19 dBm to −11 dBm. From −10 dBm to onward, output DC voltage of the parallel path is higher than the series path. Fig. 9(a) shows the measured PCE of the proposed circuit for different loads. The peak efficiencies of the proposed circuit are 33%, 32%, 31%, and 28.5% at input power levels of −8 dBm, −15 dBm, −16, and −17 dBm for load resistances of 200 k , 400 k , 600 k , and 1 M , respectively. Fig. 9(b) displays the measured output DC voltages of the proposed circuit for different loads. It can be seen that the output DC voltage increases with the increase in load resistances. Fig. 10(a) and (b) depict measured PCE and output DC voltage of the proposed circuit versus frequency at different input power levels for 200 k load, respectively. Since the proposed circuit is optimized and designed for 902 MHz, it gives superior performance at 902 MHz to the other frequencies. The proposed circuit achieves a sensitivity of −20.2 dBm while producing 1 V output DC voltage for 1 M resistive load. Table 1 summarizes the measurement results of the proposed circuit and its performance is compared with the published state-of-the-art works. The proposed circuit provides a reconfigurable structure to achieve high PCE over extended input power range. Despite being single-ended structure, the proposed circuit shows better performance than most of the reported works. The PCE is above 20% from −18 dBm to −5 dBm over 13-dB input power range. The peak PCE of 33% is achieved at −8 dBm with an output DC voltage of 3.23 V across 200 k load resistance. The proposed circuit achieves wider input power range than the circuits reported in [14], [15], and [21] while demonstrates better sensitivity than the circuits reported in [15], [16], [22], and [25].

V. CONCLUSION
In this paper, a reconfigurable RF-DC converter operating at 902 MHZ frequency to efficiently harvest radio frequency energy is presented. The proposed architecture uses a dual-path, a series (low-power) path and a parallel (highpower) path, to maintain high PCE over extended input power range. The adaptive control circuit activates the series path or the parallel path based on the input power level to maximize the harvested power at the output. Despite of process variations of the switches, the proposed circuit still achieves better PCE over extended input power range. The proposed scheme has been designed and fabricated in 180 nm CMOS technology. The measurement results show that the PCE of the proposed scheme is above 20% from −18 dBm to −5 dBm with peak measured PCE of 33% at −8 dBm. The proposed circuit obtains −20.2 dBm sensitivity for 1 M load while producing 1 V output DC voltage. Since 2012, he has been with College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South Korea, where he is currently a Professor. His research interests include implementation of power integrated circuits, CMOS RF transceiver, analog integrated circuits, and analog/digital mixed-mode VLSI system design.