A Multi-Mode ULP Receiver Based on an Injection-Locked Oscillator for IoT Applications

This paper presents an ultra-low-power receiver based on the injection-locked oscillator (ILO), which is compatible with multiple modulation schemes such as on-off keying (OOK), binary frequency-shift keying (BFSK), and differential binary phase-shift keying (DBPSK). The receiver has been fabricated in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology and operates in the ISM band of 2.4 GHz. A simple envelope detection can be used even for the demodulation of BFSK and DBPSK signals due to the conversion capability of the ILO from the frequency and phase to the amplitude. In the proposed receiver, a <inline-formula> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula>-enhanced single-ended-to-differential amplifier is employed to provide high-gain amplification as well as narrow band-pass filtering, which improves the sensitivity and selectivity of the receiver. In addition, a gain-control loop is formed in the receiver to maintain constant lock range and hence frequency-to-amplitude conversion ratio for the varying power of the BFSK-modulated receiver input signal. The receiver achieves the sensitivity of −87, −85, and −82 dBm for the OOK, BFSK, and DBPSK signals respectively at the data rate of 50 kb/s and the BER lower than 0.1% while consuming the power of <inline-formula> <tex-math notation="LaTeX">$324~\mu \text{W}$ </tex-math></inline-formula> in total.


I. INTRODUCTION
As a variety of services and applications based on the internet of things (IoT) have been widely developed, the demands on ultra-low-power wireless techniques for data transmission and reception have grown rapidly. The capability of performing wireless communication with little power consumption is a key factor enabling the operation of wireless sensor nodes for IoT [1]. As the complexity and scale of the IoT system increases and the number of sensor nodes in the network becomes large, connecting the sensor nodes to the power lines makes the installation of the system prohibitively expensive if not impossible. It is therefore preferred to power the sensor nodes by batteries. In such battery-powered sensor nodes, low power consumption is an essential requirement considering that the power consumption of the sensor node determines The associate editor coordinating the review of this manuscript and approving it for publication was Rongbo Zhu . the replacement or recharging frequency of the battery and directly affects the maintenance cost of the IoT system. Furthermore, to realize the vision of the hyper-connected world filled with trillions of sensor nodes, researchers are working toward the energy-autonomous operation of the wireless sensor nodes, which are powered by the energy harvested from their ambience. In this scenario, the average power consumption of the overall sensor node must be lower than the average rate of energy harvesting. It poses extreme limitations on the power budget of the wireless sensor node, even if the duty-cycled operation scheme is employed to cut down the amount of the power dissipated on average. Since the wireless transceiver is the most power-hungry block in the typical wireless sensor node, reducing the power consumed for wireless communication is critical.
On the other hand, the choice of modulation scheme has a significant impact on the transceiver design in various aspects such as power consumption, complexity, performance, and reliability. For short-range low-power communication, the transceivers based on on-off keying (OOK) have been widely implemented. The OOK modulation scheme allows achieving very low power consumption because of the simple circuit architecture used for the transceiver design. For example, the demodulation function of the receiver can be implemented by using an envelope detector without requiring any highpower-consuming circuit components such as oscillators, mixers, and frequency synthesizers [2]- [4]. However, the OOK receiver based on such a simple structure has low sensitivity and high susceptibility to the interferers compared to the receivers employing other modulation schemes such as frequency-shift keying (FSK) and phase-shift keying (PSK). To overcome the limited sensitivity performance, a high-gain amplifier and an expensive external filter are required to precede the envelope detector [2]. The FSK modulation with a constant envelope, on the other hand, enables the use of an energy-efficient nonlinear power amplifier in the transmitter. However, the receiver requires the precise local oscillator and quadrature signal paths, which results in a complex receiver structure consuming relatively high power.
Recently, to overcome the limitations of the conventional receivers, a variety of new receiver structures for ultra-lowpower (ULP) consumption have been introduced (Fig. 1). Fig. 1(a) shows the structure of the uncertain-IF receivers [5]. In this structure, a low-power free-running ring oscillator is used to generate the local oscillator (LO) signal for downconversion. Due to the inherent uncertainty of the LO signal frequency, the IF frequency is not clearly determined, and the selectivity performance of the receiver is therefore low. Fig. 1(b) shows the low-IF receiver structure, where the receive path itself operates as a part of the frequencylocked loop (FLL) for LO generation [6]. Since the mixers in the receive path perform frequency down-conversion for not only receiver function but also FLL operation, the highprecision LO signal can be generated without using a powerhungry frequency divider. However, the structural complexity is high due to the FLL and quadrature demodulation circuits. Fig. 1(c) shows the receiver structure based on the injection-locked oscillator (ILO) [7], [8]. The ILO plays an essential role of converting the frequency-modulated signal to the amplitude-modulated signal, which enables the energyefficient implementation of the FSK receiver. The amplitudemodulated signal generated by the ILO is down-converted by the envelope detector as in the conventional low-power OOK receiver. This structure, however, faces significant challenges in that the amplitude of the signal injected to the ILO should be sufficiently large for guaranteeing proper injectionlocking operation and kept relatively constant for maintaining consistent frequency-to-amplitude conversion ratio.
In this paper, we propose a low-power receiver design based on ILO, which can support multiple modulation schemes: OOK, binary FSK (BFSK), and differential binary PSK (DBPSK). The proposed receiver enables more robust communication based on FSK and PSK modulation schemes than the simple OOK receiver when necessary, without causing any power penalty. Also, in the case where the power reduction of the transmitter is critical, the FSK modulation with a constant envelope can be utilized to allow the use of an energy-efficient nonlinear power amplifier. A Q-enhanced single-ended-to-differential amplifier (SDA) is employed to provide high gain and generate the injection signal with sufficient strength. Moreover, the consistency of the receiver performance is greatly improved by controlling the amplitude of the injection signal in a closedloop manner. The rest of this paper is organized as follows. Section II describes the overall receiver architecture, and Section III explains the principles of the ILO-based receiver operation performing the frequency-to-amplitude, VOLUME 8, 2020 phase-to-amplitude, and amplitude-to-amplitude conversions. Then, the circuit implementation details of the proposed RF receiver are described in Section IV, and the measurement results of the implemented receiver are presented in Section V. Finally, Section VI draws the conclusion. Fig. 2 is the block diagram showing the overall architecture of the proposed wireless receiver system, consisting of the front-end matching network, RF receiver IC, and microcontroller unit (MCU). In the RF receiver IC, the ILO converts the received OOK/BFSK/DBPSK signal to the amplitudemodulated signal. Based on such ILO operation, an energyefficient wireless receiver can be realized by employing an envelope detector (ED) for RF-to-baseband frequency downconversion and demodulation. The external MCU generates a gain control signal for the SDA based on the output amplitude of the baseband amplifier (BB AMP), which is measured by the peak detector. Through this closed-loop control, the magnitude of the RF signal injected to the ILO can be kept fairly constant, and hence a significant change in the frequency-toamplitude conversion ratio of the ILO can be prohibited when the BFSK signal is received.

II. OVERALL RECEIVER ARCHITECTURE
The RF signal received by the antenna is fed to the preamplifier (Pre-AMP) through the matching network. The Pre-AMP amplifies the RF signal with moderate gain and provides isolation between the matching network and the SDA input to relieve the requirement of input-impedance matching for the SDA.
The SDA converts the single-ended input signal into an amplified differential signal driving the ILO. The Q-enhancement technique is applied to the SDA so that high gain can be achieved over a narrow frequency band. The high gain property allows obtaining the injection signal with an amplitude larger than the minimum required for locking the ILO even when the received RF signal is very weak, thereby enhancing the sensitivity of the receiver. Since the Q-enhanced SDA acts as a band-pass filter having a narrow passband, the selectivity of the receiver is also improved.
The differential output of the SDA is injected to the ILO, where the OOK/BFSK/DBPSK signal is converted into the amplitude-modulated signal. For the OOK signal, the ILO simply adds the constant amount of signal amplitude as explained in Section III, and thus the amplitude variations of the input signal are preserved at the ILO output. In the case of the BFSK signal, the ILO output has a large amplitude when the frequency of the injection signal (ω inj ) is close to the free-running frequency of the ILO (ω 0 ), while the output amplitude becomes small when ω inj is far from ω 0 . For the DBPSK signal, the output amplitude of ILO fluctuates when the phase of the injection signal changes abruptly. The ILO not only translates the OOK/BFSK/DBPSK signal to the amplitude-modulated signal but also improves the receiver sensitivity because the weak RF signal injected to the ILO generates the oscillator output signal having a relatively large swing.
The ILO output at RF is then converted down to the baseband by the ED. The baseband signal is further amplified by the BB AMP, and the BB AMP output is processed by the comparator to produce the final output data. Note that the output data for the DBPSK signal exhibits a return-to-zero (RZ) signal characteristic, as explained in Section III-C, from which the input data can be recovered by converting the RZ data to the non-return-to-zero (NRZ) data.
For reliable BFSK signal reception and demodulation, the frequency-to-amplitude conversion ratio of the ILO should not vary excessively. However, if the lock range of the ILO changes due to the varying magnitude of the injection signal, the frequency-to-amplitude conversion ratio doesn't stay constant, as explained in Section III. In this work, the strength of the ILO injection signal is regulated in a closed-loop manner, so that the ILO can provide a consistent frequency-toamplitude conversion ratio. The peak detector in the receiver IC measures the amplitude of the BB AMP output, and this amplitude information is sent to the external MCU. Then, 76968 VOLUME 8, 2020  the digital-to-analog converter (DAC) embedded in the MCU generates the control signal to adjust the gain of the SDA, thus maintaining the strength of the ILO injection signal relatively constant.

III. OPERATION PRINCIPLES OF ILO-BASED RECEIVER
A. BASIC ILO OPERATION Fig. 3(a) shows the conceptual diagram of the ILO. When there is no injection signal applied, the oscillator runs freely at ω 0 , which is the resonance frequency of the LC tank. At ω 0 , the Z tank contributes no phase shift, as illustrated in Fig. 3(b), while the inverting buffer and M 1 create a total phase shift of 360 • . In the free-running condition, the magnitude and phase of I tank are the same as those of I osc , as shown in Fig. 4(a). Now assume that the injection current I inj having the frequency of ω inj is applied to the ILO. Since the I tank should be the vector sum of I osc and I inj , the relationship among I osc , I inj , and I tank can be described by the phasor diagram as in Fig.  4(b). Before locking, the phasors, I osc , I inj , and I tank rotates clockwise with different angular velocities, ω osc , ω inj , and ω tank , respectively. Hence, the angle θ between I osc and I inj , as well as the angle φ between I osc and I tank , varies over time.
After this transition process, if I inj is not too small and ω inj is not too far from ω 0 to achieve injection-locking, the angle between the I osc and I tank becomes φ 0 , as shown in Fig. 4(c), and this phase difference is compensated by the phase shift of Z tank , as described in Fig. 3(b). It makes the total phase shift around the feedback loop become 360 • , and thus the ILO locked to the injection signal. Once injectionlocked, the phasors I osc , I inj , and I tank rotate with the same angular velocity of ω inj , keeping φ and θ constant at φ 0 and θ 0 , respectively [9]. From Fig. 4(c), the following relationships can be derived: and As the frequency of injection signal (ω inj ) deviates farther from the self-resonance frequency of the ILO (ω 0 ), the phase shift introduced by Z tank (φ 0 ) grows, as found in Fig. 3(b), and the angle between I osc and I tank , which is depicted in Fig. 4(c), becomes larger. If ω inj keeps departing from ω 0 and finally reaches the edge of the lock range ω L , φ 0 comes to have its maximum possible value φ 0,max [10]: when The phasor diagram under this condition is illustrated in Fig. 4(d), where the I inj and I tank form a 90 • angle. From Fig.  4(d), we can also find that Since the phase shift, φ 0 of Z tank at the frequencies close to ω 0 is described by [10] tan the ω L can be expressed as Note that ω L is a function of Q (= quality factor of the LC tank), ω 0 , |I osc |, and |I inj |. Since the values of Q, ω 0 , and |I osc | are given by design, these values experience only a little change during operation, which is caused by the variations in the supply voltage and ambient temperature. In contrast, |I inj | can vary significantly and results in large variations of ω L , as the amplitude of the received input signal changes. The lock range ω L increases as the injection signal I inj becomes stronger.
Using the operation characteristics of the ILO investigated in this sub-section, an energy-efficient ILO-based receiver VOLUME 8, 2020 can be implemented, which translates the signal modulated with various modulation schemes such as OOK, BFSK, and DBPSK into a simple amplitude-modulated signal. In the following sub-sections, the principles of such conversions performed by the ILO-based receiver are analyzed and discussed.

B. CONVERSION OF BFSK SIGNAL
Assume that the injection frequency ω a representing the data bit of '1' is set close to the self-resonance frequency ω 0 and hence θ a ≈ 0 as depicted in Fig. 5(a). Then, from (1), the |I tank,a | can be approximated as The output voltage amplitude of the ILO corresponding to '1' (= |V out,a |) is produced by the multiplication of |I tank,a | and Since |I tank,a | and |Z tank (ω a )| are close to the maximum possible values of |I tank | and |Z tank | respectively, V out,a presents nearly the largest output swing.
On the other hand, if the injection frequency ω b = ω a + ω used to indicate the data bit of '0' is set far from ω 0 but within the lock range, as shown in Fig. 5(b), the |I tank,b | is given by The output voltage amplitude of the ILO corresponding to '0' (= |V out,b |) is derived by multiplying |I tank,b | with |Z tank (ω b )| (< |Z tank (ω 0 )|). Since |I tank,b | and |Z tank (ω b )| are smaller than |I tank,a | and |Z tank (ω a )| respectively, |V out,b | is also smaller than |V out,a |. How large amplitude difference between V out,a and V out,b is obtained for the frequency deviation of ω = |ω b − ω a | determines the frequency-toamplitude conversion ratio.
Note that once the injection frequency ω b for the data bit of '0' is determined, the corresponding phase shift φ b is fixed as described in Fig. 3(b). It can be found in Fig. 5(b) that, for the same φ b , if |I inj | increases, θ b decreases, and hence cos θ b approaches 1. In other words, the difference between |I tank,a | and |I tank,b | becomes smaller, and thus the frequency-to-amplitude conversion ratio decreases as |I inj | increases. It demonstrates the need for prohibiting any significant variations in the magnitude of I inj to obtain a consistent demodulation performance over a wide range of received RF signal strength.
To achieve a good sensitivity, the receiver should be designed to operate even with a very weak RF input signal, which leads to a very small amplitude of I inj . Since ω L is narrow for small |I inj | as predicted by (7), the ω a and ω b cannot be separated too far from each other. The ILO-based receiver is therefore designed to generate a distinguishable amplitude change for such a small frequency difference when |I inj | is small. However, if a strong RF signal is received and hence the amplitude of I inj increases, the ω L becomes wide, and the frequency-to-amplitude conversion ratio reduces significantly, resulting in too small amplitude change at the ILO output to be discriminated properly. To avoid this problem, it is important to control the magnitude of I inj to stay relatively constant.

C. CONVERSION OF DBPSK SIGNAL
The conversion process from the DBPSK-modulated signal to the amplitude-modulated signal by the ILO is depicted in Fig. 6. Since I tank is the vector sum of I osc and I inj , and V out is the multiplication of I tank and Z tank , when there is a phase change of π in I inj , the amplitude of V out changes accordingly [11].
When the ILO is in the injection-locked state and I inj forms the angle of θ a with respect to the I osc to represent the data bit of '1', |I tank,a | is given by I tank,a = |I osc | 2 + I inj 2 + 2 |I osc | I inj cos θ a , (10) as described in Fig. 6(a).
If the angle between I inj and I osc changes to θ b = θ a + π which corresponds to the data bit of '0', the ILO is perturbed from its injection-locked state and the magnitude of I tank experiences an instantaneous change to |I tank,b |, which is expressed as as depicted in Fig. 6(b). After this transient change, as the frequency of the injection signal does not change, the ILO returns to the injection-locked state, as shown in Fig. 6(a) and the magnitude of I tank settles back to |I tank,a |. In other words, the output amplitude of ILO fluctuates when the phase of the injection signal changes abruptly. As a result, the phase change in the injection signal is translated to the transient variation of the output amplitude, and this amplitude variation can be captured by the following ED circuit, obviating the need for power-hungry circuit blocks such as the frequency synthesizer and mixer. Note that the output of the ED behaves like an RZ signal, which requires a conversion to the NRZ signal for input data recovery [11].  Fig. 7 shows how the amplitude variations of the OOKmodulated input signal are preserved at the ILO output. When I inj is on to present the data bit of '1', the I inj is added to the I osc to produce I tank , and hence the amplitude of I tank (= |I tank,a |) becomes larger than that of I osc :

D. CONVERSION OF OOK SIGNAL
On the other hand, if I inj is off to present the data bit of '0', the amplitude of I tank (= |I tank,b |) becomes the same as that of I osc : Multiplied by Z tank , the I tank generates the amplitudemodulated V out signal.
In conclusion, the OOK input signal is also processed by the ILO to generate the amplitude-modulated signal at the output, as in the cases of BFSK and DBPSK input signal. Based on this conversion process of the ILO, an energyefficient receiver IC can be constructed. The implementation details of the receiver circuits are described in the next section.

IV. CIRCUIT IMPLEMENTATION A. RF FRONT-END
The Pre-AMP and SDA amplify the received RF signal to obtain the signal with an amplitude larger than the minimum required to lock the following ILO. The Pre-AMP is based on the conventional cascode common-source structure with inductive degeneration and tuned load circuit [12]. Offchip inductors and capacitors are used to construct the input matching network. Due to the good isolation characteristic of the cascode structure, a stable input matching performance is obtained without being affected by variations of the impedance at the output. The voltage gain of the Pre-AMP is given by where L S is the degeneration inductance, and ω 0 and R L are the resonance frequency and parallel equivalent resistance of the load tank circuit, respectively. The second amplifier stage following the Pre-AMP is designed to not only provide a high voltage gain but also convert the single-ended input signal to the differential output signal, which leads to the Q-enhanced SDA structure. It is well known that the differential signaling has an inherent immunity against the common-mode noise and disturbances, and the differential injection significantly reduces the minimum amplitude needed for the injection-locking of the LC oscillator compared to the single-ended injection. The SDA design employs a Q-enhancement technique and a parallel resonant circuit structure.
The operation principle of the Q-enhanced amplification can be explained by using the equivalent circuit model shown in Fig. 8. This circuit operates in two different modes [13]. When |−G m | < 1/R p , the amount of energy put into the circuit by active devices is not enough to overcome the tank loss and build up the oscillation. The circuit, therefore, operates as a Q-enhanced amplifier. Conversely, if |−G m | > 1/R p , the circuit operates in the oscillation mode.
The quality factor Q of the parallel resonant circuit in Fig.  8 is given by [14] Q = ω 0 energy stored average power dissipated = where BW is the 3-dB bandwidth of the parallel resonant circuit and R p,eff is calculated as When the circuit in Fig. 8 operates in the amplifier mode, a high Q leads to a high voltage gain and a narrow amplification bandwidth, which improves the selectivity of the receiver. From (15) and (16), it is found that the Q varies as the value of |−G m | changes. When the |−G m | is much smaller than 1/R p , the circuit operates in the amplification mode, and the Q of the circuit is low. As the |−G m | increases, the Q increases, approaching infinity when |−G m | reaches the value of 1/R p . If the |−G m | continues to increase beyond 1/R p , the circuit enters the oscillation mode. Based on this characteristic, it is possible to implement a Q-enhanced amplifier with high gain and narrow bandwidth by operating the parallel resonant circuit as an amplifier and setting its |−G m | value close to 1/R p [15], [16].
The core circuit of the proposed Q-enhanced SDA is based on the aforementioned parallel resonant circuit structure and its simplified schematic diagram is shown in Fig. 9(a). This circuit oscillates when the voltage at the drain node is 180 • out of phase with respect to the voltage at the gate node, and the negative conductance generated by the MOS transistor is larger than 1/R 1 . If we set the negative conductance value to be slightly smaller than 1/R 1 and take the differential outputs from the gate and drain nodes, this circuit operates as a Q-enhanced SDA. The input signal is applied to the drain node in the form of current. VOLUME 8, 2020 To investigate the operation of the circuit shown in Fig. 9(a), the feedback loop of this circuit can be cut at the gate node of the MOS transistor to analyze the loop gain characteristic. By using the small-signal equivalent circuit given in Fig. 9(b), the loop gain can be calculated as where Z LC is the total equivalent impedance of the circuit network composed of L 1 , C 1 , and C 2 , and F v is the voltage division factor caused by the series-connected L 1 and C 2 .
The Z LC is given by and F v is expressed as where Note that F v introduces a phase inversion at the frequencies higher than ω inv , as depicted in Fig. 10(a). Substituting (18) and (19) into (17), the loop gain is derived as If this circuit oscillates, the oscillation frequency is given by At this oscillation frequency, the magnitude of the loop gain is calculated as  which needs to be greater than 1 for the oscillation to occur. The magnitude of the loop gain shows the frequency characteristic, as presented in Fig. 10(b). From (20) and (22), we can find that ω 0 is higher than ω inv . Therefore, the feedback network causes a phase shift of 180 • at ω 0 , which is added to the phase inversion generated by the MOS transistor, leading to a total phase shift of 360 • along the loop. If the transconductance value is controlled in such a way that the magnitude of the loop gain stays slightly lower than 1, the circuit can be operated as a Q-enhanced amplifier. Moreover, if the output voltages are taken from the gate and drain nodes of the MOS transistor while the input current is applied to the drain terminal, the circuit can also be used to convert the single-ended input to the differential output.
The complete circuit diagram of the proposed Q-enhanced SDA is shown in Fig. 11. M 3 converts the input voltage V in to the corresponding input current, which is fed to the drain node of M 1 through M 2 . M 2 is used as a cascode element to provide isolation between the input and output terminals. The voltage gain of this Q-enhanced SDA can be controlled by adjusting the gate bias voltage V CTRL of M 3 . The V CTRL determines the bias current flowing through M 1 and hence its transconductance, which in turn affects the Q-enhancement factor of the parallel resonant circuit formed by M 1 , L 1 , C 1 , and C 2 . If the inherent Q of the inductor L 1 is high, a large gain can be obtained with flowing small bias current. In other words, by using a high-Q inductor, the power consumption of the Q-enhance SDA can be reduced. In this work, an off-chip inductor component having a high Q is used.
The center frequency and amplification gain of the SDA need to be tuned to accommodate the manufacturing process tolerances. We employ a tuning method similar to the one used in [15]. For frequency tuning, the V CTRL is initially controlled to flow large enough bias current to oscillate the circuit. In the oscillation mode, the center frequency is tuned to the target value by controlling the capacitor banks C 1 and C 2 . Once the frequency tuning is completed, the V CTRL is adjusted again to enter the amplification mode and tune the amplification gain to the wanted value. Fig. 12 presents the schematic diagram of the ILO used in our design. The ILO consists of a current injection circuit (M 6−10 ) and an oscillator core circuit (M 1−5 , L 1 , and C 1 ). In this topology, the complementary cross-connected MOS transistor pairs (M 1,2 for the PMOS pair and M 3,4 for the NMOS pair) provide negative resistance. The current injection circuit plays a role of converting the differential injection voltage to the differential injection current that is fed to the oscillator core circuit. In the oscillator core, a capacitor bank is employed so that the free-running frequency of the ILO can be tuned to the desired value.
The schematic diagram of the fully differential ED is shown in Fig. 13 [17]. The nonlinear I -V characteristics of the NMOS transistor M 3,4 and the PMOS transistors M 1,2 are used to down-convert the RF signal at the input to the baseband signal at the output. The common-gate topology is used, i.e., the input is applied to the source nodes of the transistors, and the output is taken from the drain nodes of the transistors. The low-pass filters, formed by C 3,4 and R 2,3 are placed to filter out high-frequency components produced where V T is the thermal voltage and |V in | is the amplitude of the differential input voltage, |V inp -V inn |. The I Q is the quiescent current of the core transistors operating in weak inversion.

B. ANALOG BASEBAND
After the down-conversion by the fully differential ED, the signal resides in the baseband, which is processed by the analog baseband circuits consisting of a BB AMP, a comparator, and a peak detector. For baseband amplification, the conventional 2-stage fully differential operational amplifier is used. Compared to its single-ended counterpart, this balanced operational amplifier provides a larger effective output voltage swing and is less susceptible to common-mode noise and disturbances. Also, the even-order nonlinearities are canceled to the first order at its differential output. The voltage gain of the implemented BB AMP is 25 dB, and its operation bandwidth is from 300 Hz to 1 MHz.
The schematic diagram of the fully differential comparator is shown in Fig. 14, which employs the self-biasing structure [18]. The resistors R 1,2 are used to extract the common-mode output voltage from the replica-biasing circuit composed of M 5−8 , which is fed to the gate terminals of M 9,10 to control the bias current of the overall comparator circuit. This self-biasing scheme creates a negative feedback loop that stabilizes the operating point of the circuit. Note VOLUME 8, 2020  that the M 9,10 operate in the linear region, and therefore the output swing of the comparator can be close to the difference between the two supply rails. Thanks to the fully differential structure of the compactor, the explicit reference voltage for comparison doesn't need to be generated.
As shown in Fig. 15, a positive peak detector is implemented using differential amplifiers (M 1−10 ), current mirrors (M 11−14 ), and a low-pass filtering load (R 1, C 1 , and M 15 ). If the V in is larger than V peak , the excess current flows through M 11,12 and is copied to M 13,14 , charging the C 1 , which holds the peak value. The R 1 provides a small amount of discharging current, and the M 15 is used for resetting C 1 . The droop rate of the peak detector can be controlled by adjusting the values of C 1 and R 1 .

V. MEASUREMENT RESULTS
The proposed ILO-based OOK/BFSK/DBPSK receiver has been fabricated with 0.18-µm CMOS process technology, and the chip micrograph is shown in Fig. 16. The total chip area, including the bonding pads, is 1.7 mm × 1.9 mm. The receiver is implemented using three inductors. Two of them are the on-chip inductors used for the Pre-AMP and ILO, and   the other is the off-chip inductor with high Q used for the SDA.
The input impedance matching characteristic of the receiver is shown in Fig. 17, while the combined gain of the Pre-AMP and SDA is plotted in Fig. 18 as a function of frequency. The magnitude of S 11 is lower than -10 dB over the frequency range from 2.36 GHz to 2.49 GHz, which covers the ISM band. The Pre-AMP and Q-enhanced SDA provides a high voltage gain up to 43 dB with narrow bandwidth, which improves the sensitivity as well as the selectivity of the proposed receiver. Fig. 19 shows the measured output waveforms of the ILO generated for the RF input signals with different modulation schemes. The baseband data of the input signal with a data rate of 50 kb/s is shown in Fig. 19(a). Based on this baseband data, -90-dBm RF input signals are gener- ated with OOK, BFSK, and DBPSK modulation schemes. Fig. 19(b) presents the output waveform of the ILO when the OOK-modulated input signal is applied to the receiver. As explained in Section III-D, the amplitude variations of the OOK-modulated input signal are preserved at the ILO output, and thus the amplitude of the ILO output signal varies according to the input baseband data. Fig. 19(c) shows the output waveform of the ILO when the receiver input is the BFSK signal modulated between 2.404 GHz and 2.406 GHz with the frequency deviation of 2 MHz. The frequencyto-amplitude conversion characteristic of the ILO generates the variations in the amplitude of the ILO output signal corresponding to the input baseband data. The ILO output waveform for the DBPSK-modulated input signal is shown in Fig. 19(d). When the phase of the input signal changes, the ILO is perturbed from its injection-locked state, resulting in the instantaneous change of the ILO output amplitude. After the transient amplitude fluctuation, the ILO turns back to the injection-locked state, and its original output amplitude is recovered. It is found that the ILO output waveform presents an RZ signal characteristic as explained in Section III-C, and therefore the input baseband data can be recovered by converting the RZ signal to the NRZ data. From the results shown in Fig. 19, it is verified that the OOK/BFSK/DBPSKmodulated input signal can be converted to the amplitudemodulated output signal by the ILO operation, which enables the energy-efficient ED-based receiver structure.
As illustrated in Fig. 2, the ILO output is fed to the ED to generate the baseband signal capturing the variations in the amplitude envelope of the ILO output, and the ED output is amplified by the BB AMP. The amplified baseband signal is processed by the comparator to produce the output bit stream. Note that the output of the ED is AC-coupled to the input of the BB AMP. When the receiver input signal is OOK-or BFSK-modulated, the comparator output can directly be used as the demodulated output data. In the case of the DBPSKmodulated input signal, the comparator output needs to go through the conversion process from the RZ data to the NRZ data to produce the demodulated output. Fig. 20 presents the demodulated output of the receiver, which is consistent with the input baseband data shown in Fig. 19(a). This result verifies that the proposed receiver can process the modulated RF input signal properly to generate the correct and accurate output data.
When the RF input signal is BFSK-modulated, as shown in Fig. 2 and discussed in Section III-B, the peak detector is used to regulate the strength of the ILO injection signal so that the frequency-to-amplitude conversion performance of the ILO can be maintained reliably. The peak detector provides the amplitude information of the baseband signal to the MCU through the analog-to-digital converter (ADC) interface of the MCU, and the MCU generates an appropriate DC voltage (V CTRL in Fig. 11) through its DAC output to control the SDA  gain, forming the closed regulation loop. In the proposed receiver, the amplitude of the ILO injection signal is kept constant at -45 dBm to obtain the lock range of about 2 MHz consistently, leading to an optimal frequency-to-amplitude conversion ratio. As shown in Fig. 21, when the receiver input power changes from -90 dBm to -45 dBm, the peak detector generates the corresponding output voltage varying from 440 mV to 560 mV, and this information is processed by the external MCU to control the SDA gain from 45 dB to   0 dB. As a result, the ILO injection strength is regulated to -45 dBm for the wide range of the receiver input power. Fig. 22 shows the ILO output waveform for different levels of the receiver input power when the closed-loop SDA gain control function is disabled, and the combined gain of the Pre-AMP and SDA is fixed at 25 dB. As shown in Fig. 22(a), if the RF input signal is FSK-modulated with the frequency deviation of 2 MHz and its power level is -70 dBm, the ILO output exhibits a sufficiently large amplitude variation of 8 mV. However, as the power of the input signal increases, the frequency-to-amplitude conversion ratio degrades greatly, as shown in Fig. 22(b) and (c). This result demonstrates the importance of regulating the power of the ILO injection signal through the closed-loop gain control.  Fig. 23 plots the bit-error-rate (BER) test results performed at the data rate of 50 kb/s with varying the receiver input power. It is found that the proposed receiver achieves the sensitivity of -87, -85, and -82 dBm when the input is modulated with OOK, BFSK, and DBPSK schemes respectively for the data rate of 50 kb/s and BER of 10 −3 . The signal-tointerference ratio (SIR) performance measured for the interferer near the 2.4-GHz ISM band is presented in Fig. 24. For this SIR measurement, the data rate is set to 50 kb/s, and the input signal power is adjusted to be 6-dB higher than the sensitivity limit of the receiver. The measurement is repeated for different modulation schemes. The SIR measurement result indicates the power level of the interferer that the receiver can withstand. Typically, the ILO-based receiver is vulnerable to the blocker because the ILO can be locked erroneously to the interferer. However, as shown in Fig. 24, the proposed receiver can mitigate this issue significantly by employing the Q-enhanced SDA with the narrow-band amplification characteristic. The measurement results verify that the receiver can distinguish the input signal from the accompanying interferer, exhibiting good selectivity performance.
The power breakdown of the receiver is shown in Table 1. The total power consumption is 324 µW when operated with the supply voltage of 1 V. The most of power is consumed by the Pre-AMP, SDA, buffer, and ILO, while the consumption by the ED, BB AMP, comparator, and peak detector is nearly negligible. Table 2 summarizes the key performances of the proposed receiver and compares them with those of other recent low-power receivers. The receiver presented in this work exhibits competitive performances when compared with other designs. Especially, the proposed receiver can operate with multiple modulation schemes and improves the previous injection-locking-based receiver [8] in that the strength of the injection signal to the ILO is controlled in a closedloop manner, guaranteeing consistently good performances over a wide range of the receiver input power. Note that the presented receiver IC has been fabricated using a 180-nm technology and operates at 2.4 GHz with 1-V supply voltage, while the other designs in comparison were fabricated in more advanced process technologies except [8], operates at lower frequencies except [6] and [19], and powered by lower supply voltages.

VI. CONCLUSION
An energy-efficient multi-mode receiver that operates in the 2.4-GHz ISM band is presented for use in the wireless sensor node under various IoT application scenarios. The ILO is at the core of the receiver structure, and its inherent injectionlocking characteristic is exploited to convert the amplitude, frequency, and phase variations of the OOK, BFSK, and DBPSK input signals respectively to the amplitude fluctuations at the ILO output. After this conversion process, a simple envelope detection follows to extract the amplitude variations of the ILO output envelope as well as to downconvert the signal to the baseband. Consequently, the use of the mixer and the frequency synthesizer can be excluded to minimize the power consumption.
Importantly, the proposed receiver implements the closedloop control of the ILO injection signal power, unlike the previous ILO-based FSK receiver. The control loop operates by adjusting the Q-enhanced SDA gain according to the baseband signal power monitored by the peak detector. Without this loop, as the receiver input power increases, the ILO lock range becomes wider, and the frequency-to-amplitude conversion performance degrades, leading to the demodulation failure eventually.
In the RF front-end, the Pre-AMP and Q-enhanced SDA are employed to provide a sufficiently large differential injection signal to the ILO even when the RF input power is low, which improves the receiver sensitivity significantly.
In addition, the receiver selectivity is also improved due to the narrow-band amplification characteristic of the Q-enhanced SDA.
When fabricated in 0.18-µm CMOS technology, the proposed receiver achieves the sensitivity of -87, -85, and -82 dBm for the OOK, BFSK, and DBPSK signals respectively at the data rate of 50 kb/s and the BER lower than 0.1% while consuming 324 µW from the 1-V supply. tems Laboratory, IME, as a Department Head. In IME, he led various projects developing low-power 3D accelerometer ASICs for high-end medical motion sensing applications, readout ASICs for nanowire biosensor arrays detecting DNA/RNA and protein biomarkers for point-of-care diagnostics, ultra-lowpower sensor node SoCs for continuous real-time wireless health monitoring, and wireless implantable sensor ASICs for medical devices, as well as low-power radio SoCs and MEMS interface/control SoCs for consumer electronics and industrial applications. He was also a Program Director of NeuroDevices Program under A * STAR Science and Engineering Research Council (SERC), from 2011 to 2013, and an Adjunct Assistant Professor with the Department of Electrical and Computer Engineering, National University of Singapore (NUS), from 2010 to 2013. He was an Associate Professor with the Department of Information and Communication Engineering, Daegu Gyenogbuk Institute of Science and Technology (DGIST), South Korea, from 2014 to 2015. Since 2016, he has been an Associate Professor with the School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), South Korea. He is an author of five book chapters and has more than 290 peer-reviewed international conference and journal publications in the areas of sensor interface IC, wireless IC, biomedical microsystem, 3D IC, and device modeling and nanoelectronics. He also has more than 50 patents issued or filed. He has served on the Technical Program Committee and Organizing Committee for various international conferences, symposiums and workshops, including IEEE International Solid-State Circuits Conference (ISSCC), IEEE Asian Solid-State Circuits Conference (A-SSCC) and IEEE Symposium on VLSI Circuits (SOVC). He is also working as a Distinguished Lecturer of IEEE Circuits and Systems Society. His main research areas are advanced IC platform development, including smart sensor interface ICs and ultralow-power wireless communication ICs, as well as microsystem integration leveraging the advanced IC platform for emerging applications such as intelligent miniature biomedical devices, ubiquitous wireless sensor nodes, and future mobile devices. VOLUME 8, 2020