A New Topology of Switched-Capacitor Multilevel Inverter With Eliminating Leakage Current

This paper proposes a new topology of the switched-capacitor multilevel inverter (SCMLI) for photovoltaics system, which can eliminate the leakage current. In the proposed topology, the capacitors are employed as a virtual DC power supply to boost the input voltage. Here, all capacitors are charging equal to DC source, thus, just one DC source is needed to achieve the staircase waveform. In this structure in order to make the negative levels, the capacitors are connected to the output in reverse polarity. Thus, the H-bridge circuit which is used in traditional SCMLI to build zero and negative voltage levels and leads a variable common mode voltage is removed. Due to the direct connection of the neutral terminal of the grid to the negative polarity of the PV; then this topology can eliminate the leakage current. In addition, the topology has an excellent ability to path the reverse current as well as an acceptable output waveform spectrum. The operating states of all components and loss calculations are analyzed and formulated accurately as well as simulated by using MATLAB-SIMULINK software. To confirm the performance of the proposed topology; a 500 W prototype is built and experimental results are presented.


I. INTRODUCTION
Nowadays, many solar energy users tend to inject their surplus energy into the grid. The grid-connected photovoltaic systems can be divided into two different categories, with transformer and transformerless systems. For the systems with transformer, there is galvanic isolation between PV panel and grid. However, it leads to increase of cost, size and loss of power. Thus, transformerless system is a significant advantage to improve the overall system efficiency. One of the fundamental issues in the transformerless grid-connected systems is the negative effect of the leakage current due to the parasitic capacitor between the PV panels and the ground [1], [2].
Multilevel voltage source inverters (MLVSIs) have emerged as a popular solution to inject renewable energy sources, such as wind turbines, photovoltaic cells as well as into electric vehicles (EVs), advanced adjustable speed The associate editor coordinating the review of this manuscript and approving it for publication was Zhilei Yao . drives and different new power electrical applications [3], [4]. This category of converters can reduce the voltage stresses on the switches and decrease the electromagnetic interference (EMI) by generating a staircase voltage waveform, increase the voltage level numbers. In addition, the produced staircase waveforms at the output could decrease the total harmonic distortion (THD). Thus, to achieve acceptable THD, they need a smaller size output filter, which in turn, will decrease the size of inverters [5], [6]. The switched-capacitor multilevel inverters (SCMLIs) has the ability to boost the input voltage. In addition, they can create multilevel staircase waveform at the output, which eliminates the need for a large filter [5], [7]- [15]. Some conventional SCMLI's are illustrated in Fig. 1. The basic structure of a single-phase grid-connected inverter and the CM current path are shown in Fig. 2(a), where P and N indicate positive and negative polarity of the PV panel respectively. In this case, Z G and C PV refer to the ground impedance and the parasitic capacitance between the PV array and the ground. This CM voltage and the caused leakage current may lead to safety threats and VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ reduce the efficiency as well as increase the grid current distortion [16]- [18]. Fig. 2(b) illustrates the facilitated equivalent scheme of the CM resonant current. The CM voltage is given by: where v AN and v BN refer to the voltage difference between terminal A and B, the output of the inverter, in comparison with the neutral point of the PV cell. It is evident that by keeping the common mode voltage constant, the leakage current can be reduced. To achieve this, in the structure of fullbridge inverters such as H5 inverter [19], H6 inverter [17], HERIC inverter [20], etc., two inductors having identical values (L 1 = L 2 ) are used as the output filter. Thus, the equation of common mode voltage will be simplified as follows: In this solution, the output filter structure consists of two inductors with two separate cores, which increase the size and cost. Using half-bridge family inverters, such as neutral point clamped (NPC) inverters [21], is another way to keep the common mode voltage constant. It will eliminate one of the inductors (or is equal zero), so only one inductor is utilized as an output filter. In this case, the relationship of the common mode voltage is defined as: The requirement of the double DC bus voltage is one of the drawbacks of this design when compared to the full-bridge structures. Fig. 3 shows topologies of the grid-connected inverter based on full-bridge and half-bridge power converter structures. On the other hand, all conventional switchedcapacitor inverters suffer from the H-Bridge circuit to build negative polarity voltage levels at the output, which leads to a variable common mode voltage and thereby generating leakage current. Thus, it requires extra circuitry elements to obtain the constant CMV [22], [23].
Using a common ground (CG) is one of the effective methods to eliminate the leakage current. For this purpose, the negative terminal of the PV panel is directly connected to the neutral line of the grid, which ensures that the common mode voltage is stabilized and thus eliminates the leakage current [16] and [24]- [26]. In recent years some modified switched-capacitor inverters, as shown in Fig. 4, have used this solution to cancel the leakage current. Generally, for three-level inverters, if the capacitor does not connect in parallel with the voltage source at two consecutive levels, the voltage variations of the capacitor will increase considerably. Fig. 4(a) illustrates an inverter structure, which uses this technique and include of five power switches [16]. In this FIGURE 1. Switched-capacitor multilevel inverter topologies: (a) series-parallel SCMLI proposed in [10], (b) cascade SCMLI [13], (c) step-up SCMLI in [14], (d) SCMLI for pure resistance load [7].  Full-bridge and Half-bridge topologies for grid-connected transformerless inverters: (a) H5 inverter [19], (b) HERIC inverter [20], (c) H6 inverter with DC bypass [17], (d) NPC half-bridge inverter [21]. topology, the capacitor at zero and +V DC levels goes in parallel with the source. Meanwhile, due to the circuit structure and the use of conventional switches, which also can flow the reverse current, it has the capability to be utilized as a reactive load. The flying capacitor transformerless inverter as shown  [16], (b) Flying Capacitor CG Inverter proposed in [24], (c) Charge Pump CG Inverter proposed in [25] (d) Siwakoti-H inverter [26].
in Fig. 4(b) has reduced the number of controllable elements of the topology [24]. In this structure, there are two paths to charge the capacitor, while it makes +VDC and negative zero levels in output. However, for the inductive load, the current of the inductor cannot change quickly. Thus, the capacitor is in the path across the load and the current passes within the capacitor whilst the output is switching to positive zero level and then increases its voltage. Therefore, in re-switching to +V DC level, the capacitor cannot be tuned by DC source. In addition, at the negative level, as long as there is the reverse current, it will path through the capacitor (depending on the power factor), thus, the voltage variation of the capacitor raises. Fig. 4(c) shows the charge-pump topology which is proposed to resolve the abovementioned problem [25]. In this design, the capacitor that produces the negative output voltage level sets to the input source at the zero level, and the issue of increased voltage variation, is eliminated. Meanwhile, another path is considered for the reverse current. Thus, the reverse current does not pass through the capacitor. Siwakoti-H inverter topology [26], which is shown in Fig. 4(d), only consists of four switches and uses the lowest power semiconductor devices in comparison with other presented topologies. However, in the reactive power, there are the same problems as the flying capacitor inverter introduced in Fig. 4(b). At the positive cycle, the capacitor cannot regulate by the DC source. Moreover, at the negative cycle, it has reverse current. Thus, the circuit suffers from the increasing of capacitor voltage variation. Moreover, all the inverter structures mentioned above are only able to produce three-level output waveform. Therefore, boost circuit has to be added.
By considering the above-mentioned problems, this paper presents a novel switched-capacitor multilevel inverter topology, which has the potential to boost voltage as well as to eliminate the leakage current. The basic unit of the proposed topology contains four power switches and one capacitor. In summary, the advantages of the proposed topology and circuit characteristics can be described as follows.
(1) The proposed circuit only needs one input voltage source.
Thus, the need for the boost circuit, which increases the size and costs, has been eliminated. (2) According to the symmetric structure in the proposed topology, each additional capacitor can be charged equal to the input voltage. Thus, two voltage levels can be achieved at the output and increases the maximum output voltage. (3) In conventional SCMLIs, the H-bridge circuit is used to generate negative output levels. It will make a variable common mode voltage and thus lead to the leakage current. In the proposed SCMLI, direct connection of the neutral point of the grid to the negative polarity of PV panels leads to the formation of common ground in the circuit. Therefore, the leakage current is zero. On the other hand, the proposed inverter is the first MLI topology which can eliminate the leakage current. (4) Some new equations by high accuracy are presented in this paper to calculate the switching losses, conduction losses and losses caused by the voltage drop of the capacitors (ESR). The following sections organize this paper. The basic unit concept of the proposed inverter is described in Section 2. Based on that, a novel general topology is acquired, and the reason to choose unidirectional switches are explained. In section 3, the topology of a 5-level and a 9-level inverter are analyzed, which are derived from advanced general topology. In addition, the modulation strategy and operation states of switches and capacitors are described in detail. The voltage drop analysis of capacitors and calculation of the power loss have been given in Section 4. A comparison with other topologies have been done in Section 5 to prove the performance of the proposed circuit. The simulation and experimental results are shown in section 6 to confirm the validity of the proposed inverter.

II. PROPOSED CONCEPT
A. BASIC CIRCUIT Fig. 5 illustrates the basic circuit of the proposed SCML inverter. It should be noted that S a includes two groups of unidirectional switches. According to Fig. 5, the capacitors C 1 and C 2 are charging equally the DC source when the group of the switches S a , S 1 and S 2 become ON and the other switches are OFF. In this state, the positive and negative polarity of C 1 and C 2 are connected to each other respectively, and two capacitors are in parallel. Another VOLUME 8, 2020 Condition happens when S b becomes ON, and other switches are OFF. Here, the positive polarity of C 1 is connected to the negative polarity of C 2 . In this situation, if S 3 and S 2 become ON, the capacitors C 1 and C 2 will be in series to the load and generate a higher positive level in the output. In the last state, if S c along with S 2 becomes ON (other switches of the unit were OFF), the negative polarity of C 1 is connected to the positive polarity of C 2 and if S 4 was ON, thus, the stored voltage in the capacitor C 2 is pumped to the output in reverse polarity. In fact, during the generation of positive and negative output voltage levels, S 3 and S 4 become ON respectively. In this structure, the DC power supply does not have a direct role to generate negative output levels. However, if the switch S 5 becomes ON, the DC source will be series with the capacitor; thus, it can make an extra positive output level rather to the negative levels. This state disturbs the symmetrical output waveforms. Thus, the switch S 5 is eliminated in order to prevent this state.

B. PROPOSED GENERAL SCMLI TOPOLOGY
Based on the primary unit presented in Fig. 5 a general topology of the multi-level inverter is shown in Fig. 6. According to this structure, to reach the higher voltage levels and increase the output voltage, it is enough to connect k basic unit in series. Each basic unit consists of four power switches and one capacitor. If the number of output voltage levels assumed to be n, then the number of capacitors, which is applied to build a multilevel inverter as well as the number of required power switches and the maximum output voltage are as follows:

III. PROPOSED TOPOLOGY AND MODULATION METHOD A. PROPOSED 5-LEVEL AND 9-LEVEL SCMLI
According to the proposed generalized structure, the topology of the 5-level inverter, which comprises of one input voltage source, two capacitors, nine switches (seven ordinary switches and two unidirectional switches), is shown in Fig. 7 (a). In this case, unidirectional switches are utilized to charge the capacitors, which are located in higher stages, and when these kinds of switches are ON, the switches of S b and S c group will be OFF. On the other hand, it is noteworthy that the switches of S a group make the capacitors charging path. The switches of S b group make a series the capacitors with positive polarity. Moreover, while the S c category switches are turning ON, the capacitors will be series with negative polarity to generate the negative levels. To confirm the functionality of proposed circuit in generating more output voltage levels and comparing with the similar structures in terms of the number of output levels, the 9-level structure of the inverter based on the proposed topology is introduced and   analyzed, as shown in Fig. 7 (b). On the other hand, the states of the switches and capacitors in the 5-level is similar to the state of the switches in the 9-level circuit to make the same output levels, so the analysis of the 9-level inverter also includes the function of the switches in the 5-level inverter.

B. START-UP MODE
In the proposed switched-capacitor inverter in order to form the zero level, all S a group switches (unidirectional switches) are ON, and all capacitors are charging as much as the input voltage source. In this case, the switches S 3 and S 4 are OFF and ON respectively as shown in Fig.8. Fig. 9 and Fig.10 show the different switching states and the current flow path of the proposed 9-level inverter. Regarding the use of unidirectional switches in the circuit, there are two paths for forward and reverse current in the loop. The direction of the reverse flow caused by the inductive load marked in blue and the path of the working states of the inverter to determine the output voltage levels, as well as the charging path of the capacitors, are specified in red line. In addition, from this figure the different status of the capacitors in terms of charging/discharging are apparent. As it can be seen, the switches of the S c group connect the capacitor to the output in reverse polarity to generate the negative output levels, and thus the need of H-bridge is eliminated.
When the +V DC level is forming, all S a switches are still ON and only the switches S 3 and S 4 varies mode, and the voltage source directly generates the +V DC level as shown in Fig. 9(a). In this situation, all capacitors are in charging mode same as the zero voltage level. To make the +2V DC level, S a5 and S a6 are switched OFF and switch S b3 turned ON to pump the capacitor C4 in series with the voltage supply to the output load. Here, the capacitor C 4 is in the discharge mode, and other capacitors (C 1 , C 2 and C 3 ) are charged by the DC power supply simultaneously ( Fig.9 (b)). In the same way, other voltage levels will be created. To form each positive level, the capacitor of the related unit by the switch Sb is connected in series with the voltage source to the output load and the other switches of the unit turn OFF. It should be noted that the capacitor C 1 in all states of the production of positive levels is in parallel to the voltage source and is charging, thus it has no role in the creation of positive levels as shown in fig. 9. In the production of negative output levels, the switch S c of each unit has illuminated to connect the capacitor of the unit with reverse polarity to the output. To build the first negative voltage level, the stored voltage of the capacitor C 4 is pumped through the switch S c1 . In this case, the other capacitors are in charging mode simultaneously as shown in Fig.10 (a). As it can be seen in Fig. 10(b) the capacitors C 3 and C 4 via the switches S c3 , S c4 and S 4 are series connected to the output to generate −2V DC level. In this term, the switches S a2 and S 2 are ON. Continuing this process makes −3V DC level (Fig. 10(c)). To create −4V DC level, all switches in the S c group (S c1 , S c2 , S c3 and S c4 ) with S 4 become ON and other switches are OFF as shown in (Fig. 10(d)). In this state, all capacitors are in discharging mode. Fig. 11 shows the modulation strategy and the corresponding control pulses of each switch in the proposed 9-level inverter. In this term, by utilizing a carrier-based level-shifted SPWM (LSSPWM) technique, the gate driver pulses are created. Based on this figure, four triangular carrier waveforms where the amplitude of all carries are the same and equal to A c , with similar frequency (fs = 10 kHz) are compared with a completed sinusoidal reference signal by the magnitude corresponding to A r and frequency of 50 Hz. In this case, to produce switching control pulses in the negative cycle of the absolute amount of the reference signal is compared with the carrier. Therefore, the modulation index M is obtained from the following equation: Table 1 demonstrates the ON switches at various levels in proposed the 9-level inverter. Additionally, the operation of each capacitor at various levels are further shown in Table 1.

V. CALCULATION OF VOLTAGE DROP OF THE CAPACITORS, LOSSES, AND EFFICIENCY
One of the critical parameters in the design and analysis of power electronics circuits is the calculation of power dissipation. The accuracy of the estimate of this characteristic of the circuit in the technical evaluation and the application of the circuit and thus the final cost has a significant impact. The power losses in the proposed circuit consists of three categories. Power losses due to capacitor voltage drop, switching losses and conduction losses.

A. VOLTAGE DROP AND LOSSES OF CAPACITORS
In the proposed SCMLI, the capacitor will be parallel with the source during a time interval and charged equal to the input voltage while the group switches are ON. Then, to build up higher output levels, the stored energy in the capacitor is pumped to the output in series, which leads to decrease the voltage of the capacitor. On the other hand, due to the series connection of the capacitor with the output load at the discharging time, a voltage drop on the capacitor is created which leads to generating the power losses. Here, the charging and discharging of the capacitor by the switching frequency leads to making small, but large quantities of voltage drop.
In the intervals, where the capacitor is continuously connected to the output in series, this causes large voltage drop and effective power losses in comparison with the small voltage drop. According to Table 1, during two consecutive level ±n and ±(n + 1), when the capacitor is in discharging mode; thus, it has an effective voltage drop. This voltage drop leads to generating power dissipation. On the other hand, when the capacitor is discharging continuously (at least in two levels that are sequential), the large voltage drop will have happened. While the capacitor is in charge/discharge mode by switching frequency, the caused voltage drop by this condition is low. Table 2 shows the effectual charge / discharge modes of the capacitors for the 9-level proposed inverter [27]. The determination of the time interval for various output levels in one-half cycle is shown in Fig. 12.
Based on this pattern, in each time interval, the reference wave is compared to the respective carrier to generate various output levels. Following equations represent t i and t i [27].
t n = T 4 , θ n = π 2 (13) where i is equal to 1, 2, . . . , n and θ i represents the corresponding angle to i. The voltage drop of the capacitor is obtained by: The current waveform among to the pure resistive load is the same as the staircase voltage waveform, which leads to complicated calculations of the voltage drop. Thus, by an accurate assumption, the current is obtained as follows: Due to Table 1 and Table 2 , it is obtained that the operation states of capacitors in positive and negative cycles are different. Therefore, the voltage drop of the capacitors for each cycle is derived from the following equations: The total energy differences before and after the parallelization of the capacitors determine their energy dissipation. This energy is lost in the circuit as a form of the spike, which can be calculated from the following equations.
Due to the equation E Loss(C i ) = C i V 2 i /2 and with considering (21), the equation of energy loss is summarized as follows: By simplifying the above equations, the energy losses due to the voltage drop of the capacitor are expressed as follows: Thus, by concerning the previous equations, and modelling the DC power supply with the capacitor, which has infinity capacitance, and zero voltage drop, the losses due to the parallelization of the capacitors with the voltage source are obtained from the following equation.
where f L is the output frequency. Notwithstanding a large number of small spikes (which happened due to parallelization of the capacitor with the voltage source at the switching frequency), their voltage variations are negligible. Therefore, it is possible to ignore the losses of these spikes compared to large spikes.

B. SWITCHING LOSS
The output current path for different voltage levels (positive, zero and negative), and the ON switches in this flow path as well as ON switches on the charge path of the capacitors are shown in Fig. 8. In the zero levels, the current flow to the output via the switches S 1 , S a1 , S a3 , S a5 and S 4 . Likewise, the ON switches can be found on the output current path for other levels. While the output voltage is changing from zero to the positive level (+V DC ), only two switches change (S 3 turns ON, and S 4 turns OFF). In generating different positive levels always, one unidirectional switch from S a group turns OFF and one traditional switch from S b group turns ON. The switch S 4 during the time interval of generating zero level and the whole time interval of negative levels turns ON. In the formation of negative levels, at each stage, one unidirectional switch is turned OFF, and one traditional switch from S c group goes ON. Thus, the switching losses due to considering the state of switches in each level are calculated as follows [28].
where E SW (on) and E SW (off ) represent the turn-on and turnoff energy loss respectively that can be achieved from the datasheet. Because in multilevel inverters, most switches are not switching during the whole of the period; therefore, in calculating the switching losses, only the active switching times of each switch are used. The correction factor for switching losses is the ratio of the effective switching time of each switch to the whole period, which can be derived as follows: Here D S(i,i+1) is the ratio of time while the output waveform is switching between two levels i and (i+1) to the whole period.

C. CONDUCTION LOSS
In other studies, in the calculation the conduction losses it is assumed that the switch is used to conduct during the whole period. However, the switch conducts only in the part of the period. Therefore, accurate calculation of conductive losses, especially in the SPWM modulation method, requires correction coefficient. This coefficient represented the ratio of the activation of the levels over the whole of the period and indicated by DC. Therefore, the conduction losses can be derived by follow: where D Ci and t Li represent the correction coefficient and activation time in level i respectively. While the output waveform is switching between two levels i and (i−1), S i indicates the ratio of the time, which the output is on level i to the whole time interval.

VI. COMPARISON DISCUSSION
A comparison of the proposed inverter concerning the number of semiconductor devices, output levels, ability to be extended, the capability to eliminate the leakage current as well as boosting the input voltage and the efficiency are listed in Table 3 . It should be noted that there is no the same condition in comparison Table. Because this comparison contains some traditional SCMLIs which can boost the voltage and make more than three levels at the output but, cannot eliminate the leakage current and, some other threelevel inverters, which can eliminate the leakage current but suffer from needing to boost circuit and cannot be extendible. Therefore, the proposed circuit is the first SCMLI, which can eliminate the leakage current and can be easily extendible.
Only by adding four switches and one capacitor can be achieved two more voltage levels at the output. As can be seen in Table 3 , in the proposed inverter, for each basic unit, four power switches further are required, which compared to the proposed inverter in [14] it has an optimal number of switches and only is more than the number of the switches used in the technology proposed in [10] (one switch further per unit). On the other hand, in comparison with other SCMLIs that have the potential to boost the voltage, only the proposed topology can eliminate the leakage current, and other SCMLIs suffer from this issue. In addition, the topologies introduced in Table 3 which can eliminate the leakage current [23]- [26] are not capable to increase the voltage and required boost circuitry. The proposed inverter, unlike traditional SCMLIs, does not need to H-bridge circuit. In this case, similar to the inverters mentioned in [23]- [26], to create the negative levels, the capacitor with reverse polarity is connected to the output. Due to the multilevel waveform at the output of the proposed inverter, the output waveform compared to the suggested topologies in [23]- [26] is qualitative. Thus, the THD of the proposed inverter is less than them.

A. SIMULATION RESULTS
This section presents several simulation results for the proposed 9-level, and 5-level derived inverters by utilizing MAT-LAB/SIMULINK software. In this case, all semiconductor devices are assumed with internal resistance R on = 0.1 . The switches are driven based on the proposed modulation strategy with a switching frequency f SW = 10 kHz and the modulation index M = 0.85. Table 4 gives the parameters  TABLE 3. Comparison of the proposed topology with suggested topologies of [10], [11], [14], [23], [24], [25] and [26].  that are applied for the simulation of the proposed topologies. The output voltage and current waveforms of the 9-level and 5-level inverter for pure resistive R Load = 100 with a line frequency equal to 50 Hz are shown in Fig. 14 and Fig. 15 respectively.
According to the proposed method, the maximum values of output voltage and current waveform (peak value) are equal to 366 V and 3.66 A, respectively. Fig.16 and Fig. 17 show the output waveform of these two structures by considering Inductive-Resistive load (R-L), which R Load = 90 and L Load = 140 mH (cosϕ = 0.9). The THD of the output waveform without having a filter for inductive-resistive load (cosϕ = 0.9) are 18% and 36.4% for 9-level and 5-level inverter respectively as shown in Fig. 18.   The dynamic performance of step load for the output voltage/current waveforms and the voltage of the capacitors for changing the load from (90 + 140 mH) to (45 + 70 mH) and vice versa is shown in Fig. 19. It has been represented that the proposed inverter can track step change when the output power is decreased from 1000 W to 500 W (or increased from 500 W to 1000 W). As it can be seen, this test demonstrates the effectiveness of the power control strategy used in this paper in terms of fast response. Fig. 20 and 21 show the voltage variation across the capacitors in the proposed 9-level and 5-level inverter respectively. In this case, the voltages of capacitors are simulated two times. Fig. 20 (a) and Fig. 21 (a) represent the voltage variation of the capacitors for the R-L load with cosϕ = 0.9. Fig. 20 (b) . and Fig. 21 (b) show the voltage variation of the capacitors for pure resistive load cosϕ = 1 (R Load = 100 ).
In this structure, due to, the capacitor of upper unit (C i ) compared with the capacitor in down unit (C i−1 ), will be series connected with the DC source in large time. Thus, it has a higher voltage drop when the output is at the peak value. It is necessary to mention that, the capacitor C 1 in generating all states except −4V DC in the 9-level inverter and −2V DC at 5-level is in parallel with the DC source. In addition, in generating these levels, this capacitor is charged and discharged with the switching frequency. Therefore, there is no significant voltage drop. In respect to (18) and (19), in the 5-level proposed inverter, the voltage drop of capacitor C 1 does have a small, while the capacitor C 2 has a large voltage drop for the negative half-cycle, which results in a   According to the (24) and (25), the losses due to the voltage drop across the capacitors in the 5-level inverter obtained 6.5 W. Based on (26) and (27), switching losses for 5-level propose inverter calculated by following equations: where E RR refers to the reverse recovery energy of the diode. Therefore, switching losses of all switches in the proposed inverter can be derived as follow: Due to (27)(28)(29)(30)) the conduction losses of each switch is obtained from the following equations: Therefore, the conduction losses of all switches in the proposed inverter can be derived as follow: Finally, the following equation can represent the efficiency of the proposed SCMLI: From (53) for 5-level proposed inverter the efficiency is given 96.7%.

B. EXPERIMENTAL RESULTS
To confirm the feasibility of the proposed topology, a 5-level, 500 W, single-phase inverter has been made and tested to get experimental results. A picture showing the implemented inverter is depicted in Fig. 22. The components and parameters which are listed in Table 5 has been used in the prototype.
The control pulses for IGBTs are generated by the processor (FPGA AX301) based on LSSPWM technique. With an input DC voltage of 183 V, a 5-level waveform, which is boosted to 363 V, is given at output of the inverter.
All switches are working at the same switching frequency of 10 kHz. According to result, the maximum value (peak) of   the output voltage and current waveform (which are in the same phase) are equal to 363 volts (RMS value is 220 V) and 3.6 A, respectively for pure resistive load R = 100 Ohm (cosϕ = 1) as shown in Fig. 23. Fig. 24 shows the output voltage and current waveform for pure resistive load R = 50 Ohm, which leads to generate a maximum value current equal to 7.2 A. The output voltage and current waveforms in R-L load (cosϕ = 0.9) is shown in Fig. 25. The measured   efficiency of the proposed inverter for the purely resistive load is around 96 %. Fig. 26 shows the harmonic spectrum of the output voltage for pure resistors of 100. As it can be seen, the first disturbing harmonic appears at a switching frequency of 10 kHz, and its value is close to the simulated value equal to 14.5%.
The voltage stress across the all switches are shown in Fig. 27-30. According to these diagrams, the voltage stress of two categories of switches, which connect the capacitors in   series is twice as input DC source, and voltage stress on other switches is equal to the input DC voltage. It should be noted that the voltage stress of the switches S b and S c in each unit by extending the proposed structure to generate more output voltage level, always are equal to 2V DC .
As expected, and as it is shown in Fig. 31, the voltage drop of capacitor C 1 is negligible. However, the capacitor C 2 in the negative half cycle is in discharge mode at two consecutive levels (−V DC and −2V DC ), then, the voltage drop is significant, and its value is approximately 16.5 V, which is equal to the calculated value based on the theoretical.

VIII. CONCLUSION
This paper has proposed a new topology of the switchedcapacitor multilevel inverter, which can eliminate the leakage current. The proposed inverter can be extended as n-level SCMLI, and thus, the output waveform has an acceptable quality as well as decrease in the output filter size compared to 3-level inverters which eliminate the leakage current. Traditional SCMLI is based on H-bridge circuit to make zero and negative levels, which suffer from a variable common mode voltage. However, here, the H-bridge circuit is eliminated. In this case, to generate the negative levels, the capacitor pumped the stored energy to the output in reverse polarity. In this circuit, the neutral polarity of the grid is directly connected to the negative point of the PV panels, which leads to make a common ground and eliminate the leakage current. In the proposed topology, a sinusoidal pulsewidth modulation method is employed to self-balance the voltage of all capacitors equal to the DC source. A ninelevel and five-level SCMLI have been analyzed and studied, and the losses, which contain capacitor loss, switching loss, and conduction loss, are all calculated and formulated. The comparison between the proposed topology and other existing circuits shows excellent performance of it in both boosting the voltage and eliminating the leakage current. The 9-level and 5-level structures of the proposed inverter are simulated by MATLAB/SIMULINK software. A 500 W 5level prototype is built, and several experimental results have been presented to confirm the validity the performance of the proposed topology.