CMOS Backplane Pixel Circuit With Leakage and Voltage Drop Compensation for an Micro-LED Display Achieving 5000 PPI or Higher

Micro-displays based on micro-LEDs are becoming more and more attractive in AR/MR (Augmented/Mixed Reality) applications. A display size of 0.5 to 0.7-inch is preferred, with 5,000 PPI (Pixel Per Inch) or higher. Due to this pixel density and size, a CMOS (Complementary Metal-Oxide-Silicon) backplane is an ideal solution to drive these pixelized micro-LEDs. As the required pixel size gets smaller, the design of the appropriate pixel circuit becomes more challenging. The simplest 2T1C (2 transistors & 1 capacitor) pixel circuit has potential problems, due to the leakage current of the switch transistor and the voltage drop on the matrix array layout. In this paper, a pixel circuit is proposed as a solution to overcome these two issues. Our simulation results show that the variation of the driving current to the LED is improved by 95 %, and the IR drop error rate is around 2.2 % compared to the 2T1C circuit. The test results also show that the error rate of IPIXEL for the whole region of display is under 2.5 %. This work is verified using a test chip implementation with 180 nm CMOS process technology.


I. INTRODUCTION
Micro-display technology based on micro-LEDs is still in the early stages of commercial deployment, but it is expected to slowly replace the existing display technologies, such as LCDoS (Liquid Crystal Display on Silicon) or OLEDoS (Organic Light Emitting Diode on Silicon) displays, for certain applications [1]. One of the biggest hurdles for commercializing micro-LED displays is the transfer technology by which the pixelized LEDs are attached to the backplane. Because of this, the following applications are likely to be among the early adopters of these micro-LED displays. The first are micro-display applications for AR/MR (Augmented-/Mixed-Reality), where the silicon CMOS backplane IC and LEDs are hybridized by wafer-to-wafer bonding [2]. The second are super-size display applications, such as outdoor signage or TV screens larger than 110 inch, The associate editor coordinating the review of this manuscript and approving it for publication was Mahmoud Al Ahmad . which cannot be manufactured using the existing glass-based flat panel displays [3]. Fig. 1 shows the requirements for each display application in terms of pixel pitch and their pixel density, or PPI. AR/MR applications require a pixel density of 5,000 PPI or higher for 0.5-to 0.7-inch displays. Thus, recent research has concentrated on these requirements [4], [5].
As shown in Fig. 1, the pixel pitch for AR/MR should be in the range of 2 µm ∼ 5 µm. The display size of the microdisplay is less than 1 inch [6], [7]. For this reason, silicon CMOS process technology is an ideal solution that lets us manufacture a backplane with a smaller pixel size [8] and integrated peripheral circuitry.
Each pixel contains a current-driving circuit in order to drive the micro-LED. The maximum driving current to each LED is in the range of a couple of micro-ampere due to the size of the LED. The brightness of the LED is directly proportional to the driving current. The pixel size required by a certain application confines the freedom of the pixel circuit design.
In general, there are two approaches to driving the LED in such high PPI display applications. The first one, PAM (Pulse Amplitude Modulation), is the analog control of pixel current or voltage in order to adjust gray level. The other is PWM (Pulse Width Modulation), in which the gray level is adjusted by controlling the turn-on time of the LED using a maximum driving current. The PAM scheme is often called ''voltage driving'', since the voltage information is used to control the driving current level to the LED. On the other hand, PWM is often called ''current driving'' or ''digital driving'', since it uses a fixed driving current while controlling the pulse width to adjust the light intensity of the LED.
The PAM driving scheme can easily achieve a higher pixel density, per a given display size, thanks to a relatively simple pixel circuit structure. However, the leakage current at the transistors of the pixel circuit deteriorates the display uniformity. It also requires rather complex peripheral circuitry, which results in higher power consumption. The PWM driving scheme needs higher transistor counts in the pixel circuit compared to the PAM scheme, since it requires combinational logic gates and SRAM (Static Random-Access Memory) cells. However, it has the advantage of using a simpler peripheral circuitry with less power consumption. This paper proposes a CMOS backplane based on a PAM-based pixel circuit, along with a solution to the leakage current and IR drop problems. A display resolution of 1280RGB x 768 is used to verify the proposed backplane. The driving current to each micro-LED is limited to a maximum of 2 µA after consideration of the total power consumption of the display module.

II. 2T1C PIXEL CIRCIUT A. 2T1C CIRCUIT
A CMOS backplane contains two main function blocks: an active-matrix pixel array, and its peripheral circuit to drive the pixel array. All these functions are included on a single silicon backplane [9]. The pixel circuit stores the display data in a voltage form and converts it into a current form to drive the LED, while maintaining its value during a given frame time (T FRAME ).
The simplest pixel circuit is a 2T1C structure, as shown in Fig. 2 [10], [11]. Micro-LEDs can be configured by either  common-cathode or common-anode topology. The pixel circuit consists of only three components: a switch transistor (M SW ), a driving transistor (M DRV ), and a storage capacitor (C DATA ). The basic operation is as follows: when M SW is turned on by V SCAN , the value of V DATA is stored at C DATA , which sets the V GS bias of M DRV . Then, the voltage level stored at C DATA is converted by M DRV to the amount of current going to an LED (I LED ), which consequently controls the light intensity. Even after M SW is off, its current level is kept by the charge stored at C DATA . Therefore, maintaining the charge during a given frame time is critical to ensuring the consistent light intensity of the LEDs.
A typical display for an AR/MR application requires grayscale with at least 8-bit or 256 gray levels of a color. The driving current, I LED , is proportional to the light intensity of an LED. It often has a non-linear relationship to the gray scale input, as shown in Fig. 3(a). A typical display uses a specific value of the gamma correction value, γ = 2.2. I LED is determined by [12] where α is I MAX /255 γ , and G is the grayscale input with 256 gray levels. I LED has different values depending on the subthreshold and saturation region of M DRV , as shown below: [13] I LED,SUB = ηe where η is a scale factor [14], S is the subthreshold swing of the transistor, k is the process transconductance parameter, and V TH is the threshold voltage of M DRV . Assuming that the switch transistor is ideal, (1), (2), and (3) produce the relationship between V DATA and G as With a typical gamma correction value of γ = 2.2, the V DATA,SUB has a logarithmic relationship to G, and the V DATA,SAT is proportional to G 1.1 , as shown in (4), (5) and Fig. 3 Assuming the maximum voltage of the V DATA is 1.8 V, the step size of V DATA for the gray scale at the lower gray region is around 162 mV. However, in the higher grayscale region it would be as small as 1.4 mV. This means that the grayscale of the LED light will be affected by just a few mili-volt difference in the V GS value of M DRV . On the other hand, the step size of I LED has the opposite tendency, since it is quadratically proportional to the V GS of M DRV . Thus, it has a smaller value in a low grayscale region, and a larger value in a high grayscale region. Table 1 shows the minimum step size of those parameters in each grayscale region. The mismatch problem becomes critical, regardless of whether grayscale is in the low or high region.

TABLE 1. Gamma
Step size of V DATA and I LED assuming maximum The mismatch among pixel circuits of the array would severely affect the uniformity of the display. Thus, it is necessary to minimize the mismatch between the V DATA among the pixel circuits.

B. THE PROBLEM OF THE 2T1C CIRCUIT
There are many variations on the basic 2T1C circuit to improve the performance of the pixel circuit [15], [16]. The V GS bias of M DRV in the 2T1C circuit should be maintained during a given frame time (T FRAME ) to display the target gray scale. Therefore, the amount of charge at C DATA should not be changed during a given frame time. However, leakage current affects the amount of charge at the storage capacitor. This becomes worse when there is limited space for the storage capacitor due to the allowable pixel size. Therefore, a compensation technique for the leakage current must be considered. Fig. 4 shows a model of a switch transistor, including its leakage current. The leakage current, I LEAK , can be expressed as where I OFF represents the off-current through the channel under the gate of the switch transistor, and I D_REV is the reverse-bias current of the parasitic diode of the switch transistor. I LEAK is represented as a summation of I OFF and I D_REV , which can be expressed as below [13]: where V D _ REV is the applied reverse bias [17]. Equation (7) shows I OFF at V GS = 0 [14], which is a function of V TH . Fig. 5 shows the leakage current behavior based on the bias parameter. According to (7) and (8), I OFF increases as the V TH of the switch transistor decreases, while I D_REV decreases as the V BD , the body-drain voltage, decreases. I D_REV cannot be controlled by design because V GATE , the drain of the switch transistor, is always set by the image data value. Therefore, only I OFF can be controlled by the design parameters. It can be found using the following: where V TH 0 is the intrinsic threshold voltage of a transistor, V DS is the applied drain-source bias, L is the drawn gate length, and l d is the minimum gate length. It is shown in Fig. 6.
Equation (9) shows that the V TH of the transistor is dependent on V DS . This phenomenon is called the DIBL (Drain-Induced-Barrier-Lowering) effect [18]. When the finer CMOS process technology is used, I OFF increases due to the short-channel effect. This means that the smaller the V DS , the smaller the I OFF .
Depending on the bias condition at the source and the drain node of the switch transistor, I LEAK can flow in either direction and then affect the amount of charge at C DATA . This change in the charge amount directly affects not only the V GS bias of the driver transistor, but also the gray scale. Fig. 7 and Table 2 show three cases of the bias condition at the switch transistor. Assuming that I D_REV always flows in the direction of the charging C DATA due to the reverse-biased diode, I LEAK can be categorized into three cases: 1) when V D > V S , I OFF flows in the direction of the discharging C DATA ; 2) when V D ≈ V S , I OFF is almost zero and I LEAK is determined only by I D_REV , (in this case, C DATA is charging); 3) when V S > V D , I OFF flows in the direction of the charging C DATA . This should be considered the worst case. Whatever the case, ideally the change in V GS or | V GS | due to the leakage current would be small enough not to affect the target gray scale during the given frame time. In other words, | V GS | should be less than | V GAMMA |, as in where T FRAME is the frame time of the display, and V GAMMA is the voltage step of a gray scale. | V GAMMA | varies in each of the lines because of the nature of the array driving pattern. The resolution of the V DATA step size is different at the  higher-and lower-gray scale regions. Unfortunately, in a typical 2T1C, | V GS | is greater than | V GAMMA | because of the large leakage current. Fig. 8 shows a linear curve representing the ratio between I LEAK and C DATA . I LEAK should be reduced enough to lower the curve slope, so that the V GAMMA during a given T FRAME is less than the minimum step size of the gamma curve, V GAMMA,LSB in the case of I LEAK 2 . According to (7), the capacitance should be maximized at a given pixel dimension, while minimizing the leakage current. When a smaller pixel dimension is required, there is a tradeoff between the capacitance value and the leakage current.
Another critical problem is the IR drop, caused by the metal routing trace between the reference node for each pixel and the global reference node or I/O pad for the backplane [19]. Due to the layout constraints of the pixel array, the power/reference node for V DATA and V GS does not use the same reference point. As explained earlier, the driving current to an LED is determined by the V GS of M DRV , which comes from the V DATA . This means that the I LED can be different from the expected value, due to the IR drop in the pixel circuit. Therefore, the real display image would have a deviation from the target display image. This problem becomes more severe at a lower gray scale, since the step size of the lower gray scale would be in the range of ∼pA. Fig. 9 represents a modee metal line, R M , connected to the source of M DRV . Equation (11) shows that V DATA deviates in the metal line as follows: where V DROP can be expressed as where k represents the row number of the display, n the whole row number of the display, and R M the resistance of the metal routing trace. Equation (12) shows that V DROP with the k th pixel can vary on a specific pixel location inside the array and the mode of the display. In this case, it is assumed that the I LED,k in all rows are the same. The I/O pads are placed on the bottom perimeter of the backplane, so the V DATA of the top pixel has the worst voltage drop. Fig. 10 shows an example of the IR drop on a pixel array. Even if exactly the same image data or V DATA is written into all pixels, each micro-LED would have a different brightness, which in turn would affect the uniformity of the display image. It could also become worse when the total number of pixels increases. In summary, the 2T1C pixel circuit has the advantage of achieving smaller pixel dimensions, but the display image is prone to leakage, as well as an IR drop problem. In order to achieve a smaller pixel size with a uniform display, a more sophisticated pixel circuit is required.

III. PIXEL CIRCUIT DESIGN A. LEAKAGE CURRENT
In order to minimize the leakage current, a ''T-Switch'' structure has been introduced [20]. Fig. 11 shows the structure of the ''T-Switch''. I OFF is greatly reduced with this structure, thanks to V HOLD which modifies (7) so that it becomes where V HOLD is the bias voltage connected to V SAMPLE through the switch transistor, M 3 . However, this scheme adds an extra transistor and bias source, V HOLD , to the pixel circuit. This addition could become a burden in the layout when the pixel size gets smaller. In this paper, we investigated alternative solutions which aim to minimize the leakage current. The first is to use a ground reference instead of V HOLD at the source node of M 3 , thus removing the extra bias requirement, as shown in Fig. 12. If the switch control signal, φ, is low, M 3 is off while M 1 & M 2 are on. In this case, V GATE becomes the same as V DATA . When the transistors M 1 & M 2 are off, then V GATE and V DATA nodes are disconnected. The intermediate node, V SAMPLE , is set to the ground reference. This reduces the I OFF of M 2 at the lower gray levels, thereby avoiding the above-mentioned worst I LEAK case. However, this approach still has a problem FIGURE 12. Conventional (left) and improved (right) pass gates with the first proposed method. VOLUME 8, 2020 at higher gray levels, where I OFF increases as the V DS of M 2 becomes the highest value.
The other approach investigated here is to simply split the switch transistor into two transistors in series, as shown in Fig. 13. This scheme creates a V SAMPLE node with the parasitic capacitors, M 1 and M 2 (C G1 , & C G2 ), without requiring an extra bias voltage. It reduces the difference between V GATE and V SAMPLE by delaying the change of V SAMPLE with C G1 & C G2 because the V SAMPLE usually follows the V DATA . Therefore, the V DS of M 2 is close to zero, minimizing the I OFF of M 2 across the entire gray scale. In addition, it does not require the extra transistor, as is the case in Fig. 12.

B. IR DROP
To alleviate the IR drop problem, the V GS bias of the M DRV should be independent of any ground reference. Fig. 14 illustrates the proposed solution by adding a transistor to avoid the problem caused by the IR drop. Unlike the 2T1C pixel circuit, the bias current to the LED is determined by a combination of the gate-source voltages of M DRV _N and M DRV _P . The M DRV _P configured with a PMOS is always on, because the gate is connected to the local reference node, and the current of the pixel is determined to be where k n and k p are the process transconduction parameters of each MOSFET, and V S is the source voltage at each of M DRV _N and M DRV _P .  Fig. 15 shows the proposed pixel circuit, 4T1C, which combines a low leakage switch structure and an IR drop compensation circuit. The pixel size of the 4T1C pixel circuit can be minimized by using a low breakdown voltage transistor with the minimum gate length at any given CMOS process. However, the transistor directly connected to the LED of the pixel should have a high enough breakdown voltage, because the LEDs often use a higher supply voltage than the ones used in normal logic transistor devices, due to the turn-on voltage requirement of the LEDs. In this paper, a 1.8 V power supply is used for the logic transistors. Therefore, a transistor with a high breakdown voltage, M REF_BIAS , is added in order to provide a voltage clamp, as shown in Fig. 16. The voltage at the drain of M DRV _N can be arbitrarily set by adjusting the V REF_BIAS connected to the gate. The V REF_BIAS is determined by the following expression:

C. PROPOSED PIXEL CIRCUIT
where k BIAS is the conduction parameter of M BIAS , and V D is the drain voltage of M BIAS .  The simulation time was set as one frame time, or 16.6 ms. As shown in Fig. 17 and Table 3, I LED at 2T1C circuit changed significantly during the one frame time, to 45.2 nA from 2 µA at the typical process corner, and to 4.43 nA at the worst process corner. With the proposed pixel circuit, it changed a lot less: to 1.57 µA at the typical process corner model, and to 1.02 µA at the worst process corner. Thus, I LED leakage is improved by 75.9 % at the typical corner and 51.3 % at the worst corner.  The simulation results of other cases are shown in Fig. 18, Fig. 19, and Fig. 20, Table 3, and Table 4. As shown in these figures and tables, I LED and V GATE behavior in the proposed circuit is improved in all cases, compared to the conventional 2T1C circuit. Fig. 21 shows the error rate of the I LED in the proposed pixel circuit under an IR drop in the local GND line, which is from the global GND line on the I/O pads. The IR drop error rate is defined using the following equation [19]:   where I LED0 is the driving current in the ideal case, and I LED is the driving current with an IR drop. In the case of a 2 µA driving current to the micro-LED, the error rate between the conventional 2T1C pixel circuit and the proposed pixel circuit is shown in Fig. 21. The error rate of the proposed pixel circuit is reduced significantly thanks to the IR drop VOLUME 8, 2020   Fig. 22 shows the overall functional block diagram of the CMOS backplane with the proposed pixel circuit. It includes the peripheral circuitry that drives the pixel array, including a scan driver, source amplifiers, a separate gamma generator for RGB color, and an emission control. The RGB pixel drive scheme for the proposed sub-pixel circuit is shown in Fig. 23. It is designed to support a separated 8-bit color control for RGB. One of the 255 gray scales, which is generated by the gamma generator, is delivered through DEC to the buffer amplifier. The output of this buffer is written into each pixel by R_SEL, B_SEL, and G_SEL through 1-to-3 DEMUX when the switch control signal (V SCAN ) is enabled. Then it is passed to the gate of the driving transistor inside R_PIXEL,  G_PIXEL, or B_PIXEL, accordingly. The timing diagram of the driving RGB pixel is shown in Fig. 24.     The sub-pixel pitch is 5 µm and a single RGB pixel pitch is 10 µm (2 by 2 with RGBR sub-pixel structure). Fig. 26 shows the simulated and measured I PIXEL using the test images. In order to verify the IR drop compensation scheme of the proposed circuit, three test images were used: the top, middle, and bottom regions of the array.

Fig
(W/R/G/B)_TAR is the simulated target I PIXEL , while (W/R/G/B)_TOP, (W/R/G/B)_MID, and (W/R/G/B)_BOT are the measured I PIXEL in each test image. This simulation shows that the measured I PIXEL fits well with the target I PIXEL . Fig. 27 shows the maximum pixel current difference (Max. I PIXEL ) in each test image. The I PIXEL of each side is defined as (16), and Max. I PIXEL is the maximum I PIXEL with all the gray scales of each color.
The maximum I PIXEL of the white, red, green, and blue line pattern is 1.04 %, 1.94 %, 2.05 %, and 2.46 %, respectively. This proves that the non-uniformity of the pixel current with the proposed circuit is less than 2.5 % with the whole region on display.

V. CONCLUSION
In this paper, a 4T1C-based pixel circuit scheme has been introduced to address the degradation of the display image caused by the leakage current of the switch transistor, as well as the IR drop of the array. Due to the driving current, and the characteristics of its display gamma correction value, the proposed pixel circuit improves the uniformity of the display image. A detailed circuit analysis of the proposed pixel circuit, and its simulation results have been presented. The simulation and test results show that the proposed pixel circuit helps to solve the problems of the leakage current of the switch transistor and the IR drop.