Original Approach Toward Three-Phase Indirect Matrix Converters Through Hybrid PWM Modulation and DSP Implementation

Power electronic matrix converters are converters carrying out just one solitary transitional stage. AC-AC conversion automatism in matrix converters is attained through the exploitation of bidirectional controllable power switches associated with a structural matrix. The indirect matrix converter is an alternating preference to the direct matrix converter embodied by AC-DC converter and DC-AC inverter. In this paper, an assemblage of Pulse Width Modulation categories is used to control the dual stages of IMC. AC-DC converter is modulated through the well-known space vector algorithm, while DC-AC inverter is modulated through a novel algorithmic conception referred to as the digital scalar algorithm. Comparative analysis between the conventional DSVPWM modulation and the novel proposed modulation technique is escorted demonstrating that the latter is facilely comprehended and simply put into real-time practice. This paper comes forward with digital signal processor real-time enforcement, conceived for indirect matrix converter. Uniting both original approaches into one topological system entrained a significant decrease of 38% in real-time computation assesses. Throughout the paper, it is well proven that the proposed solution results in high-quality input/output waveforms, and averts from servicing supplementary devices that trigger silicon devices’ gates. Numerous experimental enquires within the delivered research reveal advantageous aspects of the contemporary approach from overall simplicity to entire effectiveness.


I. INTRODUCTION
Matrix converters are AC-AC power topologic converters that receive electrical signals characterized by fixed voltage, magnitude, and frequency from the input AC grid source. Their role is then to deliver electrical signals characterized by variable voltage, magnitude, and frequency to the output AC load. Less demand for energy storage devices makes the valuation of the converter high. Matrix converters hold multiple enticing distinguishing features over customary AC-AC power topologic converters. The considerably advantageous The associate editor coordinating the review of this manuscript and approving it for publication was Jenny Mahoney. feature of MC is the capacitor-free aspect. The absence of massive electrolytic polarized capacitors, that are of confined lifespan, from the converter elicits compact design, reliable circuitry, and enhanced power density structure. The additional favorable feature is the admirable quality of input/output grid/load current and voltage waveforms. Possessing a manageable input power factor is feasible due to the existence of bidirectional power switches. The drawback of MC topologies is the restricted output/input voltage magnitude transfer ratio [1]- [4].
Indirect matrix converters are improved substitutes of matrix converters developed to comply with the needs of industrial claims. The topology is composed of two separate VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ stages. Fig. 1 shows the power circuit of the grid-connected indirect matrix converter topology (IMC). Rectification for alternating current AC to direct current DC takes place in stage 1 through the grid-connected four-regional rectifier. During this stage, the rectifier receives fixed grid voltage signals and controls grid current signals to safely deliver positive DC voltage at its output. A capacitor-free indirect matrix converter behaves with the DC voltage as a virtual entity.
Inversion from direct virtual current DC to alternating current AC takes place in stage 2 through the load-connected fourregional inverter. During this stage, the inverter receives variable virtual DC voltage and controls the load voltage to safely deliver targeted quantities at its output. Indirect matrix converters hold several appealing hallmarks over direct matrix converters. The considerably advantageous features of IMC are the ease in the commutation process and the reduced need for clamps. Indirect matrix converters are encouraging for industries that work for distributed generation systems (DG), multi-phase drives, and multi-phase machines [5]- [10]. Modulation strategies are set to adjust input-grid current properties and alter output-load voltage properties. Various modulation approaches were suggested and applied to IMC such as the double space vector pulse width method (DSVPWM) and carrier pulse width method (CPWM). Comparative analysis for DSVPWM and CPWM is conducted to illustrate the following; DSVPWM ensures the utmost flexibility in terms of distributing switches' sequences, guarantees minor levels of load current harmonics, and mitigates the common-mode voltage gain. Contrarily, this modulation discloses complex accounts and formulation. As for CPWM, it ensures direct application and fewer calculation requirements. Conversely, sequencing flexibility is not touched and real-time implementation is difficult relative to in-market controllers' availability. Sophisticated studies in the literature were previously announced in terms of closed-loop control methods such as, but not limited to, predictive control, sliding mode control, and repetitive control, to improve the overall system's dynamic response, raise accuracy, & reinforce bodies' robustness [11]- [15].
The absence of bulk energy storage devices in matrix converter topologies grounds the necessity of complex algorithmic methods' platforming such as digital signal processor (DSP), complex programmable logic device (CLPD), or field-programmable gate array (FPGA) bases. The former platforming is high-priced, nonintegrated, and in demand for software development expertise. Besides, DSP sets out total synchronization of input source and establishes gate signals without supplementary circuitry. This paper is entitled to the original approach towards indirect matrix converters through hybrid PWM modulation and DSP implementation. The AC-AC power topologic converter to be considered in this research is the indirect matrix converter. As for the originality of the modulation, a hybrid combination of two algorithms; the SVPWM and the simple, easily understood, scalar modulation (SPWM), is set forward to modulate electrical entities of the power system. SVPWM is annexed to the rectifier stage while SPWM is annexed to the inverter stage. As for the originality of the real-time implementation, simplicity rules the situation owing to the fact that 1 DSP controller chip is employed avoiding any FPGAs. Both united approaches reveal around 40% reduction in count time without affecting the good operation of topology.
This well-developed research paper is organized point to point. In the introduction, the power topology studied is clearly specified. Section II thoroughly narrates the original approach through hybrid PWM modulation by putting into hand the modulation of the grid-connected rectifier and the load-connected inverter stages. Section III lists all design parameters and displays the verification of the former approach through Simulink Simulation. Section IV precisely reports the original approach through both stages' control and DSP real-time implementation. Section V ensures the originality of the approach by displaying the experimental setup and results. Section VI compares analytically the converter's performance under DSVPWM versus Hybrid combination. In the conclusion section, the main advantages of the proposed algorithm and the overall proposed solution are underlined.

II. ORIGINAL APPROACH THROUGH HYBRID PWM MODULATION A. MODULATION OF THE GRID-CONNECTED RECTIFIER STAGE OF THE IMC
As it is clear in Fig. 1, the main electrical power is delivered from the grid, which is considered the input to the topologic rectifier. Assign letters (a, b, c) to the three-phase input source where grid voltages are sinusoidal, symmetrical, and balanced denoted by (U a , U b , U c ) and specified in Equation (1) [16]- [18]: Input currents denoted by (i a , i b , i c ) sustain inductancecapacitance input filtering before turning into the converter's input currents (i ma , i mb , i mc ). Straightaway, the aim of the modulation and the function of the rectifier stage are primarily to keep (U a , U b , U c ) and (i a , i b , i c ) constantly in-phase and secondly to deliver positive voltage at the stage's output where this voltage is to be of virtual DC nature (U dc ). In this sub-section, the modulation of the grid-connected rectifier stage through SVPWM is clarified. The AC-DC rectifier, considered in Fig These 9 combinations representĪ , the input current space vector displacement in space where 3 of them are null and 6 space vectors are allowable [19]- [24]. Fig. 2 shows the 6 active space vectors.Ī 1 is an active input current space vector with coordinates [1, −1, 0]. This means: 9 current combinations bring forth 9 values of the rectifier's output virtual DC-Link voltage (U dc ). The 6 active input current states correspond to 6 input grid voltage states. LetŪ resemble the state of (U a , U b , U c ) . Using an angular phase detector controller, the input instantaneous phase angle θ i which is equal to ω i t is estimated and the sector location (k i ) is determined as is clear in Fig. 2. The first step into the modulation is to make known the reference input current space vector. The goal is to obtain the unity input displacement factor that is achieved whenŪ andĪ are always in phase. Generally discussing, consider that the power factor is variable and there exists a value for input displacement angle denoted by ϕ i . All data considered,Ī m being the reference input current vector is skillfully located in the space graph with an angle γ i = θ i + 6 + ϕ i . Back to Fig. 2, suppose that the input voltage vector is located in sector 1. Subsequently, is positioned and can be realized through partial operations of the active combinations reflecting the status of rectifier switches. Active vectors that are responsible to achieve the reference current located in sector 1 areĪ 1 andĪ 2 in a fraction of a period application [25]- [27]. Define d 1R as the duty ratio of application ofĪ 1 and d 2R as the duty ratio of application ofĪ 2 . Equations (2), (3), (4), (5), and (6) depict the geometrical analysis [28]- [35].
In order to benefit from the full power, null status vectors are not exploited and duty ratios of any 2 out of the 6 active vectors add up to 100%.
Under each switching period of 100 µs, the duty ratios are modified yielding new status vector switching and new average value described below.
The ripple designation, evident in the Equation (9), is transferred from the rectifier stage to the inverter stage through VOLUME 8, 2020 the intermediate DC link. The inverter is hereby in charge to remove it as it will be deliberated in the following sections.
Due to the presence of 6 space sectors, there exist 6 possible reference current positions relative to sector number. Equation (10) is a general formula for γ i varying the sector number k i .γ In this subsection, the scalar modulation of the loadconnected inverter stage through SPWM is clarified. The main electrical power should be delivered to the load, which is considered the output of the topologic inverter. Assign letters (A, B, C) to the three-phase output load where voltages, denoted by (U AN , U BN , U CN ) are normalized and their fundamental components referenced to the neutral phase are specified in Equation (11).
The goal of this modulation is to safeguard sinusoidal output voltages with controllable frequency and amplitude. The DC-AC inverter consists of 6 bi-directional power switch, each of which consists of 1 MOSFET and 1 diode joined in an anti-parallel manner. For easier analysis, it is considered that the virtual DC-Link voltage input of the inverter is ripple-free as in Equation (12).
Back to Equation (11), the angular velocity of the output voltages is ω o , M i is the dedicated inverter modulation index, and the peak value of the fundamental component isÛ o tracked in Equation (13).
Replacing Equation (12) into (13), the value M i is as follows: Let q be the output/input voltage transfer ratio such that: Therefore, M i and q will relate as below: Injection of a zero-sequence signal into the PWM method is imposed here for the sake of increasing to a maximum value 1.155 . Consequently, q has a maximum value of 0.866 cos(ϕ i ). which is, in turn, the generalized maximum value for the voltage transfer ratio of all three by three matrix converters. The modified output reference voltage is acquired after the common-mode injection through the initial sinusoidal reference vectors. It should be pointed out that the injections disappear from line-line voltage signals. Denote by (U A , U B , U C ) the modulation signals and by U zs zero-sequence signal injected; stated in Equation (17).
Another injection into the modulation signals takes place for the purpose of demounting the ripple term stated in Equation (18) so the final modulation signals are as below: (T AH ) is the switch located in the output inversion phase at the higher end of the topology. T AH is turned on by means of its duty cycle with reference to U * A . Equation (19) shows the duty cycles of T AH , T BH , and T CH .
andd C cannot take a value greater than 1 or less than 0 and for this restriction is enforced by inducing a translational term µin the expression of the common-mode added voltage waveform such that µ(0 ≤ µ ≤ 1) as per Equation (20).
Suppose, for instance, that SVPWM is applied to issue the modulating signals of the inverter's switches. When upper power switches, characterized by (T AH T BH T CH ) are set to 1, the 7 th null space vector V 7 is therefore customarily applied. This application is considered a partial contribution to the freewheeling phase of the inverter stage. Let t V 7 be the time of application of V 7 , and let t 0 be the time of the freewheeling phase. Equation (21) depicts that t V 7 is directly proportional to via the slope µ. Accordingly, the time of application of the following null space vector t Vf is alternatively expressed in Equation (22); Referring back to Equation (19), the overall equation governing d A has only one variable that can be interchangeable which is µ . Simulation is done to obtain the waveforms of d A given that the source frequency is considered 60Hz, and the load frequency is to be 70Hz with a transfer rate of 0.86. Fig. 3 shows the waveforms of Where µ shifts from 0, 0.5, and finally 1.
Graph interpretation of waveforms displayed in Fig. 3 indicates the following: -When µ = 0, and during the low cycle, the waveform is held tightly to 0 -When µ = 1, and during the high cycle, the waveform is held tightly to 1 -When µ = 0.5, and during the low and high cycles, the waveform is neither held tightly to 0 nor to 1.
For µ = 0 & µ = 1, losses of the inverter resulting from the switching process are reduced but on the other hand, the rectifier stage will not operate in safe commutation conditions.
In this research, µ is set to 0.5 to hand out equal distribution and assure the rectifier's safe commutation.
In Fig. 4, PWM sequences during all topological stages are rendered. Considering that the input current reference space vector lies in sector 1, as previously shown in Fig. 2, matching current status space vectors areĪ 1 [1, −1, 0] and I 2 [1, 0, −1] whereĪ 1 is applied for d 1R andĪ 2 is applied for d 2R as appeared in Fig. 4(a). Respective values for the DC-link voltage are U ab and −U ca for each instant cycle as appeared in Fig. 4(b).Ī 1 [1, −1, 0] is founded by making T aH = 1 and T aL = 0, T bH = 0 and T bL = 1, with T cH = 0 and T cL = 0. In the same manner,Ī 2 [1, 0, −1] is founded as appeared in Fig. 4(c).
When it comes to computing the duty cycles of the inverter stage, absolute synchronization between both stages must be conducted to accomplish the desired results reflected in output voltage and input current waveforms. Back to Equation (19), and given that the load voltage angle varies between [0, π 3 ] , duty ratios can take 3 values of maximum, minimum, and middle estimation. Equation (23) sets the ratios as below: In what follows, (d A , d B , d C ) are proportioned between duty ratios of the rectifier stage, (d 1R , d 2R ). As is clear in Fig. 4(d), gate pulses of the inverter switches are deliberated as follows: A profound study of PWM sequences in all stages of conversion clearly states that during one period T s , and within the commutation of the rectifier, the three phases of the inverter are either clamped to the high end of the topology or all clamped to the opposite low end. This reveals that no current is given birth to during commutation and both stages are completely disconnected during commutation ensuring the safety rules discussed previously. The positive clamping happens during µt 0 whereas the negative clamping happens during (1 − µ)t 0 . Equation (24) reveals the relation between µ and T s .

III. THE APPROACH VERIFIED THROUGH SIMULATION RESULTS
The topology along with the hybrid modulation is tested using Matlab/Simulink/SimPowerSystems and the results are shown in Fig. 5, 6, 7, 8, and 9. The results prove that the topology and control work well enough. Table 1 below states the parametrical values used. Fig. 5 proves that the input current waveforms are sinusoidal and in phase with the grid voltages. In addition, Fig. 8 and 9 show that the waveforms of the output voltage is also sinusoidal and follows the inductive load current waveforms shown in Fig. 10. Fig. 6 reflects the virtuality aspect of the No DC-Link Voltage value with acceptable levels and values of harmonics.

IV. ORIGINAL APPROACH THROUGH DSP IMPLEMENTATION
A. REAL-TIME IMPLEMENTATION As compared to the signals' analysis related to the conventional pulse width modulated voltage source inverters, the pulses to be applied directly on the gate power   switches of the indirect matrix converter are moderately dissimilar. Fig. 4 delineates that the pulses particular to the load-connected inverter stage are intrinsically not lined up centrally. Besides, the pulses particular to the grid-connected  rectifier stage undergo, during a complete period of switching, modulation resulting in first, left / right lining up, and second, high/low forcing. Additionally, the bidirectional power switches located along with the same leg of the rectifier, are gated in a way that their relative pulses are not restricted to be complementary. To date, almost all electric circuit arrangements that upshots logic results are founded by using complex programmable logic devices (CPLD) and Field-programmable gate arrays (FPGA) for the sake of building pulse width modulated switching sequences in real-time execution [36], [37].
In this article division, a forthright achievement of the objectives is realized through the evident application of the Enhanced Pulse Width Modulator -Texas Instruments (ePWM) of the digital signal processing DSP TMS320F28335.
The blueprint of the ePWM is revealed in Fig. 10 where its elementary building block is envisioned. This modular package is capable of engendering double signals that are primarily not dependant and secondly pulse width modulated

B. CONTROL OF THE LOAD-CONNECTED INVERTER STAGE
In furtherance of easiness in clarification, the upper transistor of the first phase A of the load-connected inverter will be addressed and detailed below. Immediately after the final acquisition of T AH gate signal, a direct inverse manner is applied on this output signal so that it is applied on the gate of T AL transistor. T AH transistor gate is fed by the output of epwm-xA and similarily, T AL transistor gate is fed by the output of epwm-xB.
Let TBCTR be the time base counter and define by TBPRD the maximal assess count of TBCTR. Equations (27) and (28) outline values that are charged into the comparison record CMPA & CMPB.
Continually, and within every entire switching period, a comparison process intervenes between TBCTR and CMPA / CMPB. Equation (29) points out the comparing occurrence: These two instances are dispatched to the Action Quali-fierAQ. Equations (30) & (31) reveal the output of the AQ.
AQx is afterward, submitted to the Dead Band (DB) as an input term. DB's outputs are the pulse width modulated signals. These two signals are additionally characterized by a time delay period that can be turned on and programmed. Fig. 11 below demonstrates the following: a) Synthesize of gates pulses of T AH and T AL within an epwm module. VOLUME 8, 2020  b) The instantaneous value of time base counter TBCTR-counter compare submodule output events. c) Action Qualifier output signal AQ-x. d) PWM output signals epwm-xA and epwm-xB.
An extremely significant benefit is remarked when zooming into Fig. 11 (a) and examining the geometrical nature of the TBCTR. The former is represented by a straight line indicating that its slope is approximately constant and this makes the method way more advantageous over the Carrier PWM approach.

C. CONTROL OF THE GRID-CONNECTED RECTIFIER STAGE
A similar approach to what was depicted in IV. B. will be interpreted in this coming section but the main difference is that the issues related to gates of the grid-connected rectifier will be dealt with. The upper and lower transistors of the second phase b of the grid-connected rectifier will be addressed and detailed below.
A back reference to Fig. 4 section (c) clearly states that while the pulse, that is transmitted to the gates of the lower transistors T bL , undergo modulation, the gates of the higher transistors of, as well, phase b T bH , undergo a low-status order.   Here, the two upper transistors T bH gates are fed by the output of epwm-xA and similarly, the two lower transistors T bL gates are fed by the output of epwm-xB.
Equations (31) and (32) outline values that are charged into the comparison record CMPA & CMPB.
And again, within every entire switching period, a comparison process intervenes between TBCTR and CMPA / CMPB. A similar Equation (33) as in (29) points out the comparing occurrence:

TBCTR = CMPB
AQ-x runs down to the falling-edge delay blocking submodule and to the inverted gate of the (DB). Subsequently, the epwm-xB, which is the output signal that feeds the transistors' gates of T bL , is shaped from the previously mentioned AQ-x. Fig. 12 section (d) explicitly shows that epwm-xB originates a pulse that has the right alignment and distinguished by a turn-on delay.
In contrast, and through the complete switching period, the signals supplying the upper transistors T bH must stay in low-status.
Accordingly, CSFA bits are set to (01) as indicated in Equation (25) to acquire the above results.    Taking into consideration that the reference input current vector in the complex space plane may be located in any of the sectors numbered from 1 and up to 6, a comprehensive study is performed and results are briefly declared as in Table 2. Table 2 shows the general waveforms of TbH and TbL pulses as well as the opportune values assigned to comparison registers (CMPA and CMPB) and the two couples of bits (CSFA and CSFB) for the six possible positions of the input current reference vector in the complex plane.
Demonstrating an example for the Table, suppose that the reference input current vector is located in sector 4, therefore, T bH pulse is modulated, T bL is forced low, CMPA = 0, CMPB = d 1R * TBPRD, CSFA = 00, and CSFB = 10.

V. THE APPROACH VERIFIED THROUGH EXPERIMENTAL RESULTS
An experimental prototype of the Indirect Matrix Converter is developed to test the proposed modulation algorithm. A simplified block diagram of the converter and control algorithm is illustrated in Fig. 13. The converter is connected to the grid through an LC filter and supplies a three-phase star-connected The last block computes first the reference output voltages (U AN , U BN , U BN ) , from the target references U * α and U * β which are usually generated by an outer loop. Then, it VOLUME 8, 2020 computes the modulating signals U * A , U * B , and U * C according to (18) and the duty ratios d A , d B , and d C as reported in (19). Finally, the opportune values of CMPA and CMPB registers of each epwm module are determined as explained above in section IV-A. To make compatibility with the data type format of epwm modules compare registers, all CMPA and CMPB values computed by the arithmetic unit are converted into 16-bit unsigned format.
The whole algorithm is first implemented using Simulink toolbox and the target support package ''Texas Instruments C2000''. Then, the TI code generation tools for windows to generate a project file for code composer studio and download the real-time executable into the DSP memory. Finally, the build process automatically runs this executable file on the DSP. The sampling and switching periods are both set to 100µs. Fig. 14 displays the waveform of a modulation signal computed according to (18) where the voltage transfer ratio is set to: This figure is obtained from a screen snapshot of Code Composer Software (CCS) running in real-time.
As can be seen, the modulating signal is inherently nonsinusoidal because of the injection of zero-sequence-term and the compensation of the dc-link voltage ripple.
On the other hand, it can be observed that the waveforms are quite within the bounds (−1, 1) which means that full utilization of the virtual dc-link voltage is achieved in the linear region.
In addition, the real switching signal/gate pulses waveform of TaH (upper switch in the first leg of the Rectifier) and of TAH (upper switch in the first leg of the Inverter) are illustrated in the Fig. 15.
All signals associated with the input electrical parameters are to be displayed below respecting the previous conjecture. Fig. 16 shows the inductive load current signals ( i AN , i BN , i CN ). The output load current waveforms are promptly cognate by the virtual DC-Link voltage character & nature. Fig. 16 displays sinusoidal and balanced signals highlighting that ripples suspended in the DC bus are redressed and distortions resulting from lower frequency signals are the slightest. As a conclusion, and as clear through depicted figures, the signals requested for modulation act upon the linear region in an effective manner. Fig. 17 shows the line-line three-phase output load voltage signals. Fig. 18 represents the line-neutral input voltage and input current that is blindly sinusoidal and in phase. The figure explains the unity displacement factor characteristic that is attained through the modulation. Now fix f 1 out = 70Hz and q1 voltage = 0.86 and consider it the 1st operational status; and let f 2 out = 40Hz and q2 voltage = 0.6 and consider it the 2nd sudden changeable operational status. Fig. 19 shows the input grid current signal under a sudden changeable condition affecting output frequency and voltage transfer ratio. Fig. 20 shows the inductive load current signal under the same conditional status. Fig. 19 & 20 together demonstrate that signals preserve their sinusoidal nature during the steady-state phase. In addition, and even though input signals barely oscillate during the transient state, the input filters are well operating to prevent harmful overshooting.

VI. DSVPWM VERSUS HYBRID MODULATION: COMPARATIVE ANALYSIS
A comparative study between the conventional DSVPWM method and the proposed one is presented [39]- [41].
The latter is based on the computing time that is required to run the algorithm as well as the THDs of line and load currents. The conventional DSVPWM algorithm is therefore implemented on the same DSP running at 150 MHz where the digital scalar modulation scheme included in the third block of Fig. 13 was replaced by the conventional DSVPWM scheme. Table 3 shows the number of time-consuming operations used in both algorithms and the obtained results are shown in Table 4. The times needed by the blocks namely ''conversion to 16-bit unsigned format'' shown in Fig. 13 are not included in the obtained results. The results show that the proposed hybrid method allows reducing near 38% of the total computation time. This is due to the simplified hybrid control algorithm of the inverter stage that needs only 3.26µs (see Table 4) while the conventional SVPWM algorithm needs 16.09µs. The large computational time of the conventional SVPWM algorithm is mainly due to two key procedures: The lookup tables that determine the opportune switching sequence for each transistor according to the position of the reference vector in the complex plane. The time needed for this operation is near 3.35µs. The ''arctan'' trigonometric function and lookup table needed to determine the phase angle of the output voltage space vector and its operating sector in the complex plane. The time needed for this procedure is near 8.74 µs. These two time-consuming procedures do not exist in the scalar modulation algorithm, which justifies the substantial reduction of the time interval needed for the control of the inverter stage.   currents under DSVPWM. Section VI. displays a comparative THD evaluation of line and load currents as a function of the voltage transfer ratio q and the output frequency fo and as can be observed, both modulation algorithms provide quite similar performance. Therefore, it can be concluded that the proposed hybrid modulation algorithm provides the same performance as the SVPWM while reducing the software design complexity and the computation time. Fig. 23 shows

VII. CONCLUSION
The main objective of this research work is to propose cheaper and simple software and hardware solution for realtime implementation of an indirect matrix converter's controller without affecting its performance. From the point of view software, a simplified modulation algorithm that is much less complex for implementation on a digital processor and needs less computational time than the SVPWM algorithm is proposed. The main drawback of the SVPWM technique is the very important computational effort to implement it in real-time. This is because it needs time-consuming operations such as the use of the arctan function to localize the position of the reference vector in the complex plane and large lookup tables to determine the opportune switching vectors. From the point of view hardware, only a single DSP board is used to implement the overall control removing thus the additional FPGA/CPLD chip usually needed in the most of former implementations. His research interests concern the modeling and control of switch-mode converters, modern rectifiers, power factor correction, active power filters, and the gridconnectivity of renewable energy systems. He has authored one book, two book chapters, and more than 200 technical papers, which are published in international journals and conferences, and holds one patent.
Dr. Kanaan is also the Vice-Chair of the IEEE Lebanon Section and an EXCOM Member of the IE/PE/CAS/PEL Joint Chapter in Lebanon. He has served as an Associate Editor for the IEEE TRANSACTIONS INDUSTRIAL ELECTRONICS, and he is currently a member of the IEEE Power Electronics Society (PELS), the Industrial Electronics Society (IES), and the Industry Applications Society (IAS). In 1999, he joined the Faculty of Engineering, UL, as an Associate Professor, and then he became a Professor, in 2014. He is associated with other engineering societies. He organized and participated in more than 20 international conferences. He is a Reviewer of different international journals and conferences, and he has participated in international research projects. He has authored more than 200 papers published in scientific journals, conferences, and books. He had supervised more than 35 Eng., 10 M.Sc., and 8 Ph.D. degree students. His current research interests include the areas of renewable energy, power electronics, and the diagnosis of the converter-machine set and energy management of power systems. He is currently an Associate Professor of electrical engineering with the ISSAT, University of Sousse. He is affiliated with the Canada Research Chair of Electric Energy Conversion and Power Electronics, École de Technologie Supérieure, Montréal, QC, Canada. He is also a member of the Research Laboratory LATIS, National Engineering School of Sousse, and the University of Sousse. His main research interests include renewable energy conversion systems, digital signal processors, and field-programmable gate arrays for embedded real-time control, grid-connected converters, and fault diagnosis of power converters. Since June 1990, he has been a Professor with the École de Technologie Supérieure, Université du Québec, Montréal, QC, Canada, where he has been the holder of the Senior Canada Research Chair in Electric Energy Conversion and Power Electronics, since 2002. He has supervised more than 150 Ph.D. and M.Sc.A. degree students and coauthored more than 600 articles and 2 books. His research interests include high-efficiency power electronic converters, active and hybrid filters, modular multilevel converters, multilevel converters, and active rectifiers, including modeling, control, and development of industrial prototypes.
Dr. Al-Haddad was the President of the IEEE Industrial Electronics Society, from 2016 to 2017, and a Fellow of the Canadian Academy of Engineering.