A 65nm Continuous-Time Sigma-Delta Modulator With Limited OTA DC Gain Compensation

This paper explores the effects of compensating the performance degradation in high-speed Continuous-Time Sigma-Delta modulators when the loop integrators are implemented through limited gain Operational Transconductance Amplifiers. Yet, the low DC-gain strongly affects both integrator magnitude and phase responses, with a reduction in the overall effective number of bits. This work models the degradation as due to a signal-dependent memory-less perturbation and theoretically studies its compensation by feeding an opposite signal back to the integrator input. The implementation and experimental results on a 65nm CMOS 2nd order prototype evaluate the performance increase with this technique, where no other compensation, nor any digital calibration, is included. Tested in different conditions, the compensated prototype improves more than 1.5 bit the ENoB with respect to the uncompensated counterpart. For a sampling frequency of 500 MHz the power consumption is 1.7mW, resulting in a 477.2fJ/conv-lev Walden and a 148.8dB Schreirer Figures of Merit.


I. INTRODUCTION
Analog-to-Digital converters (ADCs) represent a critical stage in many high-performance portable applications. The accomplishment of a good trade-off between conversion performance and energy-consumption is a critical specification that is typically not easy to achieve. The recent research items up to 2019 [1] show the continuing interest on the Continuous-Time (CT) based data converters. For a wide bandwidth, these present a good balance between the system resources and are still an option for high-performance data converters design. Another influential feature is the low quantization levels that make these modulators attractive for signal processing. As an example, other recent publications show important benefits for ultra wide-band communications with single-bit CT encoded streams [2]. The main reason is that a single-bit architecture allows using, in the feedback loop, a simple comparator and a digital buffer as Digital-to-Analog converter (DAC) and ADC, respectively, thus reducing the delay in the loop. In this scenario, regardless The associate editor coordinating the review of this manuscript and approving it for publication was Jenny Mahoney. of the improvement in the state-of-the-art, of the increase in order, and of special techniques that may be incorporated to obtain the desired noise shaping, the design of highperformance, large bandwidth (BW) integrators is the critical issue. In particular, when considering Operational Transconductance Amplifier (OTA) based CT integrators, both the BW and the low-frequency open-loop gain (the DC gain) of the OTA must accomplish the in-band noise requirements for a specific resolution [3].
When the OTA design requires a very large BW (i.e., up to a few GHz), the implementation of a multi-stage OTA is problematic. Stability issues require a passive compensation network that, however, limits the BW and increases the resources to fulfill the CT modulator's requirements. A workaround often addressed by designers is given by implementing OTAs composed of a single-stage [4]. This solution easily allows a very large BW. However, achieving a single-stage OTA with DC gain higher than 40 dB is not an easy task [5]. Therefore, a low OTA DC gain is a non-ideality that must be considered at design time. The effect in CT modulators is not only a modification of the integrator's magnitude as a function of the frequency but also a degradation of the phase response.
An integrator whose response deviates from the ideal one is known as leakage integrator [6].
Many solutions have been proposed so far in the effort of improving the CT integrators in modulators. For the sake of illustration, the topology proposed in [3] is based on a Single Amplifier Biquad (SAB) integrator with an additional RC passive network in the feedback path. The peculiarity of the design allows relaxation in the requirements of the GBW product for the OTA. However, even if a low GBW can be tolerated, a more detailed analysis shows that the noise shaping in this solution is still sensitive to a low OTA DC gain. Another aspect to be considered is that leakage integrators not only degrade the Signal to Quantization Noise Ratio (SQNR) because of the magnitude influence on the noise transfer function but also change the integrator's frequency response, giving rise to the Excess Loop Delay (ELD). New topologies have been proposed compensating the ELD and the aforementioned inconveniences with more stages in the OTA [7]. Another recent option is the single-amplifier resonator in CT modulators [8], [9]. The properties in this CT circuit improve the overall modulator's resolution at the expense of more passive elements. The mentioned work highlights the limitations of the OTA DC gain, which must be higher than 40 dB to achieve the desired benefits.
Notwithstanding the mentioned improvements, it is also possible to increase the resolution employing a digital calibration-correction scheme. The drawback is the increase of both the complexity of the DAC in the feedback loop and system power requirement. Anyway, even considering the digital-assisted architectures, the CT integrator is still the bottleneck at increasing the performance of a modulator. Previous works show that it is possible to compensate for the OTA limited DC gain by introducing negative feedback in the integrator [10]- [13]. This solution is sometimes indicated as negative-R assisted integrator. More recent works [11], [13] suggest advantages in implementing this feedback by using a transconductance amplifier. The main contribution of this work concerns implementation considerations for the transconductance based compensation of the limited DC OTA gain.
Concerning [11], [13], and other similar papers, the novelty of our work can be summarized as follows. i) We present a detailed theoretical background, to highlight the limits and the advantages of the proposed technique, but also of refuting some erroneous conclusions appearing in the recent literature. ii) The entire design of the prototype is specifically studied to operate in the condition where the proposed compensation is of paramount importance. The designed OTA is a single-stage high bandwidth, but with a quite low gain. The transconductance compensation stage is designed to work paired with the designed OTA and includes a common-mode compensation that is not present in other works. The single-bit architecture is selected to allow a high sampling frequency; furthermore, as a minor contribution, a simple and high-speed comparator is proposed to implement the one-bit DAC with a limited loop delay. Finally, no digital compensation is used, so that any observed advantage is due to the compensation technique. iii) We propose an evaluation of the effectiveness of the approach through a straightforward comparison between measurements from a non-compensated prototype and measurement from a compensated prototype that does not feature any other compensation technique, nor any digital compensation. To the best of our knowledge, this is the only paper in the literature capable to present such a complete discussion on this technique. As an example, [13] proposes a low-bandwidth low-power based on high-gain two-stages folded cascode OTAs, where there is actually no need for the low DC gain compensation and lacks in the comparison between performance obtained without compensation.
The manuscript is organized as follows. Section II introduces some analytical aspects of the CT integrators' behavior under the assumption of a limited OTA DC gain. Section III explains the proposed compensation strategy on a CMOS 65 nm process, with emphasis on the critical circuit design constraints. Section IV shows the measurement setup and results of the designed prototype. Results are compared with that achieved by the most recent CT modulators, highlighting the Figures of Merit (FoMs). Finally, Section V draws the conclusion.

II. LOW DC GAIN COMPENSATION IN CT INTEGRATORS
Due to reliability purposes, high-speed CT voltage integrators for modulators are designed upon a traditional OTA scheme. In this paper, we focus on the topology based on a single-stage OTA, whose schematic is shown in Fig. 1. For an ideal OTA, we have an infinite transconductance g m → ∞, an infinite output resistance r o → ∞ and a negligible output capacitance C p → 0. Under these assumptions, the circuit of the figure implements an ideal inverting voltage integrator: indicating with e i the input signal, with e 2 the OTA input signal, and with e 3 the output of the integrator, and considering zero initial conditions, the integrator evolution is RCd e 3 (t)/dt = −e i (t), or in the Laplace domain: (1) Yet, the deviation of real OTA implementations from this ideal and simple model is the principal source of resolution degradation in CT data conversion. To keep this VOLUME 8, 2020 into account, we introduce in the OTA model: i) a limited transconductance g m ; ii) a limited output resistance r o ; ii) a limited bandwidth, modeled in Fig. 1 with the non-zero intrinsic capacitance C p . Note that C p and r o could be used to include additional non-idealities due to a capacitive or a resistive OTA load, respectively.

A. RESPONSE OF A NON-IDEAL SINGLE-STAGE OTA BASED INTEGRATOR
Let us consider the OTA-based integrator for CT modulators of Fig. 1 with a non-ideal OTA, and let us indicate witĥ e 3 the output of the circuit. Even with a non-ideal model, it is still reasonable to assume that: The frequency response of the non-ideal integrator deviates from the ideal one (1), and by means of (2) can be approximated as: With respect to (1), the magnitude response in (3) is not going to infinity for s → 0, but is upper bounded by g m r o . At a first glance, this is the principal source of performance degradation; indeed, it is possible to show that the low OTA DC gain severely impacts also the phase response. The transfer function (3) features a (positive) real zero with associated frequency ω z = g m /C and two (negative) real poles with associated frequencies: that, given (2), can be approximated in: with ω p1 the dominant low-frequency pole, and ω p2 the high-frequency one. It is reasonable to assume that ω z is larger than the system BW. Since ω p2 > ω z , both ω z and ω p2 have little impact on the in-bandwidth signal. Conversely, the low-frequency pole ω p1 deviates from zero. This results in a non-negligible magnitude and phase distortion with respect to the desired ideal response for the in-bandwidth signal, that can be evaluated as in the following.
For frequencies lower enough than ω z , the dominant pole approximation is suitable for (3), that can be written as: By relating (1) with (4), we can evaluate the magnitude deviation as: and a phase deviation: which are non-negligible for values of ω lower enough than 1/(RC). As an example, for very low values of ω, the phase error grows up to π/2. The circuit turns from an inverting integrator to a low-pass inverting amplifier, canceling the integration effect.
In other words, the effect of a limited DC gain in single-stage OTA based integrators is not only a magnitude error but also a phase one. Of course, the two effects are strongly related; however, we would like to put stress on the second one. By considering the phase error, it is possible to immediately see that the problem is not just a DC-gain smaller than the expected one, but that the underlying principle is radically changed, turning from an integration operation to amplification. This point of view makes clearer how an uncompensated limited DC gain can strongly affect the integration operation.

B. COMPENSATING THE LIMITED DC GAIN
It is possible to formulate Eqn. (4) into the time domain as: i.e., there is an additional time-dependent term −ê 3 (t)/(g m r o ) with respect to the expected ideal integrator response. Eqn. (5) suggests that a possible way to cope with the limited DC gain is to consider the term −ê 3 (t)/(g m r o ) as a signal-dependent memoryless perturbation, that can be canceled by injecting into the circuit an equal term with opposite sign. For low values of ω, i.e., in the part of the transfer function that needs to be adjusted, we can neglect the parasitic capacitive elements in nodes e 2 , e 3 of Fig. 1 and consider e 3 (t)/(g m r o ) = e 2 (t). So, we can either consider the perturbation term proportional toê 3 or e 2 . This observation is important since it allows us to conclude that the node e 2 has all the necessary information to cancel the perturbation.
The circuit we propose to compensate the limited DC gain is the integrator of Fig. 2, where a current signal g c e 2 is injected into the e 2 node. Using (2), and indicating withē 3 the compensated circuit output, the transfer function can be approximated as: 36466 VOLUME 8, 2020 with a high-frequency positive real zero with ω z = g m /C and two negative real poles with: where the perturbation term 1 − 1 + C p /C g c /g m can be reasonably considered not far from the unity value. By setting g c = 1/R the pole ω p1 goes to zero, and the above perturbation term goes to 1, so that the response of the the compensated integrator matches that of the ideal integrator. The error with respect to the ideal response can be obtained by recomputing the transfer function (6) by considering all terms previously neglected. This leads to: where the zero and the non-null pole are still larger than system BW, so that the transfer function, for the frequencies of interest, can be approximated with: This results in zero phase error and in a constant, negligible magnitude deviation, given by: The developed model allows also to evaluate the effect of limited bandwidth for the additional transconductance stage. Let us assume a low-pass transfer function g c (s), with a single-pole in s 0 g c (s) = g c0 1 1 + s s 0 and let us use this expression to replace all g c terms in (6), easily computing the new integrator transfer function. Its expression is quite cumbersome, and it is not reported here. It features two zeros, the first (negative) at s 0 and the second (positive) at g m /C, and three (negatives) poles. Under the assumption that 1/(g m r o RC) s 0 g m /C p , the computed poles are: where, neglecting as above the perturbation term (1 − (1 + C p /C)g c /g m ), we have a pole-zero cancellation between ω p2 and the additional zero. So, the response is same as for an ideal g c transconductance.
Note that 1/(g m r o RC) is the pole of the uncompensated integrator and has typically a low-frequency value. The design of the g c stage is, therefore, not critical in terms of bandwidth. In conclusion, the cost in terms of resources of this compensation approach is very low and given by an additional, small, low-bandwidth, low-power transconductance stage.

C. INFLUENCE OF LEAKAGE INTEGRATORS ON THE MODULATOR NTF
An approach to theoretically calculate the effective resolution of a CT modulator based on a one-bit quantizer from the Noise Transfer Function (NTF) and Signal Transfer Function (STF) can be found in [14]. The Effective Resolution is calculated by relating the normalized power of the input signal to the integrated noise figure within the signal bandwidth. Indicating with H N (s) the NTF, and considering the second order modulator architecture in Fig. 3, we get: where B(s) is the continuous time filtering of the quantization error in the feedback path, i.e., from Y (s) to Q(s) in the figure: Accordingly, the deviated integrator transfer functions set a lower bound on the NTF, and the overall resolution of the converter is impaired. The case studies plotted in Fig. 4 have been obtained replacing H 1 (s) and H 2 (s) with expression (1) for the ideal case, (4) for a limited and uncompensated DC gain, and (6) for a limited but compensated DC gain.
The ideal NTF achieves a second order filter profile. The theoretical Signal to Noise Ratio (SNR), that yields the converter effective resolution, is 75 dB. The limited DC gain increases the in-band noise. For a value of g m r o as low as 26 dB (i.e., a 20 V/V gain), the SNR drops to 42 dB. This result corroborates the large DC gain requirements. Typically, A v OSR is required to shape the noise figure to an acceptable profile [15]. Indeed, in the compensated integrator regulated by (6), the NTF remains very close to the ideal performance.
Note that (6) considers the bandwidth limitation. The compensation stage ideally cancels the constant term of the characteristic polynomial but does not appear on the high order terms. It is possible to conclude that, as long as the non-dominant pole is not within the signal-band, the NTF is barely affected. The work presented in [13] mentions that the negative-resistance compensation relaxes the unity-gain frequency limit for the OTA. However, the detailed analysis and experimental tests help to highlight the limitations of the circuit.

D. PERFORMANCE OF NOISE AND LINEARITY
The transconductance-based DC compensation inherently reduces the overall noise figure of a CT integrator. The schematic in Fig. 5 shows the integrator with possible input noise sources: v n model the OTA noise referred to input, while i n other sources of noise, including that introduced by the  With g c = 1/R, the expression reduces to: Therefore, in the ideal scenario, the input referred noise v n of the OTA is canceled by the compensation scheme. In addition, the noise figure in (7) locates the pole to zero frequency, and shapes the compensation stage noise i n to a high-pass function. In a more realistic scenario, perfect compensation cannot be reached. Indeed, under the assumption that Rg c ≈ 1, and that v n and Ri n are comparable in terms of power, the main contribution to the output noise is given by i n due to the presence of the scaling factor Rg c − 1 term in the transfer function of the v n . So, we focus on the i n contribution. Fig. 6 shows, assuming v n negligible, the value of H n (s) = e 3n (s)/i n (s) for realistic values of the integrator parameters and for different compensation outcome. In other words, the figure gives an idea of how the input noise is transferred to the output according to the achieved compensation. A perfect compensation correctly locates a pole to the zero frequency and drastically reduce the low-frequency noise. Yet, for g c = 1/(0.9R) the low-frequency output noise is still reduced by 12 dB with respect to the uncompensated case. This model is valid as long as the OTA remains in the linear range of operation. The compensation circuit monitors the analog ground nodes, having small signal amplitude. Therefore, the compensation circuit design must behave linearly for this small signal amplitudes.
For the sake of clearness is important to notice that it is possible to use the compensation scheme also for multi-stage amplifiers because the compensating stage does not influence high order terms. However, the limits in bandwidth and power consumption make the compensation ineffective. This application is particularly suited for high-speed modulators.

III. CIRCUIT IMPLEMENTATION A. TOPOLOGY SELECTION AND LIMITATIONS
The scope of our work is to analyze the benefit of the transconductance based compensation scheme on the Sigma-Data modulator. For a better analysis, the topology and design must reduce other non-ideal circumstances. The target design is a medium to high-speed converter based on integrators with a very large BW so that a design based on single-stage OTA is preferable. The achievement of a high-gain is not an easy task, but the consequence of a low gain is the impairment of the integrator transfer function. The need for a high-speed converter requires considering an architecture having a good trade-off between tolerance to ELD, linearity and Noise Shaping.
According to the existent theoretical considerations in [6], the second-order single-loop CT modulator raises the in-band noise floor to −80 dB, with an ELD less than twenty percent of the sampling period. Therefore, this topology can tolerate large ELD values. In higher-order topologies the tolerance is reduced to only a few percentage units, with the need for ELD compensation, rising other complications.
Therefore, for the experiment design in this work, the second-order scheme ensures stability, ELD tolerance, and a 2-levels quantization ensures linearity and simplicity of a Non-Return to Zero (NRZ) DAC to reduce circuit resources.
The DACs are simple inverters from the digital output to the CT integrators, without the need for including additional voltage references. The only drawback is the power supply noise, that can be reduced with proper decoupling and routing techniques. Moreover, Section II-D discusses the advantages of the compensation scheme in noise. Furthermore, a feedforward typology requires an additional summing point that limits bandwidth and resolution [6]. This is the motivation for selecting a distributed feedback topology, including the consolidated high-speed CT design techniques. In conclusion, this scenario is actually the ideal case study to highlight the effects of the limited DC gain in the OTA implementing the CT integrators.
Given the aforementioned considerations, the proposed compensation scheme has been applied to the two integrators used in a high-speed second-order single-bit modulator whose block diagram is depicted in Fig. 7. A feedforward path is used to reduce the output swing in the second integrator. The coefficients are selected to improve the effective resolution under the assumption that the sampling frequency is F s = 1/(RC) and that the input signal can span the whole range [0, V dd ], that is also the conversion range of the 1-bit DAC. The circuit has been designed in the UMC 65 nm mixed-signal process. Table 1 summarizes the main modulator parameters. The implementation of the modulator at circuit-level follows a fully-differential approach and is shown in Fig. 8. Integrators are based on a simple RC scheme using single stage OTAs and have been compensated using two transconductance stages according to the approach illustrated in Fig. 2. With respect to the theoretical approach of Sec. II, two minor changes are considered: i) being fully differential, the compensating stages are driven by a doubled voltage with respect to the single-ended approach. As a result, their transconductance value is set to g c /2; ii) both integrators present multiple inputs. In this case, the g c must be calculated according to the equivalent resistance at the integrator's input.

B. SINGLE STAGE OTA
The CT integrators of the designed prototype are based on a single stage fully differential OTA. Fig. 9 shows the schematic at transistor level, the dimensions and the specs of the OTA. The OTA uses a discrete time common mode feedback circuit [16] to set the output common mode output to the V cm = V dd /2 value. The common mode control is on the V CMFB node in the scheme. The DC gain is only 21 dB; however, the gain-bandwidth (GBW) product is very large  and equal to 1.3 GHz, allowing for sampling frequencies up to F s = 500 MHz.

C. COMPENSATING TRANSCONDUCTANCE STAGE
The schematic of the compensating transconductance stages is based on the fully differential pair shown in Fig. 10. The circuit includes a CT CMFB block that sets the common mode voltage to V cm . All the NMOS transistors and all the PMOS transistors have the same size, indicated with (W /L) gn and (W /L) gp , respectively, that is set according to the desired values of g c1 and g c2 . Note that, due to the non-tight requirements in terms of bandwidth (as addressed in Sect. II), we preferred to design this stage using long-channel transistors (i.e., 16 L min = 0.96 µm) to limit the mismatch between transistors and so the variations of the compensating transconductance.
According to the modulator's schematic in Fig. 8, the two integrators are driven by an equivalent resistance equal to 2 R and 24 R/7, respectively. Given the value of R in Tab. 1, the desired gain for the transconductance stages is g c1 = 500 µS and g c2 ≈ 290 µS, i.e., g c1 /2 = 250 µS and g c2 /2 ≈ 145 µS.

D. COMPARATOR
Since this work aims to propose a measurement of real advantages of the compensation of the low DC-gain in the OTA integrator, it is necessary to keep all other sources of error at a negligible level. In particular, it is of paramount importance that the degradation of converter performance due to the comparator delay is limited (and negligible) compared with the performance degradation due to the low DC gain. Therefore, in the pursuit of reducing the loop delay, the speed of the comparator is critical.
As a minor contribution of this paper, the designed circuit embeds a novel high-speed comparator based on the regenerative latched comparator in [17]. We introduce two modifications: i) the position of transistors in the fully complementary regenerative network is rearranged in order to reduce the number of series transistor, with beneficial effects in low voltage and high-speed applications; and ii) the Set-Reset latch is very simple with a cross-coupled inverters pair and the evaluating devices are two NMOS transistors. The schematics of the fully differential comparator and of the SR latch (FDSR) are shown in Fig. 11.   FIGURE 11. Schematic of the fully differential comparator and of the SR latch (FDSR).
In the input stage, M 1,4 pre-amplify the differential input signal. Transistors M 2,3 and M 8,9 form a metastable regenerative network with positive feedback that speeds up the comparison and holds the result. M 5,6 and M 7 − M 10 reset the circuit according to the synchronization signal P 1 . Timing scheme for P 1 and its non-overlapping complementary P 1 is highlighted in the figure. When P 1 = V DD , M 7 − M 10 turn on and the S, R nodes reset to V SS , and M 5,6 turn off. In this configuration, the differential input is in wait mode, while the latch stage holds the previous state. As soon as P 1 = V SS , M 7 − M 10 turn off, and after a safe time, M 5,6 turn on thus enabling the metastable circuit.
The latch is formed by transistors M 11 − M 18 . In the hold state (P 1 = V DD ), the preamplifier computes with outputs disconnected from the latch. M 11 − M 14 operate as a standard holding circuit. In the set state (P 1 = V DD ), the preamplifier outputs are stable and passed to the latch storing the result. When the latch is disabled, even if the preamplifier enters into a not-valid state, the latch holds the previous comparison and a new cycle starts.

E. ROBUSTNESS OF THE COMPENSATION
The circuit for the compensation scheme uses the common mode bias point to set the transconductance. The compensation scheme in [13] is similar, since the cross-coupled inverters can also set the transconductance, but the bias point is not statically set. As a consequence, the scheme may not be effective when considering Process-Voltage-Temperature (PVT) changes.
Indeed, the scheme presented here is robust to PVT variations. In this section, we limit ourselves to provide simulation results when considering process variations. Fig. 12 shows the transfer function of the first integrator of the loop of Fig. 8 (considering both magnitude and phase response) in 50 runs of a Montecarlo simulation using the device models provided by the foundry that include process variations. Both the compensated and uncompensated integrators have been considered. In all runs the compensation scheme is capable to improve the overall integrator's performance both in magnitude and phase. Even if the uncompensated circuit features smaller variations, the fully differential topology of the compensated scheme ensure stability for all cases, and the compensated phase response is close to the 90 deg value of the ideal inverting integrator for a quite large range of frequency.
Note that the introduction of variability in the circuit parameters results in a non-perfect compensation between g c and R. More precisely, we may obtain an integrator that is undercompensated (i.e., g c R < 1) or overcompensated (i.e., g c R > 1). In the first case, we obtain for low frequencies, an inverting transfer function, with phase equal to 180 deg, while in the second case a non-inverting transfer function, with phase equal to 0 deg. This is the expected behavior: according to (6), if g c R = 1, the integrator is turned again into a low-pass amplifier as in the non-compensated case. This amplifier is inverting or non-inverting if 1 − g c R is positive or negative, respectively. This is visible in the figure where the worst-case reduces the cut-off frequency by at least one order of magnitude, comparing to the uncompensated case.

A. EXPERIMENTAL TEST SETUP
The microphotograph of the integrated circuit prototype is depicted in Fig. 13. The circuit has been designed and manufactured in UMC 65 nm CMOS design process using the multi-project wafer service offered by Europractice R . The design tool used for the design was Cadence R Virtuoso. The prototype physically embeds multiple instances of the designed modulator, in which the value of C was scaled to allow to work at three sampling frequencies F s = {125 MHz, 250 MHz 500 MHz}. For comparison purposes, the prototype embeds both the Sigma-Delta modulator with and without the compensation stages.  The experimental setup is shown in Fig. 14. The prototype is powered by a 3.3 V button cell battery, used to generate the V dd = 1.2 V power supply voltage, the V cm = V dd /2 and all OTA current references (''Bias mini-board'' in the figure). This solution is adopted to reduce noise coupling and to allow at the same time to change the OTA biasing. The input signal is transformed to fully differential with a JT-1975 balun, with a 80 MHz bandwidth and a 3 dB insertion loss in this frequency range. The Keysight 81160A arbitrary signal generator provides the clock signal, while the input signal is from a Siglent SDG1025 waveform generator. A Keysight 16851A logic signal analyzer is used to acquire the oversampled bitstream. When possible, the logic signal analyzer and the device under test share the same clock signal to capture data in the synchronous configuration. Due to hardware limitations, this was possible up to 300 MHz; beyond this limit, the logic analyzer allows only the asynchronous setup.

B. MEASUREMENT RESULTS
The designed prototype has been characterized by measuring the Signal to Quantization Noise Ratio (SQNR) according to the frequency spectrum computed through the Discrete Fourier Transform of the acquired signal using, for a better distinguishing of the harmonic content, N = 81920 points. A total of 8 spectra have been considered and averaged to avoid (either best-and worst-case) corner cases. Fig. 15 shows the CT modulator dynamic range for the compensated and uncompensated cases. The difference between the two curves approximately ranges between 6 dB and 10 dB for any input power level, resulting in a gain that can be evaluated between 1 bit and 1.5 bit. Moreover, the dynamic range for the compensated prototype shows an extended behavior close to the full scale (0 dB) amplitude ranges, with a higher gain concerning the uncompensated case.  reference. The ratio between F in and the system BW is set to 0.148, thus ensuring that any possible harmonic content rises in the signal bandwidth. The comparison between the two curves clearly shows an increased harmonic content and quantization noise floor level for the uncompensated circuit. The effective number of bits is improved by almost 2 bit.  Note that the resolution achieved by the compensated circuit is very similar to that achieved by high-level simulation of an ideal system and given by 10.53 bit. This is an important result, considering that the gain of the single-stage OTA used in the integrator blocks is only 21 dB.
A similar trend can be observed in Fig. 17, which shows the result for an input signal with F in = 103.8 kHz and −3 dB from the Full Scale (FS), using a F s = 500 MHz sampling frequency. Note that, to the curves of Fig. 16, both harmonic distortion and noise floor are slightly increased. We believe that this is due to the hardware limitation of our measurement setup, which does not allow the synchronization between the signal analyzer and the prototype clock, resulting in an additional uncertainty source. Anyway, the improvement of the compensated case is more than 1.5 bit also in this case.   the first in the loop is responsible for more than half of the power due to the lower gain. As highlighted in the figure, the two compensating transconductance stages allocate only about 8% of the overall power consumption. As an additional important contribution of this work, the comparator consumes a very low amount of energy corresponding to the 3% of the overall power consumption. Fig. 19 shows the PSD measured with a two-tone input signal. Programming the Siglent SDG1025 signal generator with the EasyWave application makes possible the scenario where two tones with the same amplitude are closely spaced in frequency (they are located at f 1 = 83 kHz and f 2 = 103.8 MHz, with f 2 = 1.25 f 0 ). The aim is moving intermodulation tones to the lower part of the spectrum. The prototype with the compensation scheme achieves very good linearity, as there are no intermodulation effects around the frequency f 2 − f 1 in this test.

D. DIFFERENCES WITH RECENT COMPENSATION SCHEMES
The work in [10] introduces the possibility to compensate the OTA limited DC gain with negative feedback implemented employing a low-gain inverting amplifier and a resistance. However, the basic idea is not practical because the proposed schematic includes an amplifier whose output is a voltage signal. The design is more difficult compared to a transconductance amplifier, in particular for large bandwidth. The compensation scheme requires both a precise amplifying factor and a matched resistance value, thus increasing the error sources. The work in [11] introduced the possibility to use a transconductor stage in the compensation scheme, thus achieving clear benefits. However, the results are presented only at a simulation-level, and most importantly, the compensation scheme is applied on a with a multi-bit quantizer. A problem of the compensation scheme for multi-bit quantizers is that the compensation transconductance value depends on the different values of the DAC resistances. Also, process variations have a negative impact, as it is evident from the simulated results. To make the compensation scheme more reliable it is necessary to add a transconductance stage for every feedback resistor of the DAC. Moreover, if the number of ADC levels is beyond 8, a calibration scheme is required limiting the overall ELD and the physical implementation is not straightforward for high-speed modulators. Therefore, the increased complexity and calibration of a multi-bit ADC reduces the effectiveness of the idea.
The recent works in [13] and [12] present a similar compensation strategy for the OTA's low DC gain. The work in [13] uses the compensation in a two-stage foldedcascoded OTA embedded in a low-power and low-frequency application. For the required bandwidth is possible to select an ad-hoc OPAMPs architecture. Besides, the oversampling ratio makes the limited OTA DC gain to be a non-dominant source of error. The circuit in this work provides a comparison between the experimental results of a prototype with and without the compensation strategy. The work in [12] uses a multi-bit and inverted based integrator CT filter. The topology includes several circuit techniques to improve the overall SNR performance and is not possible to distinguish the impact of negative-resistance compensation. Table 2 shows the important parameters to calculate the most accepted FoMs [1], [23] of the recent CT modulators. For the sake of distinction, the table includes the relation of the architecture with the quantizer levels and the utilization of calibration schemes. The comparison with the similar works is presented in chronological order. The topologies in [3], [7], [12] present good FoM numbers at the expense of a third-order topology and more quantization levels. These solutions use a calibration scheme and the enhanced performance is the combination of the special techniques. The solutions in [13], [20]- [22] give also important numbers, with the integration of several SQNR enhancement techniques.

E. COMPARISON WITH RECENT CT TOPOLOGIES
To highlight the contribution of this work we emphasize the work in [13] which takes a similar DC-gain compensation scheme. A big difference is that the compensating circuit of the reference is impaired with the common-mode voltage of the main OTA, and the modulator aims low-frequency rates, with a multi-stage based amplifier.
In contrast, the modulator designed in this work aims to medium to high speed bandwidth, where the compensation scheme is more relevant. It achieves a Walden FoM of 477.2 fJ/conv-lev and a Schreier FoM of 144.8 dB. The result confirms the effectiveness of the simple DC-Gain compensation scheme in the application where is necessary.

V. CONCLUSION
A theoretical analysis shows that the OTA's low DC-gain degrades to CT voltage integrators. The low DC-gain impairs both the integrator's magnitude and phase responses. Furthermore, it nullifies the integrator operation for the low-frequency components of the input signal. Therefore, OTA's low DC-gain is the bottleneck in the important CT implementations. In this work, trough an integrated circuit prototype of a CT modulators designed in a CMOS 65 nm process, we show that is possible to compensate the negative impact of a low DC gain in single stages OTA. A feedback transconductance stage cancels the frequency-dependent perturbation. With the proposed solution it is possible to achieve a good power to conversion-level balance without cumbersome compensation circuits or additional calibration techniques.