Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

Excess source and drain (S/D) recess depth (<inline-formula> <tex-math notation="LaTeX">$T_{SD}$ </tex-math></inline-formula>) variations were analyzed comprehensively as one of the most critical factors to DC/AC performances of sub 5-nm node Si-Nanosheet (NS) FETs for system-on-chip (SoC) applications. Variations of off-, on-state currents (<inline-formula> <tex-math notation="LaTeX">$I_{off}$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula>) in three-stacked NS channels and parasitic bottom transistor (<inline-formula> <tex-math notation="LaTeX">$tr_{pbt}$ </tex-math></inline-formula>), gate capacitance (<inline-formula> <tex-math notation="LaTeX">$C_{gg}$ </tex-math></inline-formula>), intrinsic switching delay time (<inline-formula> <tex-math notation="LaTeX">$\tau _{d}$ </tex-math></inline-formula>), and static power dissipation (<inline-formula> <tex-math notation="LaTeX">$P_{static}$ </tex-math></inline-formula>) are investigated quantitatively according to the <inline-formula> <tex-math notation="LaTeX">$T_{SD}$ </tex-math></inline-formula> variations. More S/D dopants diffuse into the <inline-formula> <tex-math notation="LaTeX">$tr_{pbt}$ </tex-math></inline-formula> with the deeper <inline-formula> <tex-math notation="LaTeX">$T_{SD}$ </tex-math></inline-formula>, so the <inline-formula> <tex-math notation="LaTeX">$I_{off}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula> increase due to raised current flowing through the <inline-formula> <tex-math notation="LaTeX">$tr_{pbt}$ </tex-math></inline-formula>. Especially, the <inline-formula> <tex-math notation="LaTeX">$I_{off}$ </tex-math></inline-formula> of PFETs remarkably increases above the certain <inline-formula> <tex-math notation="LaTeX">$T_{SD}$ </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">$T_{SD,critical}$ </tex-math></inline-formula>) compared to NFETs. Furthermore, the <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula> contribution of each channels having the <inline-formula> <tex-math notation="LaTeX">$T_{SD,critical}$ </tex-math></inline-formula> is the largest at the top NS channel and the <inline-formula> <tex-math notation="LaTeX">$tr_{pbt}$ </tex-math></inline-formula> has the ignorable <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula> contribution. Among the NS channels, the top (bottom) NS channel has the largest (smallest) <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula> contribution due to its larger (smaller) carrier density and velocity for both P-/NFETs. The <inline-formula> <tex-math notation="LaTeX">$C_{gg}$ </tex-math></inline-formula> also increases with the deeper <inline-formula> <tex-math notation="LaTeX">$T_{SD}$ </tex-math></inline-formula> by increasing parasitic capacitance, but fortunately, the <inline-formula> <tex-math notation="LaTeX">$\tau _{d}$ </tex-math></inline-formula> decreases simultaneously due to the larger increasing rate of the <inline-formula> <tex-math notation="LaTeX">$I_{on}$ </tex-math></inline-formula> than that of the <inline-formula> <tex-math notation="LaTeX">$C_{gg}$ </tex-math></inline-formula> for all SoC applications. However, the <inline-formula> <tex-math notation="LaTeX">$P_{static}$ </tex-math></inline-formula> enormously increases with the deeper <inline-formula> <tex-math notation="LaTeX">$T_{SD}$ </tex-math></inline-formula>, and low power application is the most sensitive to the <inline-formula> <tex-math notation="LaTeX">$T_{SD}$ </tex-math></inline-formula> variations among the SoC applications. Comprehensive analysis of the inevitable <inline-formula> <tex-math notation="LaTeX">$tr_{pbt}$ </tex-math></inline-formula> effects on DC/AC performances is one of the most critical indicators whether Si-NSFETs could be adopted to the sub 5-nm node CMOS technology.


I. INTRODUCTION
For several decades, conventional bulk planar Si-MOSFETs had been successfully scaled down, and several novel strategies were adopted from 90-to 32-nm node to improve the CMOS performance [1]- [4]. However, aggressive scaledown of planar Si-MOSFETs caused the loss of channel controllability, and short channel effects (SCEs) significantly degraded the DC/AC performances. Since 2012, as a solution, 22-nm node Si-FinFETs were adopted to industry for over-The associate editor coordinating the review of this manuscript and approving it for publication was Kalyan Koley .
coming the SCEs and enabling further scale-down [5]. The Si-FinFETs technologies have been continuously improved down to 7-nm node by decreasing fin pitch and contact poly pitch and increasing aspect ratio of fins [6]- [9]. However, these kinds of fin structures need extremely high fin aspect ratio and are limited by fin pitch [10]. As a result, vertically stacked Si-Gate-All-Around (GAA) nanosheet FETs (NSFETs) were proposed as a promising candidate to replace Si-FinFETs due to those superior electrostatics below 7-nm node [11]- [14]. But both Si-FinFETs and Si-NSFETs have inevitable parasitic channels below the intrinsic channels that critically affect the leakage current, which is the killing factor of scaled transistors [15], [16]. Especially, the Si-NSFETs are deeply concerned because of wider parasitic channels than the Si-FinFETs. Meanwhile, in ultra-scaled transistor, impacts of process variations on DC/AC performances are inevitable inherent problems. Among these variations, source/drain (S/D) process variations should be carefully controlled because those are directly related to source-to-drain leakage current as well as drive current. So far, several studies about the impacts of the S/D process variations on the Si-FinFETs including S/D epitaxy shape, depth [17]- [19], S/D length [20], [21], and S/D doping concentration [22] were addressed, but the studies on the vertically stacked Si-NSFETs were rarely reported.
In this paper, we quantitatively investigated the impacts of S/D process variations on the DC/AC performances of sub 5-nm node Si-NSFETs. We analyzed off-and on-state currents (I off , I on ), gate capacitance (C gg ), and switching delay time (τ d ) according to S/D epitaxy shapes and S/D depth variations in the following sections. In Section II, we explained the device design and simulation methodology of the sub 5-nm node NSFETs. In Section III, we investigated the sensitivity of the I off , I on , C gg , τ d , and static power dissipation (P static ) to the S/D process variations. Finally, we gave a conclusion in Section IV.

II. DEVICE DESIGN AND SIMULATION METHODOLOGY
We simulated the sub 5-nm node three-stacked NSFETs with advanced physics models using Sentaurus TCAD simulator [23]. Drift-diffusion model was considered self-consistently with Poisson and carrier continuity equations for carrier transport. Density-gradient model was included to consider quantum confinement effects of the channel region [24], [25]. Slotboom bandgap narrowing model was also included for doping-induced bandgap narrowing in overall device regions [26]. Lombardi mobility model was considered to calculate the mobility degradation induced by transverse field at the interfaces [27]. Inversion and accumulation layer and thin-layer mobility models were included to consider Coulomb, phonon, and surface roughness scatterings [28], [29]. Low-field ballistic mobility and high-field saturation models were also included [30]. Furthermore, we considered recombination using Shockley-Read-Hall, Auger, and Hurkx band-to-band tunneling models [31]- [33]. Finally,a deformation potential model was considered for strain dependency of effective mass, effective density-of-states, carrier mobility, and band structure [34]. Fig. 1 shows the structure of the n-type NSFETs having ideal and U-shaped S/D epitaxies, and its cross-section view. All the NSFETs were formed by fully considering doping, diffusion, and strain effect using Sentaurus process simulator [23]. In reality, S/D recess profile cannot be a perfect vertical shape, so we adopted the U-shaped S/D recess profile, which was taken from [11]. In the U-shaped S/D, inner spacer length (L sp ) could be the shortest (longest) at the top (bottom) side, while gate length (L g ) was the same regardless of NS channels positions. Channel length (L ch ) was defined as distance from the source to the drain epitaxies in each of the NS channels. In addition, Si 0.5 Ge 0.5 and Si 0.98 C 0.02 epitaxies were formed as the S/D to induce compressive and tensile stress to the NS channels for p/n-type FETs (P-/NFETs), respectively.
Highly doped Si 0.5 Ge 0.5 [12] (Si 0.98 C 0.02 ) epitaxies with boron (phosphorus) of 5 × 10 20 (1 × 10 20 ) cm −3 were formed as the S/D of the PFETs (NFETs), and silicon NS channels and substrate were undoped (1×10 15 cm −3 ). Punchthrough stopper (PTS) was doped with phosphorus (boron) of 2 × 10 18 cm −3 in the PFETs (NFETs). Detailed geometry parameters for the sub 5-nm node NSFETs were summarized 35874 VOLUME 8, 2020 in Table 1. Dielectric constants were 3.9, 5.0, and 22.0 in IL, spacer, and HfO 2 for overall regions of the NSFETs, respectively. Each contact resistance (R cont ) of the source and drain defined for contact width was fixed as an optimistic value of 50 · µm for both P-/NFETs [36], and operating voltage (| V dd |) was 0.7 V. All drain currents (I ds ) in this work were normalized to sheet pitch (SHP), and threshold voltage (V th ) was extracted using constant current method at . Finally, the NSFETs structures of this paper were built by process simulation mimicking the real process flow of [11], while electrical simulations were conducted using fully-calibrated physical model parameters of 10-nm node Si-FinFETs including saturation velocity and low-field ballistic coefficient [8], [35]. Here, I-V data of [11] could not be used for calibrating the physical model parameters, because those were presented as arbitrary units. Moreover, to estimate the I on /I off characteristics of the sub 5-nm node NSFET properly, calibrating the mobility and velocity model from matured and well-known Si-FinFETs technology was reasonable approach. For calibrating our TCAD deck to the hardware data properly, a higher S/D doping concentration (N SD ) of the PFETs than the NFETs was adopted for subthreshold swing (SS) and drain-induced barrier lowering (DIBL), which are relatively poorer for the PFETs than for the NFETs.  Table 2. Here, the V th of the PFETs at the T SD of 10-14 nm was not shown because they do not approach to the W ch /L g × 10 −7 A/µm even in very large positive gate voltage (| V gs |). The T SD splits from 0 to 14 nm, and drain voltage (| V ds |) is fixed to the | V dd |.

III. RESULTS AND DISCUSSION
The I off and I on are defined as the I ds when the | V gs | is 0 and the |V dd |, respectively. The ideal S/D NSFETs show the smallest SS comparing to the U-shaped S/D NSFETs due to the longest L ch , which mitigated the SCEs. In U-shaped S/D NSFETs, both I off and I on increase with the deeper T SD , and especially, the I off remarkably increases at the certain points of the T SD . To quantify these points, we defined critical excess S/D depth (T SD,critical ) as the maximum T SD where the I off is smaller than 10 times of I off at the T SD of 0. The definition of the T SD,critical is based on a I off criteria for system-on chip (SoC) applications, wherer the devices having the I off of 10 nA/um are no longer available for standard performance applications [37]. The T SD,critical is 4 nm for the PFETs and 10 nm for the NFETs, and it means that DC performance variations to the T SD are more sensitive in the PFETs than the NFETs.
To analyze which channels mainly contribute to the I off , the I off density of the U-shaped S/D NSFETs according to the T SD is shown in Fig 3a. For both P-/NFETs, the I off density of the NS channels does not change significantly regardless the T SD . Meanwhile, the I off of parasitic bottom channel (I off ,pbt ) in parasitic bottom transistor (tr pbt ) increases as the T SD increases. The I off ,pbt increases with deepen T SD , because more S/D dopants inevitably diffuse into the PTS region and reduce the V th of the tr pbt . Especially, the I off ,pbt density of the PFETs severely increases above the T SD,critical because the S/D dopant concentration of the tr pbt for the PFETs begins to increase remarkably above the T SD,CRITICAL . On the other hand, in the NFETs, the S/D dopant concentration linearly increases according to the T SD increase and its amount is smaller than the PFETs' (Fig. 3b). As a result, the PFETs are more sensitive than the NFETs to the T SD variations and show larger I off ,pbt density and SCEs.
More details on the PFETS, a critical factor of high I off sensitivity to the T SD is channel stress (S zz ) differences between the NS channels and the tr pbt . Fig. 4 shows transfer characteristics of the PFETs having the N SD of 1 × 10 20 cm −3 according to the T SD (note that the annealing condition has  been also revised accordingly to reproduce the experimental SS [8].). For accurate characteristic projection of the PFETs having the N SD of 1 × 10 20 cm −3 , S/D dopant profile along the NS channel is adjusted to 3-5 nm/dec (inset above in the Fig. 4) [38]- [42]. Note that the PFETs having lower N SD still suffer from severe upsurge of the I off as the T SD increases (T SD,critical is 6 nm). Typically, the compressive S zz of the PFETs retards boron diffusion into the silicon channels [43], and compressive S zz in the tr pbt is much smaller than NS channels. As a result, more S/D dopants can easily diffuse into the tr pbt than the NS channels (inset below in the Fig. 4), and it significantly degrades the SCEs, regardless the N SD of the PFETs.   [44]. Unlike the off-state operation, on-state operation shows different dependency on the T SD with device types. First in the PFETs, as the T SD increases, the I on density in the tr pbt (I on,pbt ) remarkably increases, whereas the I on densities in the NS channels decrease. On the other hand, in the NFETs, the I on,pbt density slightly increases, but the I on densities in the NS channels  rarely vary. In common, increasing S/D dopants diffusion into the PTS region with the deeper T SD induces the I on,pbt density increases for both P-/NFETs. The different dependencies of the I on densities on the T SD in the n-/p-channel NS channels are mainly analyzed with potential differences between the ends of the NS channels (P SD ). The P SD is defined as the valence (conduction) band energy difference between source and drain epitaxies of the PFETs (NFETs) and the P SD is extracted at the center of channel thickness and width of the NS channel (inset of Fig. 6). We investigated the P SD of the top NS only because the other two NS channels also have the same P SD tendencies as the top NS channel (Fig. 6). Increasing I on,pbt with the deeper T SD causes the larger potential reduction by the R cont , so the P SD also reduces. Especially, the I on,pbt remarkably increases above the T SD,critical in the PFETs but increases a little in the NFETs. As a result, the P SD significantly decreases for the PFETs and lowers the I on densities of the NS channels, but the P SD does not vary much for the NFETs.
To reveal the origin of the I on , we analyzed the I on contributions of each channel using the U-shaped S/D NSFETs with T SD of the T SD,critical (Fig. 7a). For comparison, the I on contributions of the ideal S/D NSFETs was also investigated in [45]. The I on contributions of each channel was evaluated by integrating I on density over the channel cross-section area at the center of channels (see Fig. 1c). The top NS channel has the largest I on contribution for both P-/NFETs and those are 41.1 % and 39.6 %, respectively. Interestingly, the tr pbt has a negligible I on contribution (0.5 and 1.1 % for the P-/NFETs, respectively), contrary to the case of the I off (Fig. 3). In addition, the bottom NS channel shows the smallest I on contribution for both P-/NFETs (28.3, 26.8 %, respectivly).
The reason why each of the NS channels has the different I on contributions can be clarified using carrier density, mobility, and velocity. Typically, current density is proportional to the product of the carrier densitiy and the velocity (Fig. 7b). First of all, the carrier density is proportional to gate overdrive voltage (| V gs | − | V th |). More S/D dopant diffusion into the channels decreases the | V th | of each channels, resulting in higher carrier density at the same | V gs |. The S/D dopant diffusion mainly occurs at S/D annealing steps due to its high annealing temperature. In this step, both the L ch and the S zz complexly affect the S/D dopant diffusion. The shorter L ch , the deeper S/D dopants diffuse from the S/D to the channels, whereas compressive (tensile) S zz retards boron (phosphorus) diffusion into silicon channels [43], [46], [47]. Furthermore, the larger S/D volume beside top-side NS channel typically induces more compressive (tensile) S zz than the bottom-side channels in the PFETs (NFETs), but the S zz differences among the NS channels for the NFETs is neglectible. Therefore, these two factors (the L ch and the S zz ) result in the S/D dopant concentrations in channels having order of top> middle ≈ bottom (top> midddle> bottom) NS channel in the PFETs (NFETs), and the carrier densities of each channels are also in this order. Secondly, carrier mobilities is critically affected by impurity scattering and the S zz . The carriers in the top-side NS channel are mostly suffered from impurity scattering due to the largest amount of S/D dopants in the channel. Then, although the S zz can boost the carrier mobility, the carrier mobilities of each NS channls show almost inversely proprotional to the amounts of impurities. Finally, the carrier velocities of the PFETs are the largest (smallest) in the top (bottom) NS channel because the shorter L ch makes stonger electric field along the channel direction. On the other hand, the carrier velocities of the NFETs are almost the same among the NS channels because the smaller (larger) carrier mobilities of the top (bottom) NS channel can be compensated (degraded) in carrier velocities by its larger (smaller) electric field. Therefore, for these reasons, I on contributions of each channel are determined like the Fig. 7a, and we summaized the dominant factors determining the I on contributions of each NS channel in Table 3.

C. AC PERFORMANCE ANALYSIS
In this section, the effects of the tr pbt on AC operation are investigated comprehensively. In the NSFETs, the C gg consists of intrinsic gate oxide capacitance (C ox ) and parasitic capacitance (C par ) consisting of inversion capacitance of the tr pbt (C inv,pbt ), inner (C if ) and outer fringe capacitances (C of ) (Fig. 8a). Fig. 8b shows the C gg and C inv.pbt of the NSFETs according to the T SD . The C gg was extracted at frequency of 1 MHz, and C inv,pbt was extracted as follow: 1) Integrating inversion charge density in the PTS region over the PTS volume along the V gs . 2) Differentiating the results of 1) over the V gs , then getting the series-connected capacitance,C inv,pbt + C ox . 3) Subtracting the C ox from the results of 2), then obtaining the C inv,pbt itself. Here, C ox = L g × W bot × 3.9 × ε 0 /EOT, where ε 0 is the vacuum permittivity and EOT is the effective oxide thickness with T IL of 1 nm and T Hf of 2 nm. 35878 VOLUME 8, 2020 The ideal S/D NSFETs have the smallest C gg due to their longest L sp and negligible I on,pbt . The C gg of the U-shaped S/D NSFETs with the T SD of 0 are 9.7 % and 7.8% larger than the ideal S/D NSFETs' for the P-/NFETs, respectively. Meanwhile, the C gg of the U-shaped S/D NSFETs increases up to 7 % as the T SD increases. Because gate oxide thickness and width of the tr pbt are not varied with the deeper T SD , the C ox is not varied much, then increase of the C par dominantly induces the increase of the C gg . Interestingly, the C inv,pbt is negligible when T SD = 0, however, its contribution to the increase of the C par gradually increases as the T SD deepens.
The P static (= I off × |V dd |) versus the τ d (= C gg × |V dd |/I on ) of the NSFETs is also presented for SoC applications: low power (LP), standard performance (SP), and high performance (HP) (Fig. 9). The I off is fixed to 10 −10 A/µm for the LP, 10 −9 A/µm for the SP, and 10 −7 A/µm for the HP. The ideal S/D NSFETs have the smaller τ d than the U-shaped S/D NSFETs with the T SD of 0 because of their superior I on and smaller C gg ( Table 2 and Fig. 8b). In the U-shaped NSFETs, the τ d decreases with the deeper T SD due to the increasing rate of the I on being larger than the increasing rate of the C gg in both P/NFETs. However, the P static significantly increases as the T SD increases because tremendous amount of current flow in the tr pbt at off-state operation. Fortunately, when the T SD is less than the T SD,critical , the variations of the τ d and P static according to the T SD are small. In addition, the τ d and P static of the PFETs are more sensitive to the T SD than those of the NFETs because the tr pbt of the PFETs drives more leakage current than the NFETs'. Furthermore, the LP is more sensitive to the T SD than the SP and the HP. Therefore, the T SD should be controlled less than T SD,critical to prevent the serious variations of the τ d and P static , especially in the PFETs than the NFETs and for the LP than the other applications.

IV. CONCLUSION
The T SD variations of the sub 5-nm node NSFETs were thoroughly investigated in terms of the DC/AC performances. The tr pbt is a critical killing factor of the NSFETs in advanced technology node. The deeper T SD induces more S/D dopant diffusion into the tr pbt and lowers the V th of tr pbt , so the I off and the I on increase due to the tr pbt . Especially, the I off remarkably increases above the T SD,critical (4, 10 nm for the P-/NFETs, respectively), and the I off of the PFETs is more severely degraded than that of the NFETs because the compressive S zz of the tr pbt is inevitably smaller than the S zz of the NS channels for the PFETs. At the T SD,critical , the top NS channel is the largest contributor to the I on for both P-/NFETs, but fortunately, the tr pbt is the negligible contributor to the I on (0.5, 1.1 % for the P-/NFETs, respectively). The C gg also increases due to the increase of the C par as the T SD deepens, especially, the contribution of the C inv,pbt to the C par also gradually increases. However, the τ d decreases as the T SD increases due to the increasing rate of the I on being larger than the increasing rate of the C gg in both P/NFETs for all the SoC applications. Finally, the P static enormously varies compared to the τ d . The τ d and P static are more sensitive to the T SD variations in the PFETs than in the NFETs and for the LP than the other applications. Therefore, the sub 5-nm node NSFETs ensures immune to the T SD variations if the I off can be controlled only. He was a Postdoctoral Researcher and a Technical Engineer with SEMATECH, Albany, NY, USA, from 2011 to 2015. He was a Senior Device Engineer with the SAMSUNG R&D Center (Pathfinding TEAM), South Korea, from 2015 to 2017. Since 2017, he has been an Assistant Professor in electrical engineering with POSTECH. His research interests include technology benchmark by characterization, simulation, and modeling of advanced devices and materials (fin, gate-all-around, nanosheet FETs, 3D-NAND, 3DIC, SiGe, Ge, and III-V). VOLUME 8, 2020