Research on a Novel DC Circuit Breaker Based on Artificial Current Zero-Crossing

Modular multilevel converter-based high voltage direct-current (MMC-HVDC) transmission has developed rapidly because of its flexibility, reliability and efficiency. DC circuit breaker (DCCB) is one of the key equipments to ensure the safe and stable operation of MMC-HVDC power grids. In this paper, we investigate a novel topology of DC circuit breaker based on artificial current zero-crossing. The proposed DC circuit breaker can effectively limit the magnitude and rise rate of fault current at the converter station side and reduce the impact of DC fault on the converter devices. The principle and operation sequence of this topology are described. Meanwhile, the breaking process of the DC fault is analyzed theoretically and the considerations for parameter design are presented. Finally, the system model of DC circuit breaker and a four-terminal MMC-HVDC test system are built in PSCAD/EMTDC. The simulation results show that the proposed DC circuit breaker is effective for quick breaking after fault.


I. INTRODUCTION
MMC-HVDC power transmission technology based on power electronics is widely used in power supply and grids and has become the focus of research. MMC-HVDC technology has great advantages in renewable energy gridconnected, distributed generation grid-connected, island power supply, urban distribution network power supply, etc. Especially in recent years, the number of MMC-HVDC transmission projects has been increasing, which has proved that MMC-HVDC transmission has its feasibility and superiority in technology and engineering [1]- [5].
However, the DC fault which leads to serious overcurrent is still a major challenge in HVDC grids realization and development [6]. Till now, only using DC circuit breakers can achieve the required fast and flexible fault isolation without voltage collapse, and maintain normal operations of non-fault areas in HVDC grids. The technology of DC circuit breaker has been extensively studied in academic and industrial fields The associate editor coordinating the review of this manuscript and approving it for publication was Ying Xu . at home and abroad [7], [8]. In the previous researches, DC circuit breakers can be categorized into three types: mechanical DCCBs (MCBs), solid-state DCCBs (SSCBs), and hybrid DCCBs (HCBs) [8]- [12]. Among them, the solidstate DCCBs use semiconductors with turn-off ability, such as Insulated-gate bipolar transistors (IGBTs) and Integrated gate commutated thyristors (IGCTs), and attain very fast operational speed [13]- [15]. Although SSCBs have the most satisfactory operational speed for interrupting currents, consisting of massive semiconductors causes high conduction losses and high cost. The MCBs do not have enough fast fault current interruption capability [8], [11].
The hybrid DCCBs combine the advantages of mechanical DCCBs and solid-state DCCBs, which makes HCBs be preferable [8], [13], [16]- [18]. ABB developed a structure of HCB that contains a main DC breaker (MB) and a bypass formed by an auxiliary DC breaker in series with a fast mechanical disconnector [13]. The MB is composed of many IGBTs to withstand the transient overvoltage and serious fault current. The State Grid Corporation of China also proposed a full-bridge based HCB, which is also an IGBT-based hybrid DCCB and has been used in Zhangbei MMC-HVDC engineering project [19]- [21]. Recently, various topologies of hybrid DC circuit breakers have been proposed [22]- [30], and most of these topologies have common features: The fault current cannot be effectively limited, a large amount of fault energies will be dissipated by the surge arrester, and high cost of full-controlled semiconductors. In other words, these DCCB must have enough fault interruption capability, the converters near the fault must withstand serious overcurrent, and the design of surge arrester in DCCB becomes particularly critical.
Thyristors are superior to IGBTs or IGCTs in terms of cost, rating parameters, and reliability [25]. Therefore, to overcome these shortcomings mentioned above, a novel type of DC circuit breaker based on artificial current zero-crossing is proposed in this paper. The proposed DCCB is based on thyristors, and has the advantages of effectively limiting fault current, fast reclosing, without full-controlled semiconductors and no additional pre-charging power supply. It can be better applied in HVDC grids. Section II details the basic structure and working principle of the proposed DC circuit breaker. The working process and considerations for parameter design are analyzed mathematically in section III. By establishing the model of DC circuit breaker and a multiterminal test system in section IV and V, the fault current breaking simulation is carried out to validate the feasibility and effectiveness of this topology.

II. TOPOLOGY STRUCTURE AND WORKING PRINCIPLE A. TOPOLOGY STRUCTURE
The proposed topology of DC circuit breaker are shown in Fig. 1, which is composed of ultrafast mechanical switch (K ), anti-parallel thyristor strings (T K ), inductors (L 1 , L 2 , L 0 ), mechanical switches (K 1 , K 2 ), diode strings (D 1 , D 2 ), thyristor strings (T 1 , T 2 ), mechanical switches (S 1 , S 2 ), capacitors (C 1 , C 2 ), and fast charging branches. D 1 and T 1 are anti-parallel connected, and then in series with S 1 and C 1 to form a commutation branch; similarly, another commutation branch is composed of D 2 , T 2 , S 2 , and C 2 . The two fast charging branches consist of charging resistors (r 1 , r 2 ) and charging thyristors (T r1 , T r2 ). T K is parallel connected with the ultrafast mechanical switch. Capacitors have individual paralleled surge arresters.
In Fig. 1, i dc , i K , i TK , i f are the current of converter side, the current of ultrafast mechanical switch, the current of T K , and the fault current of line side, respectively. I a is the threshold of fault current detection; u C1 , i C1 , u C2 , i C2 are corresponding capacitors' voltage and current; u K is the voltage of K , the total voltage of K and L 0 (i.e., the difference value between u C1 and u C2 ) is recorded as u.

B. OPERATION PRINCIPLES
The proposed DCCB has three basic operation modes: normal conduction mode, fault current interruption mode and breaker reclosing mode. Because of its symmetry, we take the current direction and the fault location shown in Fig.1 as an example to clarify the operation principle in this paper.
1. Normal conduction mode: When the whole HVDC system prepares to start up, the switch K , K 1 and K 2 should be closed. After turning on thyristors T r1 and T r2 , the system begins to pre-charge capacitors C 1 and C 2 , the charging process can be done through charging resistors (r 1 , r 2 ) upon energization of the DC bus side. After C 1 and C 2 are charged up to the system voltage level the charge current decreases gradually. The thyristors turn off naturally after the charge current falls below the holding current, and then close the mechanical switches S 1 and S 2 . Considering the influence of charging current on DC system, the capacitors will be charged from zero to the system voltage in tens of milliseconds with parameters designed of charging resistors. In most of the working time of DCCB, the load current flows through the following path: 2. Fault current interruption mode: The proposed topology has bidirectional interruption capability. We take a fault location shown in Fig.1 as an example, the following paragraphs will describe how to clear the fault current.
Assume that the short circuit fault occurs at t 0 , the fault current rises rapidly and reaches the threshold value I a at t 1 . Then, the control system sends the action command to the DCCB. The thyristor T 1 is triggered and K is controlled to open at the same time. The capacitor C 1 starts discharging to the fault line and feeds the fault point, which provides most of the fault current. Therefore, the amplitude and rise rate of the current at the converter side are limited, in addition, reducing the impact of the fault current on the converter station. After the short mechanical delay of K , the contacts begin to separate at t 2, resulting in arc immediately, and the distance between contacts increases gradually. After the preset arcing time, at t 3 , the thyristor string in T K whose direction is opposite to i K is turned on and thyristor T 2 is triggered, C 2 starts to discharge. Under the resonance of C 2 and L 0 , the resonant current injects into switch K branch, which makes i K decrease immediately, meanwhile, C 1 is charged. At t 4 , i K becomes zero, the resonant current continues to VOLUME 8, 2020 flow through T K , which provides enough time for K to extinguishing arc and ensure the recovery of dielectric insulation, therefore, the arc extinguishes and K breaks completely. At t 5 , the T K turns off while the direction of resonant current reverses, thus, the converter is isolated from the DC fault.
After t 5 , the current i dc starts to charge C 1 through diode D 1 ; C 2 forms a continuous current loop with the fault point. The current i dc decreases gradually during the resonant process. At t 6 , i dc drops to zero, D 1 and T 1 all turn off. At t 7 , C 2 completes discharge and i f drops to zero, D 2 and T 2 all turn off. When i dc and i f all become zero, which indicates that the DC fault current is completely cleared.
3. Breaker reclosing mode: After fault breaking, the fault transmission line needs de-ionization to restore insulation. The time interval of de-ionization is about 300 ms [7], [31], [32]. DC circuit breaker used in MMC-HVDC system should have the ability of reclosing and re-breaking after the first breaking interval of 300 ms. The prerequisite of fault current breaking is the capacitors pre-charged. When fault resistance is several-tens of ohms, or even several hundred ohms, the voltage of C 2 may be lower than U dc after fault breaking, so C 2 must be recharged quickly before reclosing operation (if the fault located on the left side of the DCCB, C 1 must be recharged). After the first break, K 2 and S 2 are controlled to open, closing K and turning on T r2 to charge C 2 up to the rated DC voltage level quickly through r 2 . After T r2 turns off naturally, S 2 is controlled to close. We can control the charging current and charging time by designing r 2 , and the recharging process can be completed before reclosing.
In order to avoid reclosing dccb under fault situation, the proposed dccb has an additional function that we can choose to test the fault before reclosing. The strategy is as follows: first, triggering thyristor T 2 . If C 2 is detected to have very small discharge current due to the characteristics of transmission line distribution parameters, the short circuit fault does not exist, then the reclosing operation can be carried out. If C 2 has a large discharge current, it shows that there is still a short circuit fault, stop reclosing and after a set time, triggering T 2 again for testing. If the fault still exists, we can judge the fault as a permanent fault and conduct repair.

III. THEORETICAL ANALYSIS AND DESIGN CONSIDERATIONS
This section will focus on analyzing the breaker's equivalent process and parameter design considerations.
The overhead lines' failure rate will be much higher than dc cables. In this paper, we take overhead lines as an example, and overhead lines can be represented to simplified R-L series models [33]- [35].
In the whole process of DCCB isolating faults, it is better that the breaker can avoid converter blocking to maintain the power transmission of the healthy area. we take the halfbridge MMC (HB-MMC) converter as an example, the analysis is carried out under the condition that the converter submodules (SMs) will not be blocked. HB-MMC can be equivalent to a discharge circuit consists of a capacitance C S , a reactance L s , and a resistance R s in series during the fault process [36]- [38]. And C s = 6 C m /N , L s = 2 L m /3, R s = 2R m /3, where N is the number of SMs in each arm, C m is the SM capacitor, L m and R m are the inductance and resistance in each arm, respectively [34], [39], [40]. The equivalent circuits of short circuit fault breaking process are shown in Fig. 2. The fault occurs at t 0 . I dc is the normal steady-state DC system current before fault. U dc is the initial steady-state voltage of C s , also represents the rated DC bus voltage. The following four stages describe the isolation process of the line fault.
After fault occurs, inductors limit fault current immediately. The fault current is fed by the DC system. AS shown in Fig.  2(a), the circuit equation can be expressed as follows: We can obtain the expression of fault current as follows: where , R L and L L are equivalent resistance and inductance of transmission line respectively, and R f is fault resistance.
The equivalent circuit is shown in Fig. 2(B). turning on T 1 and open switch K at t 1 , C 1 discharges to contribute most of the fault current which can prevent the DC bus voltage from collapsing.
According to laplace transform and node-voltage method, we can obtain: , U 1 (s) is u C1 (s), and then we can deduce the Laplacian expression of the current i K at this stage as follows: The inverse Laplace transform of i K (s), i dc (s), u C1 (s), u Cs (s) can be solved by using MATLAB, so their corresponding time domain solutions can be obtained.
As shown in Fig. 2(c), after the preset arcing time, the contacts of k have reached a safe distance. At t 3 , the discharge current of the capacitor C 2 injects into switch K in reverse direction.
We know that the current expression of LC resonance is: where U C is the initial voltage value of the capacitor.
In the equivalent circuit of this stage, the resonance of C 2 -L 0 -C 1 is superimposed on K . The value of L 0 is much smaller than L 1 and L 2 . The resonant frequency of C 2 -L 0 is high and the amplitude of resonant current is very large, so the zero-crossing time of i K is very short. In order to simplify the analysis, the resonant current injected into K can be approximately given by: where U C is the differential voltage value between u C2 (t 3 ) and u C1 (t 3 ), and u C2 (t 3 ) = U dc . From (8), the time of zerocrossing of i K can be approximately obtained.
According to Laplace transform and node-voltage method, we can obtain: So, u C2 (t) and u C1 (t) can be further derived.

D. AFTER t 5
After t 5 , K has opened and T K has turned off, the current of converter side charges C 1 , meanwhile, C 2 discharges through L 2 to the fault point. As shown in Fig. 2(d).
According to Laplace transform and loop current method for circuit of converter side, the following equation can be gotten: Hence, we can obtain u C1 (t), i dc (t), u Cs (t) and other variables.
furthermore, u 2 (t) can be given by: The voltage across the switch K can be approximately given by: After both i dc and i f become zero, the fault breaking process ends. The MOVs of capacitor are used for voltage limiting protection, and the impedance characteristic is nonlinear. This paper will not discuss it.
In MMC-HVDC system, there are relatively large bridge arm inductance, and line impedance between fault point and DC circuit breaker. Therefore, the actual inductance of fault equivalent circuit is much larger than the inductance in DC circuit breaker. The design of inductor (L 1 , L 2 ) should consider the maximum current I max that DC system and DCCB can withstand, and the maximum fault detection time t for the fault with 0 km distance. Therefore, we have: The reasonable values of C 1 , C 2 and L 0 can be obtained based on the theoretical calculation above and following design considerations: the maximum amplitude and zerocrossing time of converter side current (i dc ) must be limited; in order to ensure i K can achieve zero-crossing, the maximum amplitude of resonant current provided by C 2 -L 0 -C 1 should be 1.3-2 times the amplitude of i K , and the resonant frequency should be several hundred Hz to several kHz [41]; the capacitor value of C 1 should not be too large because of its cost.

IV. SIMULATION ANALYSIS OF FAULT BREAKING
This section aims to detail the performance of fault breaking. the simplified simulation system is depicted in fig. 3. according to the analysis in section III, the designed parameters of simulation system are as follows: U dc = 500 kV, I dc = 3 kA, N = 312, C m = 15 mF, L m = 100 mH, R m = 0.3 .
Ultrafast mechanical switch adopts vacuum switches, under the current research and development situation, the time to achieve the safe distance between contacts of switch k is set to 2 ms [6], [42], and the mechanical delay is set to 0.3 ms [43], [44]. L 1 = L 2 = 100 mH, L 0 = 2 mH, C 1 = C 2 = 100 µF. Resistors r 1 and r 2 are 200 , which can effectively control charging current and charging time.
The low-impedance (R F = 1 m ) pole-to-ground fault occurs at the connection between the DCCB and the transmission line (fault distance from DCCB to fault point is 0 km), which is the most serious fault for DCCB., The threshold current value I a is set to 1.5I dc . Fig. 4 shows the main voltage and current waveforms of dccb. the short circuit fault occurs at t 0 = 0.2 s. The fault current i f rises rapidly and reaches 4.5 kA at t 1 = 0.201 s, then, K is controlled to open and triggering T 1 . Upon T 1 is turned on, C 1 discharges and effectively restricting the growth of i dc . At t 3 = 0.203 s, turning on T 2 to discharge C 2 , the reverse current injects into K . Fig. 4(a) show the current of switch K without breaking, which aims to illustrate that the topology can produce reliable current zero-crossing in K . At t 4 = 0.20328 s, i K becomes zero, and at t 5 = 0.20383 s, i TK becomes zero. We can obtain that the thyristor T K provides a period of more than 500 µs (between t 4 and t 5 ) for K to recover its insulation with low voltage stress. Current of converter side (i dc ) drops to zero at t 6 = 0.210 s and line side fault current (i f ) becomes zero at t 7 = 0.2205 s. So, the whole process of fault breaking is completed at t 7 . In other words, the converter can be isolated from the DC fault within about 10 ms. Moreover, the fault can be completely cleared within approximately 20 ms after it occurs.
In addition, it can be seen that the converter side current i dc begins to decrease within 4 ms after the fault is detected, which means the breaking time of the proposed DCCB is 4 ms. And its maximum value is only 4.92 kA, which effectively reduces the impact of DC fault on the converter station. The capacitors C 1 and C 2 are restored to the initial voltage. The maximum current of K is 13.6 kA and the maximum voltage across it is 2.4 times as much as U dc , which requires a high insulation ability. Therefore, the multi-switch combination structure should be used.
The DCCB proposed by State Grid Corporation of China can break fault in 3 ms, which will be used in Zhangbei HVDC grid. But, it's maximum value of the fault current reaches about 13 kA with current limiting reactor of 200 mH, therefore, taking a certain design margin into consideration, MMC converter for Zhangbei is designed to withstand transient current of 100 ms up to 32 kA [21], [45]. A large number of IGBT and many technologies for improving breaking capability of IGBT are used, which leads to high costs. However, the maximum fault current of the proposed DCCB is 4.92 kA, which is less than 2 times the rated DC current. Thus, the design margin of IGBT and other related technologies can be reduced by more than half, and further reduce the cost of MMC converter stations.
According to the preceding scheme, reclosing can begin at 0.52 s. The opening of K 2 and S 2 will take a few milliseconds, then the recharge process of C 2 will begin. The voltage of C 2 under different fault resistance is shown in Fig. 5. It can be seen that the topology can quickly charge C 2 before reclosing, and has the ability of reclosing and re-breaking. Taking R f = 1 m as an example, and reclosing operation begins. In case of the transient fault, the HVDC system will quickly enter the steady-state operation mode, and the line current will be restored, as shown in Fig. 6(a). However, in the case of the permanent fault, the DCCB can break fault again immediately after reclosing, the process of re-breaking VOLUME 8, 2020  is the same as that of the previous breaking. The simulation waveform of re-breaking current is depicted in Fig. 6(b).
In order to better illustrate the current limiting effect of the proposed DCCB, we built the simulation model of the abb-dccb [13], and compared the two DCCBs. Under the condition that the parameters of the simulation system are the  same, we obtain the fault current waveforms at the converter station side of the two schemes in the process of dc line fault, as shown in Fig. 7. After the fault is detected, the ABB-DCCB starts to transfer fault current to the MB, then turn off MB after several milliseconds of fast mechanical disconnector break time. During the process, the fault current continues to increase until the MOV starts. The peak value of fault current i dc is 8.24 kA. However, once the fault is detected, the proposed DCCB starts to limit the current by discharging the capacitors, the maximum value is 4.92 kA. Therefore, the fault current i dc of the proposed DCCB is limited more quickly and greatly. It is obvious that the proposed DCCB has an effective current limiting capability.

V. SIMULATION RESULTS IN MULTI-TERMINAL HVDC SYSTEM A. TEST SYSTEM
To evaluate the basic operational performance of the proposed DCCB in HVDC system, a four-terminal MMC-HVDC test model with a DC system voltage of 500 kV is built in PSCAD/EMTDC, as shown in Fig. 8. The test model adopts HB-MMC and integrate the proposed circuit breaker.

B. RESULTS
In Fig. 8, a pole-to-ground fault f is occurs on the Line1 side of CB12 (i.e. the fault location was 0 km away from CB12) at t = 3 s.
The detailed currents in the CB12 simulation results are shown in Fig. 9(a), which indicates that the overall fault clearing time of the DCCB is 20.05 ms. The initial steady current amplitude of CB12 (i dcCB12 ) is 1kA, and the threshold current value is 1.5 times of i dcCB12 . After the fault, the peak current of converter side (i.e. i dcCB12 ) is 2.26 kA, and becomes zero at 3.0118 s. The withstand voltage of switch K in CB12 is 1140 kV, as shown in Fig. 9(b).
The currents of each line in test system are as shown in Fig. 10(a). After the fault, the currents of each converter station stabilize again after a short period of oscillation fluctuation.
As shown in Fig. 10(b), the normal DC bus voltage of the system is 500 kV, when the DC fault happens, the DC voltage decreases sharply. Only the DC bus voltage of MMC1 and MMC2 fluctuates to a certain extent. After the fault is cleared, the DC bus voltage quickly restores to the system voltage, which avoids the voltage collapse of the DC bus.
In practical engineering, in order to protect converter valves, the converter's IGBTs will be blocked when arm current exceeds a maximum threshold [46], [47]. From Fig. 10(c), it can be seen that the bridge arm current fluctuation of MMC1 is small and restores to normal quickly, which can effectively reduce the blocking probability of converter and keep the continuous operation of the healthy part of multiterminal HVDC system.

VI. CONCLUSION
In view of the shortcomings of existing DC circuit breakers and the demands of MMC-HVDC transmission system, a new type of DC circuit breaker topology based on artificial current zero-crossing is proposed.
The unique advantages of the proposed DC circuit breaker are as follow: it can quickly limit the fault current on the side of the converter station, significantly reduce the impact of dc fault on the converter, reduce the design capacity of converter valves to a certain extent, reduce the blocking probability of converter, and reduce the cost. The clamping effect of capacitors can avoid voltage collapse of DC bus when short circuit fault occurs. It realizes fast reclosing and has the ability of identifying whether the faults are cleared before reclosing, which can avoid the effect of fault on DC system again.
Firstly, the operation principle of the topology is detailed, and the theoretical analysis of the working process is presented. Then, aiming at the demands of MMC-HVDC grids, the basic operational performance of DCCB is simulated and verified by PSCAD/EMTDC.
The topology scheme in this paper provides a new idea for the research of DC circuit breaker and has positive significance for the construction of HVDC power system. Future work will analyze the application of the proposed DC circuit breaker in different MMC-HVDC system structures and different fault types. In addition, a cost-benefit analysis will be investigated in order to confirm the economic feasibility of its application in meshed MMC-HVDC grids. LIYE XIAO was born in China, in 1966. He received the M.S. and Ph.D. degrees from the Institute of Electrical Engineering, Chinese Academy of Sciences, in 1992 and 1995, respectively. He is currently a Professor with the Institute of Electrical Engineering, Chinese Academy of Sciences. His research interests include smart grid, application of superconductivity, and new materials in power and energy. VOLUME 8, 2020